SystemZInstrFP.td revision 055ac429cc995c78be4aee552ea51be7b32efbf1
1//==- SystemZInstrFP.td - Floating-point SystemZ instructions --*- tblgen-*-==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Control-flow instructions 12//===----------------------------------------------------------------------===// 13 14// C's ?: operator for floating-point operands. 15def SelectF32 : SelectWrapper<FP32>; 16def SelectF64 : SelectWrapper<FP64>; 17def SelectF128 : SelectWrapper<FP128>; 18 19//===----------------------------------------------------------------------===// 20// Move instructions 21//===----------------------------------------------------------------------===// 22 23// Load zero. 24let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 25 def LZER : InherentRRE<"lzer", 0xB374, FP32, (fpimm0)>; 26 def LZDR : InherentRRE<"lzdr", 0xB375, FP64, (fpimm0)>; 27 def LZXR : InherentRRE<"lzxr", 0xB376, FP128, (fpimm0)>; 28} 29 30// Moves between two floating-point registers. 31let neverHasSideEffects = 1 in { 32 def LER : UnaryRR <"ler", 0x38, null_frag, FP32, FP32>; 33 def LDR : UnaryRR <"ldr", 0x28, null_frag, FP64, FP64>; 34 def LXR : UnaryRRE<"lxr", 0xB365, null_frag, FP128, FP128>; 35} 36 37// Moves between 64-bit integer and floating-point registers. 38def LGDR : UnaryRRE<"lgdr", 0xB3CD, bitconvert, GR64, FP64>; 39def LDGR : UnaryRRE<"ldgr", 0xB3C1, bitconvert, FP64, GR64>; 40 41// fcopysign with an FP32 result. 42let isCodeGenOnly = 1 in { 43 def CPSDRss : BinaryRRF<"cpsdr", 0xB372, fcopysign, FP32, FP32>; 44 def CPSDRsd : BinaryRRF<"cpsdr", 0xB372, fcopysign, FP32, FP64>; 45} 46 47// The sign of an FP128 is in the high register. 48def : Pat<(fcopysign FP32:$src1, FP128:$src2), 49 (CPSDRsd FP32:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_high))>; 50 51// fcopysign with an FP64 result. 52let isCodeGenOnly = 1 in 53 def CPSDRds : BinaryRRF<"cpsdr", 0xB372, fcopysign, FP64, FP32>; 54def CPSDRdd : BinaryRRF<"cpsdr", 0xB372, fcopysign, FP64, FP64>; 55 56// The sign of an FP128 is in the high register. 57def : Pat<(fcopysign FP64:$src1, FP128:$src2), 58 (CPSDRdd FP64:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_high))>; 59 60// fcopysign with an FP128 result. Use "upper" as the high half and leave 61// the low half as-is. 62class CopySign128<RegisterOperand cls, dag upper> 63 : Pat<(fcopysign FP128:$src1, cls:$src2), 64 (INSERT_SUBREG FP128:$src1, upper, subreg_high)>; 65 66def : CopySign128<FP32, (CPSDRds (EXTRACT_SUBREG FP128:$src1, subreg_high), 67 FP32:$src2)>; 68def : CopySign128<FP64, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_high), 69 FP64:$src2)>; 70def : CopySign128<FP128, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_high), 71 (EXTRACT_SUBREG FP128:$src2, subreg_high))>; 72 73//===----------------------------------------------------------------------===// 74// Load instructions 75//===----------------------------------------------------------------------===// 76 77let canFoldAsLoad = 1, SimpleBDXLoad = 1 in { 78 defm LE : UnaryRXPair<"le", 0x78, 0xED64, load, FP32>; 79 defm LD : UnaryRXPair<"ld", 0x68, 0xED65, load, FP64>; 80 81 // These instructions are split after register allocation, so we don't 82 // want a custom inserter. 83 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 84 def LX : Pseudo<(outs FP128:$dst), (ins bdxaddr20only128:$src), 85 [(set FP128:$dst, (load bdxaddr20only128:$src))]>; 86 } 87} 88 89//===----------------------------------------------------------------------===// 90// Store instructions 91//===----------------------------------------------------------------------===// 92 93let SimpleBDXStore = 1 in { 94 defm STE : StoreRXPair<"ste", 0x70, 0xED66, store, FP32>; 95 defm STD : StoreRXPair<"std", 0x60, 0xED67, store, FP64>; 96 97 // These instructions are split after register allocation, so we don't 98 // want a custom inserter. 99 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 100 def STX : Pseudo<(outs), (ins FP128:$src, bdxaddr20only128:$dst), 101 [(store FP128:$src, bdxaddr20only128:$dst)]>; 102 } 103} 104 105//===----------------------------------------------------------------------===// 106// Conversion instructions 107//===----------------------------------------------------------------------===// 108 109// Convert floating-point values to narrower representations, rounding 110// according to the current mode. The destination of LEXBR and LDXBR 111// is a 128-bit value, but only the first register of the pair is used. 112def LEDBR : UnaryRRE<"ledbr", 0xB344, fround, FP32, FP64>; 113def LEXBR : UnaryRRE<"lexbr", 0xB346, null_frag, FP128, FP128>; 114def LDXBR : UnaryRRE<"ldxbr", 0xB345, null_frag, FP128, FP128>; 115 116def : Pat<(f32 (fround FP128:$src)), 117 (EXTRACT_SUBREG (LEXBR FP128:$src), subreg_32bit)>; 118def : Pat<(f64 (fround FP128:$src)), 119 (EXTRACT_SUBREG (LDXBR FP128:$src), subreg_high)>; 120 121// Extend register floating-point values to wider representations. 122def LDEBR : UnaryRRE<"ldebr", 0xB304, fextend, FP64, FP32>; 123def LXEBR : UnaryRRE<"lxebr", 0xB306, fextend, FP128, FP32>; 124def LXDBR : UnaryRRE<"lxdbr", 0xB305, fextend, FP128, FP64>; 125 126// Extend memory floating-point values to wider representations. 127def LDEB : UnaryRXE<"ldeb", 0xED04, extloadf32, FP64>; 128def LXEB : UnaryRXE<"lxeb", 0xED06, extloadf32, FP128>; 129def LXDB : UnaryRXE<"lxdb", 0xED05, extloadf64, FP128>; 130 131// Convert a signed integer register value to a floating-point one. 132let Defs = [PSW] in { 133 def CEFBR : UnaryRRE<"cefbr", 0xB394, sint_to_fp, FP32, GR32>; 134 def CDFBR : UnaryRRE<"cdfbr", 0xB395, sint_to_fp, FP64, GR32>; 135 def CXFBR : UnaryRRE<"cxfbr", 0xB396, sint_to_fp, FP128, GR32>; 136 137 def CEGBR : UnaryRRE<"cegbr", 0xB3A4, sint_to_fp, FP32, GR64>; 138 def CDGBR : UnaryRRE<"cdgbr", 0xB3A5, sint_to_fp, FP64, GR64>; 139 def CXGBR : UnaryRRE<"cxgbr", 0xB3A6, sint_to_fp, FP128, GR64>; 140} 141 142// Convert a floating-point register value to a signed integer value, 143// with the second operand (modifier M3) specifying the rounding mode. 144let Defs = [PSW] in { 145 def CFEBR : UnaryRRF<"cfebr", 0xB398, GR32, FP32>; 146 def CFDBR : UnaryRRF<"cfdbr", 0xB399, GR32, FP64>; 147 def CFXBR : UnaryRRF<"cfxbr", 0xB39A, GR32, FP128>; 148 149 def CGEBR : UnaryRRF<"cgebr", 0xB3A8, GR64, FP32>; 150 def CGDBR : UnaryRRF<"cgdbr", 0xB3A9, GR64, FP64>; 151 def CGXBR : UnaryRRF<"cgxbr", 0xB3AA, GR64, FP128>; 152} 153 154// fp_to_sint always rounds towards zero, which is modifier value 5. 155def : Pat<(i32 (fp_to_sint FP32:$src)), (CFEBR 5, FP32:$src)>; 156def : Pat<(i32 (fp_to_sint FP64:$src)), (CFDBR 5, FP64:$src)>; 157def : Pat<(i32 (fp_to_sint FP128:$src)), (CFXBR 5, FP128:$src)>; 158 159def : Pat<(i64 (fp_to_sint FP32:$src)), (CGEBR 5, FP32:$src)>; 160def : Pat<(i64 (fp_to_sint FP64:$src)), (CGDBR 5, FP64:$src)>; 161def : Pat<(i64 (fp_to_sint FP128:$src)), (CGXBR 5, FP128:$src)>; 162 163//===----------------------------------------------------------------------===// 164// Unary arithmetic 165//===----------------------------------------------------------------------===// 166 167// Negation (Load Complement). 168let Defs = [PSW] in { 169 def LCEBR : UnaryRRE<"lcebr", 0xB303, fneg, FP32, FP32>; 170 def LCDBR : UnaryRRE<"lcdbr", 0xB313, fneg, FP64, FP64>; 171 def LCXBR : UnaryRRE<"lcxbr", 0xB343, fneg, FP128, FP128>; 172} 173 174// Absolute value (Load Positive). 175let Defs = [PSW] in { 176 def LPEBR : UnaryRRE<"lpebr", 0xB300, fabs, FP32, FP32>; 177 def LPDBR : UnaryRRE<"lpdbr", 0xB310, fabs, FP64, FP64>; 178 def LPXBR : UnaryRRE<"lpxbr", 0xB340, fabs, FP128, FP128>; 179} 180 181// Negative absolute value (Load Negative). 182let Defs = [PSW] in { 183 def LNEBR : UnaryRRE<"lnebr", 0xB301, fnabs, FP32, FP32>; 184 def LNDBR : UnaryRRE<"lndbr", 0xB311, fnabs, FP64, FP64>; 185 def LNXBR : UnaryRRE<"lnxbr", 0xB341, fnabs, FP128, FP128>; 186} 187 188// Square root. 189def SQEBR : UnaryRRE<"sqebr", 0xB314, fsqrt, FP32, FP32>; 190def SQDBR : UnaryRRE<"sqdbr", 0xB315, fsqrt, FP64, FP64>; 191def SQXBR : UnaryRRE<"sqxbr", 0xB316, fsqrt, FP128, FP128>; 192 193def SQEB : UnaryRXE<"sqeb", 0xED14, loadu<fsqrt>, FP32>; 194def SQDB : UnaryRXE<"sqdb", 0xED15, loadu<fsqrt>, FP64>; 195 196// Round to an integer, with the second operand (modifier M3) specifying 197// the rounding mode. 198// 199// These forms always check for inexact conditions. z196 added versions 200// that allow this to suppressed (as for fnearbyint), but we don't yet 201// support -march=z196. 202let Defs = [PSW] in { 203 def FIEBR : UnaryRRF<"fiebr", 0xB357, FP32, FP32>; 204 def FIDBR : UnaryRRF<"fidbr", 0xB35F, FP64, FP64>; 205 def FIXBR : UnaryRRF<"fixbr", 0xB347, FP128, FP128>; 206} 207 208// frint rounds according to the current mode (modifier 0) and detects 209// inexact conditions. 210def : Pat<(frint FP32:$src), (FIEBR 0, FP32:$src)>; 211def : Pat<(frint FP64:$src), (FIDBR 0, FP64:$src)>; 212def : Pat<(frint FP128:$src), (FIXBR 0, FP128:$src)>; 213 214//===----------------------------------------------------------------------===// 215// Binary arithmetic 216//===----------------------------------------------------------------------===// 217 218// Addition. 219let Defs = [PSW] in { 220 let isCommutable = 1 in { 221 def AEBR : BinaryRRE<"aebr", 0xB30A, fadd, FP32, FP32>; 222 def ADBR : BinaryRRE<"adbr", 0xB31A, fadd, FP64, FP64>; 223 def AXBR : BinaryRRE<"axbr", 0xB34A, fadd, FP128, FP128>; 224 } 225 def AEB : BinaryRXE<"aeb", 0xED0A, fadd, FP32, load>; 226 def ADB : BinaryRXE<"adb", 0xED1A, fadd, FP64, load>; 227} 228 229// Subtraction. 230let Defs = [PSW] in { 231 def SEBR : BinaryRRE<"sebr", 0xB30B, fsub, FP32, FP32>; 232 def SDBR : BinaryRRE<"sdbr", 0xB31B, fsub, FP64, FP64>; 233 def SXBR : BinaryRRE<"sxbr", 0xB34B, fsub, FP128, FP128>; 234 235 def SEB : BinaryRXE<"seb", 0xED0B, fsub, FP32, load>; 236 def SDB : BinaryRXE<"sdb", 0xED1B, fsub, FP64, load>; 237} 238 239// Multiplication. 240let isCommutable = 1 in { 241 def MEEBR : BinaryRRE<"meebr", 0xB317, fmul, FP32, FP32>; 242 def MDBR : BinaryRRE<"mdbr", 0xB31C, fmul, FP64, FP64>; 243 def MXBR : BinaryRRE<"mxbr", 0xB34C, fmul, FP128, FP128>; 244} 245def MEEB : BinaryRXE<"meeb", 0xED17, fmul, FP32, load>; 246def MDB : BinaryRXE<"mdb", 0xED1C, fmul, FP64, load>; 247 248// f64 multiplication of two FP32 registers. 249def MDEBR : BinaryRRE<"mdebr", 0xB30C, null_frag, FP64, FP32>; 250def : Pat<(fmul (f64 (fextend FP32:$src1)), (f64 (fextend FP32:$src2))), 251 (MDEBR (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 252 FP32:$src1, subreg_32bit), FP32:$src2)>; 253 254// f64 multiplication of an FP32 register and an f32 memory. 255def MDEB : BinaryRXE<"mdeb", 0xED0C, null_frag, FP64, load>; 256def : Pat<(fmul (f64 (fextend FP32:$src1)), 257 (f64 (extloadf32 bdxaddr12only:$addr))), 258 (MDEB (INSERT_SUBREG (f64 (IMPLICIT_DEF)), FP32:$src1, subreg_32bit), 259 bdxaddr12only:$addr)>; 260 261// f128 multiplication of two FP64 registers. 262def MXDBR : BinaryRRE<"mxdbr", 0xB307, null_frag, FP128, FP64>; 263def : Pat<(fmul (f128 (fextend FP64:$src1)), (f128 (fextend FP64:$src2))), 264 (MXDBR (INSERT_SUBREG (f128 (IMPLICIT_DEF)), 265 FP64:$src1, subreg_high), FP64:$src2)>; 266 267// f128 multiplication of an FP64 register and an f64 memory. 268def MXDB : BinaryRXE<"mxdb", 0xED07, null_frag, FP128, load>; 269def : Pat<(fmul (f128 (fextend FP64:$src1)), 270 (f128 (extloadf64 bdxaddr12only:$addr))), 271 (MXDB (INSERT_SUBREG (f128 (IMPLICIT_DEF)), FP64:$src1, subreg_high), 272 bdxaddr12only:$addr)>; 273 274// Fused multiply-add. 275def MAEBR : TernaryRRD<"maebr", 0xB30E, z_fma, FP32>; 276def MADBR : TernaryRRD<"madbr", 0xB31E, z_fma, FP64>; 277 278def MAEB : TernaryRXF<"maeb", 0xED0E, z_fma, FP32, load>; 279def MADB : TernaryRXF<"madb", 0xED1E, z_fma, FP64, load>; 280 281// Fused multiply-subtract. 282def MSEBR : TernaryRRD<"msebr", 0xB30F, z_fms, FP32>; 283def MSDBR : TernaryRRD<"msdbr", 0xB31F, z_fms, FP64>; 284 285def MSEB : TernaryRXF<"mseb", 0xED0F, z_fms, FP32, load>; 286def MSDB : TernaryRXF<"msdb", 0xED1F, z_fms, FP64, load>; 287 288// Division. 289def DEBR : BinaryRRE<"debr", 0xB30D, fdiv, FP32, FP32>; 290def DDBR : BinaryRRE<"ddbr", 0xB31D, fdiv, FP64, FP64>; 291def DXBR : BinaryRRE<"dxbr", 0xB34D, fdiv, FP128, FP128>; 292 293def DEB : BinaryRXE<"deb", 0xED0D, fdiv, FP32, load>; 294def DDB : BinaryRXE<"ddb", 0xED1D, fdiv, FP64, load>; 295 296//===----------------------------------------------------------------------===// 297// Comparisons 298//===----------------------------------------------------------------------===// 299 300let Defs = [PSW] in { 301 def CEBR : CompareRRE<"cebr", 0xB309, z_cmp, FP32, FP32>; 302 def CDBR : CompareRRE<"cdbr", 0xB319, z_cmp, FP64, FP64>; 303 def CXBR : CompareRRE<"cxbr", 0xB349, z_cmp, FP128, FP128>; 304 305 def CEB : CompareRXE<"ceb", 0xED09, z_cmp, FP32, load>; 306 def CDB : CompareRXE<"cdb", 0xED19, z_cmp, FP64, load>; 307} 308 309//===----------------------------------------------------------------------===// 310// Peepholes 311//===----------------------------------------------------------------------===// 312 313def : Pat<(f32 fpimmneg0), (LCEBR (LZER))>; 314def : Pat<(f64 fpimmneg0), (LCDBR (LZDR))>; 315def : Pat<(f128 fpimmneg0), (LCXBR (LZXR))>; 316