SystemZInstrFP.td revision 1d0ec0b4fc948f437b3ffbbf4b7c47ca5cd971fd 
1//===- SystemZInstrFP.td - SystemZ FP Instruction defs --------*- tblgen-*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source 
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the SystemZ (binary) floating point instructions in 
11// TableGen format.
12//
13//===----------------------------------------------------------------------===//
14
15// FIXME: multiclassify!
16
17//===----------------------------------------------------------------------===//
18// Move Instructions
19
20let neverHasSideEffects = 1 in {
21def FMOV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
22                      "ler\t{$dst, $src}",
23                      []>;
24def FMOV64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
25                      "ldr\t{$dst, $src}",
26                      []>;
27}
28
29let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
30def FMOV32rm  : Pseudo<(outs FP32:$dst), (ins rriaddr12:$src),
31                      "le\t{$dst, $src}",
32                      [(set FP32:$dst, (load rriaddr12:$src))]>;
33def FMOV32rmy : Pseudo<(outs FP32:$dst), (ins rriaddr:$src),
34                      "ley\t{$dst, $src}",
35                      [(set FP32:$dst, (load rriaddr:$src))]>;
36def FMOV64rm  : Pseudo<(outs FP64:$dst), (ins rriaddr12:$src),
37                      "ld\t{$dst, $src}",
38                      [(set FP64:$dst, (load rriaddr12:$src))]>;
39def FMOV64rmy : Pseudo<(outs FP64:$dst), (ins rriaddr:$src),
40                      "ldy\t{$dst, $src}",
41                      [(set FP64:$dst, (load rriaddr:$src))]>;
42}
43
44def FMOV32mr  : Pseudo<(outs), (ins rriaddr12:$dst, FP32:$src),
45                       "ste\t{$src, $dst}",
46                       [(store FP32:$src, rriaddr12:$dst)]>;
47def FMOV32mry : Pseudo<(outs), (ins rriaddr:$dst, FP32:$src),
48                       "stey\t{$src, $dst}",
49                       [(store FP32:$src, rriaddr:$dst)]>;
50def FMOV64mr  : Pseudo<(outs), (ins rriaddr12:$dst, FP64:$src),
51                       "std\t{$src, $dst}",
52                       [(store FP64:$src, rriaddr12:$dst)]>;
53def FMOV64mry : Pseudo<(outs), (ins rriaddr:$dst, FP64:$src),
54                       "stdy\t{$src, $dst}",
55                       [(store FP64:$src, rriaddr:$dst)]>;
56
57//===----------------------------------------------------------------------===//
58// Arithmetic Instructions
59
60let isTwoAddress = 1 in {
61
62let isCommutable = 1 in { // X = ADD Y, Z  == X = ADD Z, Y
63def FADD32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
64                       "aebr\t{$dst, $src2}",
65                       [(set FP32:$dst, (fadd FP32:$src1, FP32:$src2))]>;
66def FADD64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
67                       "adbr\t{$dst, $src2}",
68                       [(set FP64:$dst, (fadd FP64:$src1, FP64:$src2))]>;
69}
70
71def FADD32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
72                       "aeb\t{$dst, $src2}",
73                       [(set FP32:$dst, (fadd FP32:$src1, (load rriaddr:$src2)))]>;
74def FADD64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
75                       "adb\t{$dst, $src2}",
76                       [(set FP64:$dst, (fadd FP64:$src1, (load rriaddr:$src2)))]>;
77
78def FSUB32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
79                       "sebr\t{$dst, $src2}",
80                       [(set FP32:$dst, (fsub FP32:$src1, FP32:$src2))]>;
81def FSUB64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
82                       "sdbr\t{$dst, $src2}",
83                       [(set FP64:$dst, (fsub FP64:$src1, FP64:$src2))]>;
84
85def FSUB32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
86                       "seb\t{$dst, $src2}",
87                       [(set FP32:$dst, (fsub FP32:$src1, (load rriaddr:$src2)))]>;
88def FSUB64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
89                       "sdb\t{$dst, $src2}",
90                       [(set FP64:$dst, (fsub FP64:$src1, (load rriaddr:$src2)))]>;
91
92let isCommutable = 1 in { // X = MUL Y, Z  == X = MUL Z, Y
93def FMUL32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
94                       "meebr\t{$dst, $src2}",
95                       [(set FP32:$dst, (fmul FP32:$src1, FP32:$src2))]>;
96def FMUL64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
97                       "mdbr\t{$dst, $src2}",
98                       [(set FP64:$dst, (fmul FP64:$src1, FP64:$src2))]>;
99}
100
101def FMUL32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
102                       "meeb\t{$dst, $src2}",
103                       [(set FP32:$dst, (fmul FP32:$src1, (load rriaddr:$src2)))]>;
104def FMUL64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
105                       "mdb\t{$dst, $src2}",
106                       [(set FP64:$dst, (fmul FP64:$src1, (load rriaddr:$src2)))]>;
107
108def FDIV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
109                       "debr\t{$dst, $src2}",
110                       [(set FP32:$dst, (fdiv FP32:$src1, FP32:$src2))]>;
111def FDIV64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
112                       "ddbr\t{$dst, $src2}",
113                       [(set FP64:$dst, (fdiv FP64:$src1, FP64:$src2))]>;
114
115def FDIV32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
116                       "deb\t{$dst, $src2}",
117                       [(set FP32:$dst, (fdiv FP32:$src1, (load rriaddr:$src2)))]>;
118def FDIV64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
119                       "ddb\t{$dst, $src2}",
120                       [(set FP64:$dst, (fdiv FP64:$src1, (load rriaddr:$src2)))]>;
121
122} // isTwoAddress = 1
123
124def FROUND64r32 : Pseudo<(outs FP32:$dst), (ins FP64:$src),
125                         "ledbr\t{$dst, $src}",
126                         [(set FP32:$dst, (fround FP64:$src))]>;
127
128def FCONVFP32   : Pseudo<(outs FP32:$dst), (ins GR32:$src),
129                         "cefbr\t{$dst, $src}",
130                         [(set FP32:$dst, (sint_to_fp GR32:$src))]>;
131def FCONVFP32r64: Pseudo<(outs FP32:$dst), (ins GR64:$src),
132                         "cegbr\t{$dst, $src}",
133                         [(set FP32:$dst, (sint_to_fp GR64:$src))]>;
134
135def FCONVFP64r32: Pseudo<(outs FP64:$dst), (ins GR32:$src),
136                         "cdfbr\t{$dst, $src}",
137                         [(set FP64:$dst, (sint_to_fp GR32:$src))]>;
138
139def FCONVFP64   : Pseudo<(outs FP64:$dst), (ins GR64:$src),
140                         "cdgbr\t{$dst, $src}",
141                         [(set FP64:$dst, (sint_to_fp GR64:$src))]>;
142
143//===----------------------------------------------------------------------===//
144// Test instructions (like AND but do not produce any result)
145
146// Integer comparisons
147let Defs = [PSW] in {
148def FCMP32rr : Pseudo<(outs), (ins FP32:$src1, FP32:$src2),
149                      "cebr\t$src1, $src2",
150                      [(SystemZcmp FP32:$src1, FP32:$src2), (implicit PSW)]>;
151def FCMP64rr : Pseudo<(outs), (ins FP64:$src1, FP64:$src2),
152                      "cdbr\t$src1, $src2",
153                      [(SystemZcmp FP64:$src1, FP64:$src2), (implicit PSW)]>;
154
155def FCMP32rm : Pseudo<(outs), (ins FP32:$src1, rriaddr:$src2),
156                      "ceb\t$src1, $src2",
157                      [(SystemZcmp FP32:$src1, (load rriaddr:$src2)),
158                       (implicit PSW)]>;
159def FCMP64rm : Pseudo<(outs), (ins FP64:$src1, rriaddr:$src2),
160                      "cdb\t$src1, $src2",
161                      [(SystemZcmp FP64:$src1, (load rriaddr:$src2)),
162                       (implicit PSW)]>;
163} // Defs = [PSW]
164