SystemZInstrFP.td revision 299dc78d67c63d9ea365a3b39a418998c26096ab
1//===- SystemZInstrFP.td - SystemZ FP Instruction defs --------*- tblgen-*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the SystemZ (binary) floating point instructions in 11// TableGen format. 12// 13//===----------------------------------------------------------------------===// 14 15// FIXME: multiclassify! 16 17let usesCustomDAGSchedInserter = 1 in { 18 def SelectF32 : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, i8imm:$cc), 19 "# SelectF32 PSEUDO", 20 [(set FP32:$dst, 21 (SystemZselect FP32:$src1, FP32:$src2, imm:$cc))]>; 22 def SelectF64 : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, i8imm:$cc), 23 "# SelectF64 PSEUDO", 24 [(set FP64:$dst, 25 (SystemZselect FP64:$src1, FP64:$src2, imm:$cc))]>; 26} 27 28//===----------------------------------------------------------------------===// 29// Move Instructions 30 31let neverHasSideEffects = 1 in { 32def FMOV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src), 33 "ler\t{$dst, $src}", 34 []>; 35def FMOV64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src), 36 "ldr\t{$dst, $src}", 37 []>; 38} 39 40let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in { 41def FMOV32rm : Pseudo<(outs FP32:$dst), (ins rriaddr12:$src), 42 "le\t{$dst, $src}", 43 [(set FP32:$dst, (load rriaddr12:$src))]>; 44def FMOV32rmy : Pseudo<(outs FP32:$dst), (ins rriaddr:$src), 45 "ley\t{$dst, $src}", 46 [(set FP32:$dst, (load rriaddr:$src))]>; 47def FMOV64rm : Pseudo<(outs FP64:$dst), (ins rriaddr12:$src), 48 "ld\t{$dst, $src}", 49 [(set FP64:$dst, (load rriaddr12:$src))]>; 50def FMOV64rmy : Pseudo<(outs FP64:$dst), (ins rriaddr:$src), 51 "ldy\t{$dst, $src}", 52 [(set FP64:$dst, (load rriaddr:$src))]>; 53} 54 55def FMOV32mr : Pseudo<(outs), (ins rriaddr12:$dst, FP32:$src), 56 "ste\t{$src, $dst}", 57 [(store FP32:$src, rriaddr12:$dst)]>; 58def FMOV32mry : Pseudo<(outs), (ins rriaddr:$dst, FP32:$src), 59 "stey\t{$src, $dst}", 60 [(store FP32:$src, rriaddr:$dst)]>; 61def FMOV64mr : Pseudo<(outs), (ins rriaddr12:$dst, FP64:$src), 62 "std\t{$src, $dst}", 63 [(store FP64:$src, rriaddr12:$dst)]>; 64def FMOV64mry : Pseudo<(outs), (ins rriaddr:$dst, FP64:$src), 65 "stdy\t{$src, $dst}", 66 [(store FP64:$src, rriaddr:$dst)]>; 67 68//===----------------------------------------------------------------------===// 69// Arithmetic Instructions 70 71 72let isTwoAddress = 1 in { 73let Defs = [PSW] in { 74 75def FNEG32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src), 76 "lcebr\t{$dst}", 77 [(set FP32:$dst, (fneg FP32:$src)), 78 (implicit PSW)]>; 79def FNEG64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src), 80 "lcdbr\t{$dst}", 81 [(set FP64:$dst, (fneg FP64:$src)), 82 (implicit PSW)]>; 83 84// FIXME: Add peephole for fneg(fabs) => load negative 85 86def FABS32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src), 87 "lpebr\t{$dst}", 88 [(set FP32:$dst, (fabs FP32:$src)), 89 (implicit PSW)]>; 90def FABS64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src), 91 "lpdbr\t{$dst}", 92 [(set FP64:$dst, (fabs FP64:$src)), 93 (implicit PSW)]>; 94 95let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y 96def FADD32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2), 97 "aebr\t{$dst, $src2}", 98 [(set FP32:$dst, (fadd FP32:$src1, FP32:$src2)), 99 (implicit PSW)]>; 100def FADD64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2), 101 "adbr\t{$dst, $src2}", 102 [(set FP64:$dst, (fadd FP64:$src1, FP64:$src2)), 103 (implicit PSW)]>; 104} 105 106def FADD32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2), 107 "aeb\t{$dst, $src2}", 108 [(set FP32:$dst, (fadd FP32:$src1, (load rriaddr:$src2))), 109 (implicit PSW)]>; 110def FADD64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2), 111 "adb\t{$dst, $src2}", 112 [(set FP64:$dst, (fadd FP64:$src1, (load rriaddr:$src2))), 113 (implicit PSW)]>; 114 115def FSUB32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2), 116 "sebr\t{$dst, $src2}", 117 [(set FP32:$dst, (fsub FP32:$src1, FP32:$src2)), 118 (implicit PSW)]>; 119def FSUB64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2), 120 "sdbr\t{$dst, $src2}", 121 [(set FP64:$dst, (fsub FP64:$src1, FP64:$src2)), 122 (implicit PSW)]>; 123 124def FSUB32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2), 125 "seb\t{$dst, $src2}", 126 [(set FP32:$dst, (fsub FP32:$src1, (load rriaddr:$src2))), 127 (implicit PSW)]>; 128def FSUB64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2), 129 "sdb\t{$dst, $src2}", 130 [(set FP64:$dst, (fsub FP64:$src1, (load rriaddr:$src2))), 131 (implicit PSW)]>; 132} // Defs = [PSW] 133 134let isCommutable = 1 in { // X = MUL Y, Z == X = MUL Z, Y 135def FMUL32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2), 136 "meebr\t{$dst, $src2}", 137 [(set FP32:$dst, (fmul FP32:$src1, FP32:$src2))]>; 138def FMUL64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2), 139 "mdbr\t{$dst, $src2}", 140 [(set FP64:$dst, (fmul FP64:$src1, FP64:$src2))]>; 141} 142 143def FMUL32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2), 144 "meeb\t{$dst, $src2}", 145 [(set FP32:$dst, (fmul FP32:$src1, (load rriaddr:$src2)))]>; 146def FMUL64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2), 147 "mdb\t{$dst, $src2}", 148 [(set FP64:$dst, (fmul FP64:$src1, (load rriaddr:$src2)))]>; 149 150def FDIV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2), 151 "debr\t{$dst, $src2}", 152 [(set FP32:$dst, (fdiv FP32:$src1, FP32:$src2))]>; 153def FDIV64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2), 154 "ddbr\t{$dst, $src2}", 155 [(set FP64:$dst, (fdiv FP64:$src1, FP64:$src2))]>; 156 157def FDIV32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2), 158 "deb\t{$dst, $src2}", 159 [(set FP32:$dst, (fdiv FP32:$src1, (load rriaddr:$src2)))]>; 160def FDIV64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2), 161 "ddb\t{$dst, $src2}", 162 [(set FP64:$dst, (fdiv FP64:$src1, (load rriaddr:$src2)))]>; 163 164} // isTwoAddress = 1 165 166def FROUND64r32 : Pseudo<(outs FP32:$dst), (ins FP64:$src), 167 "ledbr\t{$dst, $src}", 168 [(set FP32:$dst, (fround FP64:$src))]>; 169 170// FIXME: memory variant 171def FEXT32r64 : Pseudo<(outs FP64:$dst), (ins FP32:$src), 172 "ldebr\t{$dst, $src}", 173 [(set FP64:$dst, (fextend FP32:$src))]>; 174 175let Defs = [PSW] in { 176def FCONVFP32 : Pseudo<(outs FP32:$dst), (ins GR32:$src), 177 "cefbr\t{$dst, $src}", 178 [(set FP32:$dst, (sint_to_fp GR32:$src)), 179 (implicit PSW)]>; 180def FCONVFP32r64: Pseudo<(outs FP32:$dst), (ins GR64:$src), 181 "cegbr\t{$dst, $src}", 182 [(set FP32:$dst, (sint_to_fp GR64:$src)), 183 (implicit PSW)]>; 184 185def FCONVFP64r32: Pseudo<(outs FP64:$dst), (ins GR32:$src), 186 "cdfbr\t{$dst, $src}", 187 [(set FP64:$dst, (sint_to_fp GR32:$src)), 188 (implicit PSW)]>; 189def FCONVFP64 : Pseudo<(outs FP64:$dst), (ins GR64:$src), 190 "cdgbr\t{$dst, $src}", 191 [(set FP64:$dst, (sint_to_fp GR64:$src)), 192 (implicit PSW)]>; 193 194def FCONVGR32 : Pseudo<(outs GR32:$dst), (ins FP32:$src), 195 "cfebr\t{$dst, $src}", 196 [(set GR32:$dst, (fp_to_sint FP32:$src)), 197 (implicit PSW)]>; 198def FCONVGR32r64: Pseudo<(outs GR32:$dst), (ins FP64:$src), 199 "cgebr\t{$dst, $src}", 200 [(set GR32:$dst, (fp_to_sint FP64:$src)), 201 (implicit PSW)]>; 202 203def FCONVGR64r32: Pseudo<(outs GR64:$dst), (ins FP32:$src), 204 "cfdbr\t{$dst, $src}", 205 [(set GR64:$dst, (fp_to_sint FP32:$src)), 206 (implicit PSW)]>; 207def FCONVGR64 : Pseudo<(outs GR64:$dst), (ins FP64:$src), 208 "cgdbr\t{$dst, $src}", 209 [(set GR64:$dst, (fp_to_sint FP64:$src)), 210 (implicit PSW)]>; 211} // Defs = [PSW] 212 213//===----------------------------------------------------------------------===// 214// Test instructions (like AND but do not produce any result) 215 216// Integer comparisons 217let Defs = [PSW] in { 218def FCMP32rr : Pseudo<(outs), (ins FP32:$src1, FP32:$src2), 219 "cebr\t$src1, $src2", 220 [(SystemZcmp FP32:$src1, FP32:$src2), (implicit PSW)]>; 221def FCMP64rr : Pseudo<(outs), (ins FP64:$src1, FP64:$src2), 222 "cdbr\t$src1, $src2", 223 [(SystemZcmp FP64:$src1, FP64:$src2), (implicit PSW)]>; 224 225def FCMP32rm : Pseudo<(outs), (ins FP32:$src1, rriaddr:$src2), 226 "ceb\t$src1, $src2", 227 [(SystemZcmp FP32:$src1, (load rriaddr:$src2)), 228 (implicit PSW)]>; 229def FCMP64rm : Pseudo<(outs), (ins FP64:$src1, rriaddr:$src2), 230 "cdb\t$src1, $src2", 231 [(SystemZcmp FP64:$src1, (load rriaddr:$src2)), 232 (implicit PSW)]>; 233} // Defs = [PSW] 234