SystemZInstrFP.td revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338
1//==- SystemZInstrFP.td - Floating-point SystemZ instructions --*- tblgen-*-==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Select instructions 12//===----------------------------------------------------------------------===// 13 14// C's ?: operator for floating-point operands. 15def SelectF32 : SelectWrapper<FP32>; 16def SelectF64 : SelectWrapper<FP64>; 17def SelectF128 : SelectWrapper<FP128>; 18 19defm CondStoreF32 : CondStores<FP32, nonvolatile_store, 20 nonvolatile_load, bdxaddr20only>; 21defm CondStoreF64 : CondStores<FP64, nonvolatile_store, 22 nonvolatile_load, bdxaddr20only>; 23 24//===----------------------------------------------------------------------===// 25// Move instructions 26//===----------------------------------------------------------------------===// 27 28// Load zero. 29let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 30 def LZER : InherentRRE<"lzer", 0xB374, FP32, (fpimm0)>; 31 def LZDR : InherentRRE<"lzdr", 0xB375, FP64, (fpimm0)>; 32 def LZXR : InherentRRE<"lzxr", 0xB376, FP128, (fpimm0)>; 33} 34 35// Moves between two floating-point registers. 36let neverHasSideEffects = 1 in { 37 def LER : UnaryRR <"le", 0x38, null_frag, FP32, FP32>; 38 def LDR : UnaryRR <"ld", 0x28, null_frag, FP64, FP64>; 39 def LXR : UnaryRRE<"lx", 0xB365, null_frag, FP128, FP128>; 40} 41 42// Moves between two floating-point registers that also set the condition 43// codes. 44let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 45 defm LTEBR : LoadAndTestRRE<"lteb", 0xB302, FP32>; 46 defm LTDBR : LoadAndTestRRE<"ltdb", 0xB312, FP64>; 47 defm LTXBR : LoadAndTestRRE<"ltxb", 0xB342, FP128>; 48} 49defm : CompareZeroFP<LTEBRCompare, FP32>; 50defm : CompareZeroFP<LTDBRCompare, FP64>; 51defm : CompareZeroFP<LTXBRCompare, FP128>; 52 53// Moves between 64-bit integer and floating-point registers. 54def LGDR : UnaryRRE<"lgd", 0xB3CD, bitconvert, GR64, FP64>; 55def LDGR : UnaryRRE<"ldg", 0xB3C1, bitconvert, FP64, GR64>; 56 57// fcopysign with an FP32 result. 58let isCodeGenOnly = 1 in { 59 def CPSDRss : BinaryRRF<"cpsd", 0xB372, fcopysign, FP32, FP32>; 60 def CPSDRsd : BinaryRRF<"cpsd", 0xB372, fcopysign, FP32, FP64>; 61} 62 63// The sign of an FP128 is in the high register. 64def : Pat<(fcopysign FP32:$src1, FP128:$src2), 65 (CPSDRsd FP32:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>; 66 67// fcopysign with an FP64 result. 68let isCodeGenOnly = 1 in 69 def CPSDRds : BinaryRRF<"cpsd", 0xB372, fcopysign, FP64, FP32>; 70def CPSDRdd : BinaryRRF<"cpsd", 0xB372, fcopysign, FP64, FP64>; 71 72// The sign of an FP128 is in the high register. 73def : Pat<(fcopysign FP64:$src1, FP128:$src2), 74 (CPSDRdd FP64:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>; 75 76// fcopysign with an FP128 result. Use "upper" as the high half and leave 77// the low half as-is. 78class CopySign128<RegisterOperand cls, dag upper> 79 : Pat<(fcopysign FP128:$src1, cls:$src2), 80 (INSERT_SUBREG FP128:$src1, upper, subreg_h64)>; 81 82def : CopySign128<FP32, (CPSDRds (EXTRACT_SUBREG FP128:$src1, subreg_h64), 83 FP32:$src2)>; 84def : CopySign128<FP64, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64), 85 FP64:$src2)>; 86def : CopySign128<FP128, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64), 87 (EXTRACT_SUBREG FP128:$src2, subreg_h64))>; 88 89defm LoadStoreF32 : MVCLoadStore<load, f32, MVCSequence, 4>; 90defm LoadStoreF64 : MVCLoadStore<load, f64, MVCSequence, 8>; 91defm LoadStoreF128 : MVCLoadStore<load, f128, MVCSequence, 16>; 92 93//===----------------------------------------------------------------------===// 94// Load instructions 95//===----------------------------------------------------------------------===// 96 97let canFoldAsLoad = 1, SimpleBDXLoad = 1 in { 98 defm LE : UnaryRXPair<"le", 0x78, 0xED64, load, FP32, 4>; 99 defm LD : UnaryRXPair<"ld", 0x68, 0xED65, load, FP64, 8>; 100 101 // These instructions are split after register allocation, so we don't 102 // want a custom inserter. 103 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 104 def LX : Pseudo<(outs FP128:$dst), (ins bdxaddr20only128:$src), 105 [(set FP128:$dst, (load bdxaddr20only128:$src))]>; 106 } 107} 108 109//===----------------------------------------------------------------------===// 110// Store instructions 111//===----------------------------------------------------------------------===// 112 113let SimpleBDXStore = 1 in { 114 defm STE : StoreRXPair<"ste", 0x70, 0xED66, store, FP32, 4>; 115 defm STD : StoreRXPair<"std", 0x60, 0xED67, store, FP64, 8>; 116 117 // These instructions are split after register allocation, so we don't 118 // want a custom inserter. 119 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 120 def STX : Pseudo<(outs), (ins FP128:$src, bdxaddr20only128:$dst), 121 [(store FP128:$src, bdxaddr20only128:$dst)]>; 122 } 123} 124 125//===----------------------------------------------------------------------===// 126// Conversion instructions 127//===----------------------------------------------------------------------===// 128 129// Convert floating-point values to narrower representations, rounding 130// according to the current mode. The destination of LEXBR and LDXBR 131// is a 128-bit value, but only the first register of the pair is used. 132def LEDBR : UnaryRRE<"ledb", 0xB344, fround, FP32, FP64>; 133def LEXBR : UnaryRRE<"lexb", 0xB346, null_frag, FP128, FP128>; 134def LDXBR : UnaryRRE<"ldxb", 0xB345, null_frag, FP128, FP128>; 135 136def : Pat<(f32 (fround FP128:$src)), 137 (EXTRACT_SUBREG (LEXBR FP128:$src), subreg_hh32)>; 138def : Pat<(f64 (fround FP128:$src)), 139 (EXTRACT_SUBREG (LDXBR FP128:$src), subreg_h64)>; 140 141// Extend register floating-point values to wider representations. 142def LDEBR : UnaryRRE<"ldeb", 0xB304, fextend, FP64, FP32>; 143def LXEBR : UnaryRRE<"lxeb", 0xB306, fextend, FP128, FP32>; 144def LXDBR : UnaryRRE<"lxdb", 0xB305, fextend, FP128, FP64>; 145 146// Extend memory floating-point values to wider representations. 147def LDEB : UnaryRXE<"ldeb", 0xED04, extloadf32, FP64, 4>; 148def LXEB : UnaryRXE<"lxeb", 0xED06, extloadf32, FP128, 4>; 149def LXDB : UnaryRXE<"lxdb", 0xED05, extloadf64, FP128, 8>; 150 151// Convert a signed integer register value to a floating-point one. 152def CEFBR : UnaryRRE<"cefb", 0xB394, sint_to_fp, FP32, GR32>; 153def CDFBR : UnaryRRE<"cdfb", 0xB395, sint_to_fp, FP64, GR32>; 154def CXFBR : UnaryRRE<"cxfb", 0xB396, sint_to_fp, FP128, GR32>; 155 156def CEGBR : UnaryRRE<"cegb", 0xB3A4, sint_to_fp, FP32, GR64>; 157def CDGBR : UnaryRRE<"cdgb", 0xB3A5, sint_to_fp, FP64, GR64>; 158def CXGBR : UnaryRRE<"cxgb", 0xB3A6, sint_to_fp, FP128, GR64>; 159 160// Convert am unsigned integer register value to a floating-point one. 161let Predicates = [FeatureFPExtension] in { 162 def CELFBR : UnaryRRF4<"celfbr", 0xB390, FP32, GR32>; 163 def CDLFBR : UnaryRRF4<"cdlfbr", 0xB391, FP64, GR32>; 164 def CXLFBR : UnaryRRF4<"cxlfbr", 0xB392, FP128, GR32>; 165 166 def CELGBR : UnaryRRF4<"celgbr", 0xB3A0, FP32, GR64>; 167 def CDLGBR : UnaryRRF4<"cdlgbr", 0xB3A1, FP64, GR64>; 168 def CXLGBR : UnaryRRF4<"cxlgbr", 0xB3A2, FP128, GR64>; 169 170 def : Pat<(f32 (uint_to_fp GR32:$src)), (CELFBR 0, GR32:$src, 0)>; 171 def : Pat<(f64 (uint_to_fp GR32:$src)), (CDLFBR 0, GR32:$src, 0)>; 172 def : Pat<(f128 (uint_to_fp GR32:$src)), (CXLFBR 0, GR32:$src, 0)>; 173 174 def : Pat<(f32 (uint_to_fp GR64:$src)), (CELGBR 0, GR64:$src, 0)>; 175 def : Pat<(f64 (uint_to_fp GR64:$src)), (CDLGBR 0, GR64:$src, 0)>; 176 def : Pat<(f128 (uint_to_fp GR64:$src)), (CXLGBR 0, GR64:$src, 0)>; 177} 178 179// Convert a floating-point register value to a signed integer value, 180// with the second operand (modifier M3) specifying the rounding mode. 181let Defs = [CC] in { 182 def CFEBR : UnaryRRF<"cfeb", 0xB398, GR32, FP32>; 183 def CFDBR : UnaryRRF<"cfdb", 0xB399, GR32, FP64>; 184 def CFXBR : UnaryRRF<"cfxb", 0xB39A, GR32, FP128>; 185 186 def CGEBR : UnaryRRF<"cgeb", 0xB3A8, GR64, FP32>; 187 def CGDBR : UnaryRRF<"cgdb", 0xB3A9, GR64, FP64>; 188 def CGXBR : UnaryRRF<"cgxb", 0xB3AA, GR64, FP128>; 189} 190 191// fp_to_sint always rounds towards zero, which is modifier value 5. 192def : Pat<(i32 (fp_to_sint FP32:$src)), (CFEBR 5, FP32:$src)>; 193def : Pat<(i32 (fp_to_sint FP64:$src)), (CFDBR 5, FP64:$src)>; 194def : Pat<(i32 (fp_to_sint FP128:$src)), (CFXBR 5, FP128:$src)>; 195 196def : Pat<(i64 (fp_to_sint FP32:$src)), (CGEBR 5, FP32:$src)>; 197def : Pat<(i64 (fp_to_sint FP64:$src)), (CGDBR 5, FP64:$src)>; 198def : Pat<(i64 (fp_to_sint FP128:$src)), (CGXBR 5, FP128:$src)>; 199 200// Convert a floating-point register value to an unsigned integer value. 201let Predicates = [FeatureFPExtension] in { 202 let Defs = [CC] in { 203 def CLFEBR : UnaryRRF4<"clfebr", 0xB39C, GR32, FP32>; 204 def CLFDBR : UnaryRRF4<"clfdbr", 0xB39D, GR32, FP64>; 205 def CLFXBR : UnaryRRF4<"clfxbr", 0xB39E, GR32, FP128>; 206 207 def CLGEBR : UnaryRRF4<"clgebr", 0xB3AC, GR64, FP32>; 208 def CLGDBR : UnaryRRF4<"clgdbr", 0xB3AD, GR64, FP64>; 209 def CLGXBR : UnaryRRF4<"clgxbr", 0xB3AE, GR64, FP128>; 210 } 211 212 def : Pat<(i32 (fp_to_uint FP32:$src)), (CLFEBR 5, FP32:$src, 0)>; 213 def : Pat<(i32 (fp_to_uint FP64:$src)), (CLFDBR 5, FP64:$src, 0)>; 214 def : Pat<(i32 (fp_to_uint FP128:$src)), (CLFXBR 5, FP128:$src, 0)>; 215 216 def : Pat<(i64 (fp_to_uint FP32:$src)), (CLGEBR 5, FP32:$src, 0)>; 217 def : Pat<(i64 (fp_to_uint FP64:$src)), (CLGDBR 5, FP64:$src, 0)>; 218 def : Pat<(i64 (fp_to_uint FP128:$src)), (CLGXBR 5, FP128:$src, 0)>; 219} 220 221 222//===----------------------------------------------------------------------===// 223// Unary arithmetic 224//===----------------------------------------------------------------------===// 225 226// Negation (Load Complement). 227let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 228 def LCEBR : UnaryRRE<"lceb", 0xB303, fneg, FP32, FP32>; 229 def LCDBR : UnaryRRE<"lcdb", 0xB313, fneg, FP64, FP64>; 230 def LCXBR : UnaryRRE<"lcxb", 0xB343, fneg, FP128, FP128>; 231} 232 233// Absolute value (Load Positive). 234let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 235 def LPEBR : UnaryRRE<"lpeb", 0xB300, fabs, FP32, FP32>; 236 def LPDBR : UnaryRRE<"lpdb", 0xB310, fabs, FP64, FP64>; 237 def LPXBR : UnaryRRE<"lpxb", 0xB340, fabs, FP128, FP128>; 238} 239 240// Negative absolute value (Load Negative). 241let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 242 def LNEBR : UnaryRRE<"lneb", 0xB301, fnabs, FP32, FP32>; 243 def LNDBR : UnaryRRE<"lndb", 0xB311, fnabs, FP64, FP64>; 244 def LNXBR : UnaryRRE<"lnxb", 0xB341, fnabs, FP128, FP128>; 245} 246 247// Square root. 248def SQEBR : UnaryRRE<"sqeb", 0xB314, fsqrt, FP32, FP32>; 249def SQDBR : UnaryRRE<"sqdb", 0xB315, fsqrt, FP64, FP64>; 250def SQXBR : UnaryRRE<"sqxb", 0xB316, fsqrt, FP128, FP128>; 251 252def SQEB : UnaryRXE<"sqeb", 0xED14, loadu<fsqrt>, FP32, 4>; 253def SQDB : UnaryRXE<"sqdb", 0xED15, loadu<fsqrt>, FP64, 8>; 254 255// Round to an integer, with the second operand (modifier M3) specifying 256// the rounding mode. These forms always check for inexact conditions. 257def FIEBR : UnaryRRF<"fieb", 0xB357, FP32, FP32>; 258def FIDBR : UnaryRRF<"fidb", 0xB35F, FP64, FP64>; 259def FIXBR : UnaryRRF<"fixb", 0xB347, FP128, FP128>; 260 261// frint rounds according to the current mode (modifier 0) and detects 262// inexact conditions. 263def : Pat<(frint FP32:$src), (FIEBR 0, FP32:$src)>; 264def : Pat<(frint FP64:$src), (FIDBR 0, FP64:$src)>; 265def : Pat<(frint FP128:$src), (FIXBR 0, FP128:$src)>; 266 267let Predicates = [FeatureFPExtension] in { 268 // Extended forms of the FIxBR instructions. M4 can be set to 4 269 // to suppress detection of inexact conditions. 270 def FIEBRA : UnaryRRF4<"fiebra", 0xB357, FP32, FP32>; 271 def FIDBRA : UnaryRRF4<"fidbra", 0xB35F, FP64, FP64>; 272 def FIXBRA : UnaryRRF4<"fixbra", 0xB347, FP128, FP128>; 273 274 // fnearbyint is like frint but does not detect inexact conditions. 275 def : Pat<(fnearbyint FP32:$src), (FIEBRA 0, FP32:$src, 4)>; 276 def : Pat<(fnearbyint FP64:$src), (FIDBRA 0, FP64:$src, 4)>; 277 def : Pat<(fnearbyint FP128:$src), (FIXBRA 0, FP128:$src, 4)>; 278 279 // floor is no longer allowed to raise an inexact condition, 280 // so restrict it to the cases where the condition can be suppressed. 281 // Mode 7 is round towards -inf. 282 def : Pat<(ffloor FP32:$src), (FIEBRA 7, FP32:$src, 4)>; 283 def : Pat<(ffloor FP64:$src), (FIDBRA 7, FP64:$src, 4)>; 284 def : Pat<(ffloor FP128:$src), (FIXBRA 7, FP128:$src, 4)>; 285 286 // Same idea for ceil, where mode 6 is round towards +inf. 287 def : Pat<(fceil FP32:$src), (FIEBRA 6, FP32:$src, 4)>; 288 def : Pat<(fceil FP64:$src), (FIDBRA 6, FP64:$src, 4)>; 289 def : Pat<(fceil FP128:$src), (FIXBRA 6, FP128:$src, 4)>; 290 291 // Same idea for trunc, where mode 5 is round towards zero. 292 def : Pat<(ftrunc FP32:$src), (FIEBRA 5, FP32:$src, 4)>; 293 def : Pat<(ftrunc FP64:$src), (FIDBRA 5, FP64:$src, 4)>; 294 def : Pat<(ftrunc FP128:$src), (FIXBRA 5, FP128:$src, 4)>; 295 296 // Same idea for round, where mode 1 is round towards nearest with 297 // ties away from zero. 298 def : Pat<(frnd FP32:$src), (FIEBRA 1, FP32:$src, 4)>; 299 def : Pat<(frnd FP64:$src), (FIDBRA 1, FP64:$src, 4)>; 300 def : Pat<(frnd FP128:$src), (FIXBRA 1, FP128:$src, 4)>; 301} 302 303//===----------------------------------------------------------------------===// 304// Binary arithmetic 305//===----------------------------------------------------------------------===// 306 307// Addition. 308let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 309 let isCommutable = 1 in { 310 def AEBR : BinaryRRE<"aeb", 0xB30A, fadd, FP32, FP32>; 311 def ADBR : BinaryRRE<"adb", 0xB31A, fadd, FP64, FP64>; 312 def AXBR : BinaryRRE<"axb", 0xB34A, fadd, FP128, FP128>; 313 } 314 def AEB : BinaryRXE<"aeb", 0xED0A, fadd, FP32, load, 4>; 315 def ADB : BinaryRXE<"adb", 0xED1A, fadd, FP64, load, 8>; 316} 317 318// Subtraction. 319let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 320 def SEBR : BinaryRRE<"seb", 0xB30B, fsub, FP32, FP32>; 321 def SDBR : BinaryRRE<"sdb", 0xB31B, fsub, FP64, FP64>; 322 def SXBR : BinaryRRE<"sxb", 0xB34B, fsub, FP128, FP128>; 323 324 def SEB : BinaryRXE<"seb", 0xED0B, fsub, FP32, load, 4>; 325 def SDB : BinaryRXE<"sdb", 0xED1B, fsub, FP64, load, 8>; 326} 327 328// Multiplication. 329let isCommutable = 1 in { 330 def MEEBR : BinaryRRE<"meeb", 0xB317, fmul, FP32, FP32>; 331 def MDBR : BinaryRRE<"mdb", 0xB31C, fmul, FP64, FP64>; 332 def MXBR : BinaryRRE<"mxb", 0xB34C, fmul, FP128, FP128>; 333} 334def MEEB : BinaryRXE<"meeb", 0xED17, fmul, FP32, load, 4>; 335def MDB : BinaryRXE<"mdb", 0xED1C, fmul, FP64, load, 8>; 336 337// f64 multiplication of two FP32 registers. 338def MDEBR : BinaryRRE<"mdeb", 0xB30C, null_frag, FP64, FP32>; 339def : Pat<(fmul (f64 (fextend FP32:$src1)), (f64 (fextend FP32:$src2))), 340 (MDEBR (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 341 FP32:$src1, subreg_h32), FP32:$src2)>; 342 343// f64 multiplication of an FP32 register and an f32 memory. 344def MDEB : BinaryRXE<"mdeb", 0xED0C, null_frag, FP64, load, 4>; 345def : Pat<(fmul (f64 (fextend FP32:$src1)), 346 (f64 (extloadf32 bdxaddr12only:$addr))), 347 (MDEB (INSERT_SUBREG (f64 (IMPLICIT_DEF)), FP32:$src1, subreg_h32), 348 bdxaddr12only:$addr)>; 349 350// f128 multiplication of two FP64 registers. 351def MXDBR : BinaryRRE<"mxdb", 0xB307, null_frag, FP128, FP64>; 352def : Pat<(fmul (f128 (fextend FP64:$src1)), (f128 (fextend FP64:$src2))), 353 (MXDBR (INSERT_SUBREG (f128 (IMPLICIT_DEF)), 354 FP64:$src1, subreg_h64), FP64:$src2)>; 355 356// f128 multiplication of an FP64 register and an f64 memory. 357def MXDB : BinaryRXE<"mxdb", 0xED07, null_frag, FP128, load, 8>; 358def : Pat<(fmul (f128 (fextend FP64:$src1)), 359 (f128 (extloadf64 bdxaddr12only:$addr))), 360 (MXDB (INSERT_SUBREG (f128 (IMPLICIT_DEF)), FP64:$src1, subreg_h64), 361 bdxaddr12only:$addr)>; 362 363// Fused multiply-add. 364def MAEBR : TernaryRRD<"maeb", 0xB30E, z_fma, FP32>; 365def MADBR : TernaryRRD<"madb", 0xB31E, z_fma, FP64>; 366 367def MAEB : TernaryRXF<"maeb", 0xED0E, z_fma, FP32, load, 4>; 368def MADB : TernaryRXF<"madb", 0xED1E, z_fma, FP64, load, 8>; 369 370// Fused multiply-subtract. 371def MSEBR : TernaryRRD<"mseb", 0xB30F, z_fms, FP32>; 372def MSDBR : TernaryRRD<"msdb", 0xB31F, z_fms, FP64>; 373 374def MSEB : TernaryRXF<"mseb", 0xED0F, z_fms, FP32, load, 4>; 375def MSDB : TernaryRXF<"msdb", 0xED1F, z_fms, FP64, load, 8>; 376 377// Division. 378def DEBR : BinaryRRE<"deb", 0xB30D, fdiv, FP32, FP32>; 379def DDBR : BinaryRRE<"ddb", 0xB31D, fdiv, FP64, FP64>; 380def DXBR : BinaryRRE<"dxb", 0xB34D, fdiv, FP128, FP128>; 381 382def DEB : BinaryRXE<"deb", 0xED0D, fdiv, FP32, load, 4>; 383def DDB : BinaryRXE<"ddb", 0xED1D, fdiv, FP64, load, 8>; 384 385//===----------------------------------------------------------------------===// 386// Comparisons 387//===----------------------------------------------------------------------===// 388 389let Defs = [CC], CCValues = 0xF in { 390 def CEBR : CompareRRE<"ceb", 0xB309, z_fcmp, FP32, FP32>; 391 def CDBR : CompareRRE<"cdb", 0xB319, z_fcmp, FP64, FP64>; 392 def CXBR : CompareRRE<"cxb", 0xB349, z_fcmp, FP128, FP128>; 393 394 def CEB : CompareRXE<"ceb", 0xED09, z_fcmp, FP32, load, 4>; 395 def CDB : CompareRXE<"cdb", 0xED19, z_fcmp, FP64, load, 8>; 396} 397 398//===----------------------------------------------------------------------===// 399// Peepholes 400//===----------------------------------------------------------------------===// 401 402def : Pat<(f32 fpimmneg0), (LCEBR (LZER))>; 403def : Pat<(f64 fpimmneg0), (LCDBR (LZDR))>; 404def : Pat<(f128 fpimmneg0), (LCXBR (LZXR))>; 405