SystemZInstrFP.td revision 5753f47f5bc965ec6a891a768dc7f1a26d655ac8
1//===- SystemZInstrFP.td - SystemZ FP Instruction defs --------*- tblgen-*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the SystemZ (binary) floating point instructions in 11// TableGen format. 12// 13//===----------------------------------------------------------------------===// 14 15// FIXME: multiclassify! 16 17let usesCustomDAGSchedInserter = 1 in { 18 def SelectF32 : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, i8imm:$cc), 19 "# SelectF32 PSEUDO", 20 [(set FP32:$dst, 21 (SystemZselect FP32:$src1, FP32:$src2, imm:$cc))]>; 22 def SelectF64 : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, i8imm:$cc), 23 "# SelectF64 PSEUDO", 24 [(set FP64:$dst, 25 (SystemZselect FP64:$src1, FP64:$src2, imm:$cc))]>; 26} 27 28//===----------------------------------------------------------------------===// 29// Move Instructions 30 31let neverHasSideEffects = 1 in { 32def FMOV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src), 33 "ler\t{$dst, $src}", 34 []>; 35def FMOV64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src), 36 "ldr\t{$dst, $src}", 37 []>; 38} 39 40let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in { 41def FMOV32rm : Pseudo<(outs FP32:$dst), (ins rriaddr12:$src), 42 "le\t{$dst, $src}", 43 [(set FP32:$dst, (load rriaddr12:$src))]>; 44def FMOV32rmy : Pseudo<(outs FP32:$dst), (ins rriaddr:$src), 45 "ley\t{$dst, $src}", 46 [(set FP32:$dst, (load rriaddr:$src))]>; 47def FMOV64rm : Pseudo<(outs FP64:$dst), (ins rriaddr12:$src), 48 "ld\t{$dst, $src}", 49 [(set FP64:$dst, (load rriaddr12:$src))]>; 50def FMOV64rmy : Pseudo<(outs FP64:$dst), (ins rriaddr:$src), 51 "ldy\t{$dst, $src}", 52 [(set FP64:$dst, (load rriaddr:$src))]>; 53} 54 55def FMOV32mr : Pseudo<(outs), (ins rriaddr12:$dst, FP32:$src), 56 "ste\t{$src, $dst}", 57 [(store FP32:$src, rriaddr12:$dst)]>; 58def FMOV32mry : Pseudo<(outs), (ins rriaddr:$dst, FP32:$src), 59 "stey\t{$src, $dst}", 60 [(store FP32:$src, rriaddr:$dst)]>; 61def FMOV64mr : Pseudo<(outs), (ins rriaddr12:$dst, FP64:$src), 62 "std\t{$src, $dst}", 63 [(store FP64:$src, rriaddr12:$dst)]>; 64def FMOV64mry : Pseudo<(outs), (ins rriaddr:$dst, FP64:$src), 65 "stdy\t{$src, $dst}", 66 [(store FP64:$src, rriaddr:$dst)]>; 67 68//===----------------------------------------------------------------------===// 69// Arithmetic Instructions 70 71 72let Defs = [PSW] in { 73def FNEG32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src), 74 "lcebr\t{$dst, $src}", 75 [(set FP32:$dst, (fneg FP32:$src)), 76 (implicit PSW)]>; 77def FNEG64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src), 78 "lcdbr\t{$dst, $src}", 79 [(set FP64:$dst, (fneg FP64:$src)), 80 (implicit PSW)]>; 81 82def FABS32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src), 83 "lpebr\t{$dst, $src}", 84 [(set FP32:$dst, (fabs FP32:$src)), 85 (implicit PSW)]>; 86def FABS64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src), 87 "lpdbr\t{$dst, $src}", 88 [(set FP64:$dst, (fabs FP64:$src)), 89 (implicit PSW)]>; 90 91def FNABS32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src), 92 "lnebr\t{$dst, $src}", 93 [(set FP32:$dst, (fneg(fabs FP32:$src))), 94 (implicit PSW)]>; 95def FNABS64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src), 96 "lndbr\t{$dst, $src}", 97 [(set FP64:$dst, (fneg(fabs FP64:$src))), 98 (implicit PSW)]>; 99} 100 101let isTwoAddress = 1 in { 102let Defs = [PSW] in { 103let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y 104def FADD32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2), 105 "aebr\t{$dst, $src2}", 106 [(set FP32:$dst, (fadd FP32:$src1, FP32:$src2)), 107 (implicit PSW)]>; 108def FADD64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2), 109 "adbr\t{$dst, $src2}", 110 [(set FP64:$dst, (fadd FP64:$src1, FP64:$src2)), 111 (implicit PSW)]>; 112} 113 114def FADD32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2), 115 "aeb\t{$dst, $src2}", 116 [(set FP32:$dst, (fadd FP32:$src1, (load rriaddr:$src2))), 117 (implicit PSW)]>; 118def FADD64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2), 119 "adb\t{$dst, $src2}", 120 [(set FP64:$dst, (fadd FP64:$src1, (load rriaddr:$src2))), 121 (implicit PSW)]>; 122 123def FSUB32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2), 124 "sebr\t{$dst, $src2}", 125 [(set FP32:$dst, (fsub FP32:$src1, FP32:$src2)), 126 (implicit PSW)]>; 127def FSUB64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2), 128 "sdbr\t{$dst, $src2}", 129 [(set FP64:$dst, (fsub FP64:$src1, FP64:$src2)), 130 (implicit PSW)]>; 131 132def FSUB32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2), 133 "seb\t{$dst, $src2}", 134 [(set FP32:$dst, (fsub FP32:$src1, (load rriaddr:$src2))), 135 (implicit PSW)]>; 136def FSUB64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2), 137 "sdb\t{$dst, $src2}", 138 [(set FP64:$dst, (fsub FP64:$src1, (load rriaddr:$src2))), 139 (implicit PSW)]>; 140} // Defs = [PSW] 141 142let isCommutable = 1 in { // X = MUL Y, Z == X = MUL Z, Y 143def FMUL32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2), 144 "meebr\t{$dst, $src2}", 145 [(set FP32:$dst, (fmul FP32:$src1, FP32:$src2))]>; 146def FMUL64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2), 147 "mdbr\t{$dst, $src2}", 148 [(set FP64:$dst, (fmul FP64:$src1, FP64:$src2))]>; 149} 150 151def FMUL32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2), 152 "meeb\t{$dst, $src2}", 153 [(set FP32:$dst, (fmul FP32:$src1, (load rriaddr:$src2)))]>; 154def FMUL64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2), 155 "mdb\t{$dst, $src2}", 156 [(set FP64:$dst, (fmul FP64:$src1, (load rriaddr:$src2)))]>; 157 158def FMADD32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, FP32:$src3), 159 "maebr\t{$dst, $src3, $src2}", 160 [(set FP32:$dst, (fadd (fmul FP32:$src2, FP32:$src3), 161 FP32:$src1))]>; 162def FMADD32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2, FP32:$src3), 163 "maeb\t{$dst, $src3, $src2}", 164 [(set FP32:$dst, (fadd (fmul (load rriaddr:$src2), 165 FP32:$src3), 166 FP32:$src1))]>; 167 168def FMADD64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, FP64:$src3), 169 "madbr\t{$dst, $src3, $src2}", 170 [(set FP64:$dst, (fadd (fmul FP64:$src2, FP64:$src3), 171 FP64:$src1))]>; 172def FMADD64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2, FP64:$src3), 173 "madb\t{$dst, $src3, $src2}", 174 [(set FP64:$dst, (fadd (fmul (load rriaddr:$src2), 175 FP64:$src3), 176 FP64:$src1))]>; 177 178def FMSUB32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, FP32:$src3), 179 "msebr\t{$dst, $src3, $src2}", 180 [(set FP32:$dst, (fsub (fmul FP32:$src2, FP32:$src3), 181 FP32:$src1))]>; 182def FMSUB32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2, FP32:$src3), 183 "mseb\t{$dst, $src3, $src2}", 184 [(set FP32:$dst, (fsub (fmul (load rriaddr:$src2), 185 FP32:$src3), 186 FP32:$src1))]>; 187 188def FMSUB64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, FP64:$src3), 189 "msdbr\t{$dst, $src3, $src2}", 190 [(set FP64:$dst, (fsub (fmul FP64:$src2, FP64:$src3), 191 FP64:$src1))]>; 192def FMSUB64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2, FP64:$src3), 193 "msdb\t{$dst, $src3, $src2}", 194 [(set FP64:$dst, (fsub (fmul (load rriaddr:$src2), 195 FP64:$src3), 196 FP64:$src1))]>; 197 198def FDIV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2), 199 "debr\t{$dst, $src2}", 200 [(set FP32:$dst, (fdiv FP32:$src1, FP32:$src2))]>; 201def FDIV64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2), 202 "ddbr\t{$dst, $src2}", 203 [(set FP64:$dst, (fdiv FP64:$src1, FP64:$src2))]>; 204 205def FDIV32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2), 206 "deb\t{$dst, $src2}", 207 [(set FP32:$dst, (fdiv FP32:$src1, (load rriaddr:$src2)))]>; 208def FDIV64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2), 209 "ddb\t{$dst, $src2}", 210 [(set FP64:$dst, (fdiv FP64:$src1, (load rriaddr:$src2)))]>; 211 212} // isTwoAddress = 1 213 214def FROUND64r32 : Pseudo<(outs FP32:$dst), (ins FP64:$src), 215 "ledbr\t{$dst, $src}", 216 [(set FP32:$dst, (fround FP64:$src))]>; 217 218def FEXT32r64 : Pseudo<(outs FP64:$dst), (ins FP32:$src), 219 "ldebr\t{$dst, $src}", 220 [(set FP64:$dst, (fextend FP32:$src))]>; 221def FEXT32m64 : Pseudo<(outs FP64:$dst), (ins rriaddr:$src), 222 "ldeb\t{$dst, $src}", 223 [(set FP64:$dst, (fextend (load rriaddr:$src)))]>; 224 225let Defs = [PSW] in { 226def FCONVFP32 : Pseudo<(outs FP32:$dst), (ins GR32:$src), 227 "cefbr\t{$dst, $src}", 228 [(set FP32:$dst, (sint_to_fp GR32:$src)), 229 (implicit PSW)]>; 230def FCONVFP32r64: Pseudo<(outs FP32:$dst), (ins GR64:$src), 231 "cegbr\t{$dst, $src}", 232 [(set FP32:$dst, (sint_to_fp GR64:$src)), 233 (implicit PSW)]>; 234 235def FCONVFP64r32: Pseudo<(outs FP64:$dst), (ins GR32:$src), 236 "cdfbr\t{$dst, $src}", 237 [(set FP64:$dst, (sint_to_fp GR32:$src)), 238 (implicit PSW)]>; 239def FCONVFP64 : Pseudo<(outs FP64:$dst), (ins GR64:$src), 240 "cdgbr\t{$dst, $src}", 241 [(set FP64:$dst, (sint_to_fp GR64:$src)), 242 (implicit PSW)]>; 243 244def FCONVGR32 : Pseudo<(outs GR32:$dst), (ins FP32:$src), 245 "cfebr\t{$dst, $src}", 246 [(set GR32:$dst, (fp_to_sint FP32:$src)), 247 (implicit PSW)]>; 248def FCONVGR32r64: Pseudo<(outs GR32:$dst), (ins FP64:$src), 249 "cgebr\t{$dst, $src}", 250 [(set GR32:$dst, (fp_to_sint FP64:$src)), 251 (implicit PSW)]>; 252 253def FCONVGR64r32: Pseudo<(outs GR64:$dst), (ins FP32:$src), 254 "cfdbr\t{$dst, $src}", 255 [(set GR64:$dst, (fp_to_sint FP32:$src)), 256 (implicit PSW)]>; 257def FCONVGR64 : Pseudo<(outs GR64:$dst), (ins FP64:$src), 258 "cgdbr\t{$dst, $src}", 259 [(set GR64:$dst, (fp_to_sint FP64:$src)), 260 (implicit PSW)]>; 261} // Defs = [PSW] 262 263//===----------------------------------------------------------------------===// 264// Test instructions (like AND but do not produce any result) 265 266// Integer comparisons 267let Defs = [PSW] in { 268def FCMP32rr : Pseudo<(outs), (ins FP32:$src1, FP32:$src2), 269 "cebr\t$src1, $src2", 270 [(SystemZcmp FP32:$src1, FP32:$src2), (implicit PSW)]>; 271def FCMP64rr : Pseudo<(outs), (ins FP64:$src1, FP64:$src2), 272 "cdbr\t$src1, $src2", 273 [(SystemZcmp FP64:$src1, FP64:$src2), (implicit PSW)]>; 274 275def FCMP32rm : Pseudo<(outs), (ins FP32:$src1, rriaddr:$src2), 276 "ceb\t$src1, $src2", 277 [(SystemZcmp FP32:$src1, (load rriaddr:$src2)), 278 (implicit PSW)]>; 279def FCMP64rm : Pseudo<(outs), (ins FP64:$src1, rriaddr:$src2), 280 "cdb\t$src1, $src2", 281 [(SystemZcmp FP64:$src1, (load rriaddr:$src2)), 282 (implicit PSW)]>; 283} // Defs = [PSW] 284