SystemZInstrFP.td revision d954716e7567282ff6f3d25b4f404bae006eed04
1//==- SystemZInstrFP.td - Floating-point SystemZ instructions --*- tblgen-*-==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Select instructions 12//===----------------------------------------------------------------------===// 13 14// C's ?: operator for floating-point operands. 15def SelectF32 : SelectWrapper<FP32>; 16def SelectF64 : SelectWrapper<FP64>; 17def SelectF128 : SelectWrapper<FP128>; 18 19defm CondStoreF32 : CondStores<FP32, nonvolatile_store, 20 nonvolatile_load, bdxaddr20only>; 21defm CondStoreF64 : CondStores<FP64, nonvolatile_store, 22 nonvolatile_load, bdxaddr20only>; 23 24//===----------------------------------------------------------------------===// 25// Move instructions 26//===----------------------------------------------------------------------===// 27 28// Load zero. 29let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 30 def LZER : InherentRRE<"lzer", 0xB374, FP32, (fpimm0)>; 31 def LZDR : InherentRRE<"lzdr", 0xB375, FP64, (fpimm0)>; 32 def LZXR : InherentRRE<"lzxr", 0xB376, FP128, (fpimm0)>; 33} 34 35// Moves between two floating-point registers. 36let neverHasSideEffects = 1 in { 37 def LER : UnaryRR <"le", 0x38, null_frag, FP32, FP32>; 38 def LDR : UnaryRR <"ld", 0x28, null_frag, FP64, FP64>; 39 def LXR : UnaryRRE<"lx", 0xB365, null_frag, FP128, FP128>; 40} 41 42// Moves between two floating-point registers that also set the condition 43// codes. 44let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 45 defm LTEBR : LoadAndTestRRE<"lteb", 0xB302, FP32>; 46 defm LTDBR : LoadAndTestRRE<"ltdb", 0xB312, FP64>; 47 defm LTXBR : LoadAndTestRRE<"ltxb", 0xB342, FP128>; 48} 49def : CompareZeroFP<LTEBRCompare, FP32>; 50def : CompareZeroFP<LTDBRCompare, FP64>; 51def : CompareZeroFP<LTXBRCompare, FP128>; 52 53// Moves between 64-bit integer and floating-point registers. 54def LGDR : UnaryRRE<"lgd", 0xB3CD, bitconvert, GR64, FP64>; 55def LDGR : UnaryRRE<"ldg", 0xB3C1, bitconvert, FP64, GR64>; 56 57// fcopysign with an FP32 result. 58let isCodeGenOnly = 1 in { 59 def CPSDRss : BinaryRRF<"cpsd", 0xB372, fcopysign, FP32, FP32>; 60 def CPSDRsd : BinaryRRF<"cpsd", 0xB372, fcopysign, FP32, FP64>; 61} 62 63// The sign of an FP128 is in the high register. 64def : Pat<(fcopysign FP32:$src1, FP128:$src2), 65 (CPSDRsd FP32:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_high))>; 66 67// fcopysign with an FP64 result. 68let isCodeGenOnly = 1 in 69 def CPSDRds : BinaryRRF<"cpsd", 0xB372, fcopysign, FP64, FP32>; 70def CPSDRdd : BinaryRRF<"cpsd", 0xB372, fcopysign, FP64, FP64>; 71 72// The sign of an FP128 is in the high register. 73def : Pat<(fcopysign FP64:$src1, FP128:$src2), 74 (CPSDRdd FP64:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_high))>; 75 76// fcopysign with an FP128 result. Use "upper" as the high half and leave 77// the low half as-is. 78class CopySign128<RegisterOperand cls, dag upper> 79 : Pat<(fcopysign FP128:$src1, cls:$src2), 80 (INSERT_SUBREG FP128:$src1, upper, subreg_high)>; 81 82def : CopySign128<FP32, (CPSDRds (EXTRACT_SUBREG FP128:$src1, subreg_high), 83 FP32:$src2)>; 84def : CopySign128<FP64, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_high), 85 FP64:$src2)>; 86def : CopySign128<FP128, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_high), 87 (EXTRACT_SUBREG FP128:$src2, subreg_high))>; 88 89defm LoadStoreF32 : MVCLoadStore<load, store, f32, MVCWrapper, 4>; 90defm LoadStoreF64 : MVCLoadStore<load, store, f64, MVCWrapper, 8>; 91defm LoadStoreF128 : MVCLoadStore<load, store, f128, MVCWrapper, 16>; 92 93//===----------------------------------------------------------------------===// 94// Load instructions 95//===----------------------------------------------------------------------===// 96 97let canFoldAsLoad = 1, SimpleBDXLoad = 1 in { 98 defm LE : UnaryRXPair<"le", 0x78, 0xED64, load, FP32, 4>; 99 defm LD : UnaryRXPair<"ld", 0x68, 0xED65, load, FP64, 8>; 100 101 // These instructions are split after register allocation, so we don't 102 // want a custom inserter. 103 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 104 def LX : Pseudo<(outs FP128:$dst), (ins bdxaddr20only128:$src), 105 [(set FP128:$dst, (load bdxaddr20only128:$src))]>; 106 } 107} 108 109//===----------------------------------------------------------------------===// 110// Store instructions 111//===----------------------------------------------------------------------===// 112 113let SimpleBDXStore = 1 in { 114 defm STE : StoreRXPair<"ste", 0x70, 0xED66, store, FP32, 4>; 115 defm STD : StoreRXPair<"std", 0x60, 0xED67, store, FP64, 8>; 116 117 // These instructions are split after register allocation, so we don't 118 // want a custom inserter. 119 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 120 def STX : Pseudo<(outs), (ins FP128:$src, bdxaddr20only128:$dst), 121 [(store FP128:$src, bdxaddr20only128:$dst)]>; 122 } 123} 124 125//===----------------------------------------------------------------------===// 126// Conversion instructions 127//===----------------------------------------------------------------------===// 128 129// Convert floating-point values to narrower representations, rounding 130// according to the current mode. The destination of LEXBR and LDXBR 131// is a 128-bit value, but only the first register of the pair is used. 132def LEDBR : UnaryRRE<"ledb", 0xB344, fround, FP32, FP64>; 133def LEXBR : UnaryRRE<"lexb", 0xB346, null_frag, FP128, FP128>; 134def LDXBR : UnaryRRE<"ldxb", 0xB345, null_frag, FP128, FP128>; 135 136def : Pat<(f32 (fround FP128:$src)), 137 (EXTRACT_SUBREG (LEXBR FP128:$src), subreg_32bit)>; 138def : Pat<(f64 (fround FP128:$src)), 139 (EXTRACT_SUBREG (LDXBR FP128:$src), subreg_high)>; 140 141// Extend register floating-point values to wider representations. 142def LDEBR : UnaryRRE<"ldeb", 0xB304, fextend, FP64, FP32>; 143def LXEBR : UnaryRRE<"lxeb", 0xB306, fextend, FP128, FP32>; 144def LXDBR : UnaryRRE<"lxdb", 0xB305, fextend, FP128, FP64>; 145 146// Extend memory floating-point values to wider representations. 147def LDEB : UnaryRXE<"ldeb", 0xED04, extloadf32, FP64, 4>; 148def LXEB : UnaryRXE<"lxeb", 0xED06, extloadf32, FP128, 4>; 149def LXDB : UnaryRXE<"lxdb", 0xED05, extloadf64, FP128, 8>; 150 151// Convert a signed integer register value to a floating-point one. 152def CEFBR : UnaryRRE<"cefb", 0xB394, sint_to_fp, FP32, GR32>; 153def CDFBR : UnaryRRE<"cdfb", 0xB395, sint_to_fp, FP64, GR32>; 154def CXFBR : UnaryRRE<"cxfb", 0xB396, sint_to_fp, FP128, GR32>; 155 156def CEGBR : UnaryRRE<"cegb", 0xB3A4, sint_to_fp, FP32, GR64>; 157def CDGBR : UnaryRRE<"cdgb", 0xB3A5, sint_to_fp, FP64, GR64>; 158def CXGBR : UnaryRRE<"cxgb", 0xB3A6, sint_to_fp, FP128, GR64>; 159 160// Convert a floating-point register value to a signed integer value, 161// with the second operand (modifier M3) specifying the rounding mode. 162let Defs = [CC] in { 163 def CFEBR : UnaryRRF<"cfeb", 0xB398, GR32, FP32>; 164 def CFDBR : UnaryRRF<"cfdb", 0xB399, GR32, FP64>; 165 def CFXBR : UnaryRRF<"cfxb", 0xB39A, GR32, FP128>; 166 167 def CGEBR : UnaryRRF<"cgeb", 0xB3A8, GR64, FP32>; 168 def CGDBR : UnaryRRF<"cgdb", 0xB3A9, GR64, FP64>; 169 def CGXBR : UnaryRRF<"cgxb", 0xB3AA, GR64, FP128>; 170} 171 172// fp_to_sint always rounds towards zero, which is modifier value 5. 173def : Pat<(i32 (fp_to_sint FP32:$src)), (CFEBR 5, FP32:$src)>; 174def : Pat<(i32 (fp_to_sint FP64:$src)), (CFDBR 5, FP64:$src)>; 175def : Pat<(i32 (fp_to_sint FP128:$src)), (CFXBR 5, FP128:$src)>; 176 177def : Pat<(i64 (fp_to_sint FP32:$src)), (CGEBR 5, FP32:$src)>; 178def : Pat<(i64 (fp_to_sint FP64:$src)), (CGDBR 5, FP64:$src)>; 179def : Pat<(i64 (fp_to_sint FP128:$src)), (CGXBR 5, FP128:$src)>; 180 181//===----------------------------------------------------------------------===// 182// Unary arithmetic 183//===----------------------------------------------------------------------===// 184 185// Negation (Load Complement). 186let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 187 def LCEBR : UnaryRRE<"lceb", 0xB303, fneg, FP32, FP32>; 188 def LCDBR : UnaryRRE<"lcdb", 0xB313, fneg, FP64, FP64>; 189 def LCXBR : UnaryRRE<"lcxb", 0xB343, fneg, FP128, FP128>; 190} 191 192// Absolute value (Load Positive). 193let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 194 def LPEBR : UnaryRRE<"lpeb", 0xB300, fabs, FP32, FP32>; 195 def LPDBR : UnaryRRE<"lpdb", 0xB310, fabs, FP64, FP64>; 196 def LPXBR : UnaryRRE<"lpxb", 0xB340, fabs, FP128, FP128>; 197} 198 199// Negative absolute value (Load Negative). 200let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 201 def LNEBR : UnaryRRE<"lneb", 0xB301, fnabs, FP32, FP32>; 202 def LNDBR : UnaryRRE<"lndb", 0xB311, fnabs, FP64, FP64>; 203 def LNXBR : UnaryRRE<"lnxb", 0xB341, fnabs, FP128, FP128>; 204} 205 206// Square root. 207def SQEBR : UnaryRRE<"sqeb", 0xB314, fsqrt, FP32, FP32>; 208def SQDBR : UnaryRRE<"sqdb", 0xB315, fsqrt, FP64, FP64>; 209def SQXBR : UnaryRRE<"sqxb", 0xB316, fsqrt, FP128, FP128>; 210 211def SQEB : UnaryRXE<"sqeb", 0xED14, loadu<fsqrt>, FP32, 4>; 212def SQDB : UnaryRXE<"sqdb", 0xED15, loadu<fsqrt>, FP64, 8>; 213 214// Round to an integer, with the second operand (modifier M3) specifying 215// the rounding mode. These forms always check for inexact conditions. 216def FIEBR : UnaryRRF<"fieb", 0xB357, FP32, FP32>; 217def FIDBR : UnaryRRF<"fidb", 0xB35F, FP64, FP64>; 218def FIXBR : UnaryRRF<"fixb", 0xB347, FP128, FP128>; 219 220// Extended forms of the previous three instructions. M4 can be set to 4 221// to suppress detection of inexact conditions. 222def FIEBRA : UnaryRRF4<"fiebra", 0xB357, FP32, FP32>, 223 Requires<[FeatureFPExtension]>; 224def FIDBRA : UnaryRRF4<"fidbra", 0xB35F, FP64, FP64>, 225 Requires<[FeatureFPExtension]>; 226def FIXBRA : UnaryRRF4<"fixbra", 0xB347, FP128, FP128>, 227 Requires<[FeatureFPExtension]>; 228 229// frint rounds according to the current mode (modifier 0) and detects 230// inexact conditions. 231def : Pat<(frint FP32:$src), (FIEBR 0, FP32:$src)>; 232def : Pat<(frint FP64:$src), (FIDBR 0, FP64:$src)>; 233def : Pat<(frint FP128:$src), (FIXBR 0, FP128:$src)>; 234 235//===----------------------------------------------------------------------===// 236// Binary arithmetic 237//===----------------------------------------------------------------------===// 238 239// Addition. 240let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 241 let isCommutable = 1 in { 242 def AEBR : BinaryRRE<"aeb", 0xB30A, fadd, FP32, FP32>; 243 def ADBR : BinaryRRE<"adb", 0xB31A, fadd, FP64, FP64>; 244 def AXBR : BinaryRRE<"axb", 0xB34A, fadd, FP128, FP128>; 245 } 246 def AEB : BinaryRXE<"aeb", 0xED0A, fadd, FP32, load, 4>; 247 def ADB : BinaryRXE<"adb", 0xED1A, fadd, FP64, load, 8>; 248} 249 250// Subtraction. 251let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 252 def SEBR : BinaryRRE<"seb", 0xB30B, fsub, FP32, FP32>; 253 def SDBR : BinaryRRE<"sdb", 0xB31B, fsub, FP64, FP64>; 254 def SXBR : BinaryRRE<"sxb", 0xB34B, fsub, FP128, FP128>; 255 256 def SEB : BinaryRXE<"seb", 0xED0B, fsub, FP32, load, 4>; 257 def SDB : BinaryRXE<"sdb", 0xED1B, fsub, FP64, load, 8>; 258} 259 260// Multiplication. 261let isCommutable = 1 in { 262 def MEEBR : BinaryRRE<"meeb", 0xB317, fmul, FP32, FP32>; 263 def MDBR : BinaryRRE<"mdb", 0xB31C, fmul, FP64, FP64>; 264 def MXBR : BinaryRRE<"mxb", 0xB34C, fmul, FP128, FP128>; 265} 266def MEEB : BinaryRXE<"meeb", 0xED17, fmul, FP32, load, 4>; 267def MDB : BinaryRXE<"mdb", 0xED1C, fmul, FP64, load, 8>; 268 269// f64 multiplication of two FP32 registers. 270def MDEBR : BinaryRRE<"mdeb", 0xB30C, null_frag, FP64, FP32>; 271def : Pat<(fmul (f64 (fextend FP32:$src1)), (f64 (fextend FP32:$src2))), 272 (MDEBR (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 273 FP32:$src1, subreg_32bit), FP32:$src2)>; 274 275// f64 multiplication of an FP32 register and an f32 memory. 276def MDEB : BinaryRXE<"mdeb", 0xED0C, null_frag, FP64, load, 4>; 277def : Pat<(fmul (f64 (fextend FP32:$src1)), 278 (f64 (extloadf32 bdxaddr12only:$addr))), 279 (MDEB (INSERT_SUBREG (f64 (IMPLICIT_DEF)), FP32:$src1, subreg_32bit), 280 bdxaddr12only:$addr)>; 281 282// f128 multiplication of two FP64 registers. 283def MXDBR : BinaryRRE<"mxdb", 0xB307, null_frag, FP128, FP64>; 284def : Pat<(fmul (f128 (fextend FP64:$src1)), (f128 (fextend FP64:$src2))), 285 (MXDBR (INSERT_SUBREG (f128 (IMPLICIT_DEF)), 286 FP64:$src1, subreg_high), FP64:$src2)>; 287 288// f128 multiplication of an FP64 register and an f64 memory. 289def MXDB : BinaryRXE<"mxdb", 0xED07, null_frag, FP128, load, 8>; 290def : Pat<(fmul (f128 (fextend FP64:$src1)), 291 (f128 (extloadf64 bdxaddr12only:$addr))), 292 (MXDB (INSERT_SUBREG (f128 (IMPLICIT_DEF)), FP64:$src1, subreg_high), 293 bdxaddr12only:$addr)>; 294 295// Fused multiply-add. 296def MAEBR : TernaryRRD<"maeb", 0xB30E, z_fma, FP32>; 297def MADBR : TernaryRRD<"madb", 0xB31E, z_fma, FP64>; 298 299def MAEB : TernaryRXF<"maeb", 0xED0E, z_fma, FP32, load, 4>; 300def MADB : TernaryRXF<"madb", 0xED1E, z_fma, FP64, load, 8>; 301 302// Fused multiply-subtract. 303def MSEBR : TernaryRRD<"mseb", 0xB30F, z_fms, FP32>; 304def MSDBR : TernaryRRD<"msdb", 0xB31F, z_fms, FP64>; 305 306def MSEB : TernaryRXF<"mseb", 0xED0F, z_fms, FP32, load, 4>; 307def MSDB : TernaryRXF<"msdb", 0xED1F, z_fms, FP64, load, 8>; 308 309// Division. 310def DEBR : BinaryRRE<"deb", 0xB30D, fdiv, FP32, FP32>; 311def DDBR : BinaryRRE<"ddb", 0xB31D, fdiv, FP64, FP64>; 312def DXBR : BinaryRRE<"dxb", 0xB34D, fdiv, FP128, FP128>; 313 314def DEB : BinaryRXE<"deb", 0xED0D, fdiv, FP32, load, 4>; 315def DDB : BinaryRXE<"ddb", 0xED1D, fdiv, FP64, load, 8>; 316 317//===----------------------------------------------------------------------===// 318// Comparisons 319//===----------------------------------------------------------------------===// 320 321let Defs = [CC], CCValues = 0xF in { 322 def CEBR : CompareRRE<"ceb", 0xB309, z_cmp, FP32, FP32>; 323 def CDBR : CompareRRE<"cdb", 0xB319, z_cmp, FP64, FP64>; 324 def CXBR : CompareRRE<"cxb", 0xB349, z_cmp, FP128, FP128>; 325 326 def CEB : CompareRXE<"ceb", 0xED09, z_cmp, FP32, load, 4>; 327 def CDB : CompareRXE<"cdb", 0xED19, z_cmp, FP64, load, 8>; 328} 329 330//===----------------------------------------------------------------------===// 331// Peepholes 332//===----------------------------------------------------------------------===// 333 334def : Pat<(f32 fpimmneg0), (LCEBR (LZER))>; 335def : Pat<(f64 fpimmneg0), (LCDBR (LZDR))>; 336def : Pat<(f128 fpimmneg0), (LCXBR (LZXR))>; 337