SystemZInstrFP.td revision da723d7d9191b5710ea783f4a57c83a0c7087748 
1//===- SystemZInstrFP.td - SystemZ FP Instruction defs --------*- tblgen-*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source 
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the SystemZ (binary) floating point instructions in 
11// TableGen format.
12//
13//===----------------------------------------------------------------------===//
14
15// FIXME: multiclassify!
16
17let usesCustomDAGSchedInserter = 1 in {
18  def SelectF32 : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, i8imm:$cc),
19                        "# SelectF32 PSEUDO",
20                        [(set FP32:$dst,
21                              (SystemZselect FP32:$src1, FP32:$src2, imm:$cc))]>;
22  def SelectF64 : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, i8imm:$cc),
23                        "# SelectF64 PSEUDO",
24                        [(set FP64:$dst,
25                              (SystemZselect FP64:$src1, FP64:$src2, imm:$cc))]>;
26}
27
28//===----------------------------------------------------------------------===//
29// Move Instructions
30
31let neverHasSideEffects = 1 in {
32def FMOV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
33                      "ler\t{$dst, $src}",
34                      []>;
35def FMOV64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
36                      "ldr\t{$dst, $src}",
37                      []>;
38}
39
40let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
41def FMOV32rm  : Pseudo<(outs FP32:$dst), (ins rriaddr12:$src),
42                      "le\t{$dst, $src}",
43                      [(set FP32:$dst, (load rriaddr12:$src))]>;
44def FMOV32rmy : Pseudo<(outs FP32:$dst), (ins rriaddr:$src),
45                      "ley\t{$dst, $src}",
46                      [(set FP32:$dst, (load rriaddr:$src))]>;
47def FMOV64rm  : Pseudo<(outs FP64:$dst), (ins rriaddr12:$src),
48                      "ld\t{$dst, $src}",
49                      [(set FP64:$dst, (load rriaddr12:$src))]>;
50def FMOV64rmy : Pseudo<(outs FP64:$dst), (ins rriaddr:$src),
51                      "ldy\t{$dst, $src}",
52                      [(set FP64:$dst, (load rriaddr:$src))]>;
53}
54
55def FMOV32mr  : Pseudo<(outs), (ins rriaddr12:$dst, FP32:$src),
56                       "ste\t{$src, $dst}",
57                       [(store FP32:$src, rriaddr12:$dst)]>;
58def FMOV32mry : Pseudo<(outs), (ins rriaddr:$dst, FP32:$src),
59                       "stey\t{$src, $dst}",
60                       [(store FP32:$src, rriaddr:$dst)]>;
61def FMOV64mr  : Pseudo<(outs), (ins rriaddr12:$dst, FP64:$src),
62                       "std\t{$src, $dst}",
63                       [(store FP64:$src, rriaddr12:$dst)]>;
64def FMOV64mry : Pseudo<(outs), (ins rriaddr:$dst, FP64:$src),
65                       "stdy\t{$src, $dst}",
66                       [(store FP64:$src, rriaddr:$dst)]>;
67
68//===----------------------------------------------------------------------===//
69// Arithmetic Instructions
70
71
72
73let isTwoAddress = 1 in {
74def FNEG32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
75                       "lcebr\t{$dst}",
76                       [(set FP32:$dst, (fneg FP32:$src))]>;
77def FNEG64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
78                       "lcdbr\t{$dst}",
79                       [(set FP64:$dst, (fneg FP64:$src))]>;
80
81// FIXME: Add peephole for fneg(fabs) => load negative
82
83def FABS32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
84                       "lpebr\t{$dst}",
85                       [(set FP32:$dst, (fabs FP32:$src))]>;
86def FABS64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
87                       "lpdbr\t{$dst}",
88                       [(set FP64:$dst, (fabs FP64:$src))]>;
89
90let isCommutable = 1 in { // X = ADD Y, Z  == X = ADD Z, Y
91def FADD32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
92                       "aebr\t{$dst, $src2}",
93                       [(set FP32:$dst, (fadd FP32:$src1, FP32:$src2))]>;
94def FADD64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
95                       "adbr\t{$dst, $src2}",
96                       [(set FP64:$dst, (fadd FP64:$src1, FP64:$src2))]>;
97}
98
99def FADD32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
100                       "aeb\t{$dst, $src2}",
101                       [(set FP32:$dst, (fadd FP32:$src1, (load rriaddr:$src2)))]>;
102def FADD64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
103                       "adb\t{$dst, $src2}",
104                       [(set FP64:$dst, (fadd FP64:$src1, (load rriaddr:$src2)))]>;
105
106def FSUB32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
107                       "sebr\t{$dst, $src2}",
108                       [(set FP32:$dst, (fsub FP32:$src1, FP32:$src2))]>;
109def FSUB64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
110                       "sdbr\t{$dst, $src2}",
111                       [(set FP64:$dst, (fsub FP64:$src1, FP64:$src2))]>;
112
113def FSUB32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
114                       "seb\t{$dst, $src2}",
115                       [(set FP32:$dst, (fsub FP32:$src1, (load rriaddr:$src2)))]>;
116def FSUB64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
117                       "sdb\t{$dst, $src2}",
118                       [(set FP64:$dst, (fsub FP64:$src1, (load rriaddr:$src2)))]>;
119
120let isCommutable = 1 in { // X = MUL Y, Z  == X = MUL Z, Y
121def FMUL32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
122                       "meebr\t{$dst, $src2}",
123                       [(set FP32:$dst, (fmul FP32:$src1, FP32:$src2))]>;
124def FMUL64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
125                       "mdbr\t{$dst, $src2}",
126                       [(set FP64:$dst, (fmul FP64:$src1, FP64:$src2))]>;
127}
128
129def FMUL32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
130                       "meeb\t{$dst, $src2}",
131                       [(set FP32:$dst, (fmul FP32:$src1, (load rriaddr:$src2)))]>;
132def FMUL64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
133                       "mdb\t{$dst, $src2}",
134                       [(set FP64:$dst, (fmul FP64:$src1, (load rriaddr:$src2)))]>;
135
136def FDIV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
137                       "debr\t{$dst, $src2}",
138                       [(set FP32:$dst, (fdiv FP32:$src1, FP32:$src2))]>;
139def FDIV64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
140                       "ddbr\t{$dst, $src2}",
141                       [(set FP64:$dst, (fdiv FP64:$src1, FP64:$src2))]>;
142
143def FDIV32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
144                       "deb\t{$dst, $src2}",
145                       [(set FP32:$dst, (fdiv FP32:$src1, (load rriaddr:$src2)))]>;
146def FDIV64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
147                       "ddb\t{$dst, $src2}",
148                       [(set FP64:$dst, (fdiv FP64:$src1, (load rriaddr:$src2)))]>;
149
150} // isTwoAddress = 1
151
152def FROUND64r32 : Pseudo<(outs FP32:$dst), (ins FP64:$src),
153                         "ledbr\t{$dst, $src}",
154                         [(set FP32:$dst, (fround FP64:$src))]>;
155
156def FCONVFP32   : Pseudo<(outs FP32:$dst), (ins GR32:$src),
157                         "cefbr\t{$dst, $src}",
158                         [(set FP32:$dst, (sint_to_fp GR32:$src))]>;
159def FCONVFP32r64: Pseudo<(outs FP32:$dst), (ins GR64:$src),
160                         "cegbr\t{$dst, $src}",
161                         [(set FP32:$dst, (sint_to_fp GR64:$src))]>;
162
163def FCONVFP64r32: Pseudo<(outs FP64:$dst), (ins GR32:$src),
164                         "cdfbr\t{$dst, $src}",
165                         [(set FP64:$dst, (sint_to_fp GR32:$src))]>;
166def FCONVFP64   : Pseudo<(outs FP64:$dst), (ins GR64:$src),
167                         "cdgbr\t{$dst, $src}",
168                         [(set FP64:$dst, (sint_to_fp GR64:$src))]>;
169
170def FCONVGR32   : Pseudo<(outs GR32:$dst), (ins FP32:$src),
171                         "cfebr\t{$dst, $src}",
172                         [(set GR32:$dst, (fp_to_sint FP32:$src))]>;
173def FCONVGR32r64: Pseudo<(outs GR32:$dst), (ins FP64:$src),
174                         "cgebr\t{$dst, $src}",
175                         [(set GR32:$dst, (fp_to_sint FP64:$src))]>;
176
177def FCONVGR64r32: Pseudo<(outs GR64:$dst), (ins FP32:$src),
178                         "cfdbr\t{$dst, $src}",
179                         [(set GR64:$dst, (fp_to_sint FP32:$src))]>;
180def FCONVGR64   : Pseudo<(outs GR64:$dst), (ins FP64:$src),
181                         "cgdbr\t{$dst, $src}",
182                         [(set GR64:$dst, (fp_to_sint FP64:$src))]>;
183
184//===----------------------------------------------------------------------===//
185// Test instructions (like AND but do not produce any result)
186
187// Integer comparisons
188let Defs = [PSW] in {
189def FCMP32rr : Pseudo<(outs), (ins FP32:$src1, FP32:$src2),
190                      "cebr\t$src1, $src2",
191                      [(SystemZcmp FP32:$src1, FP32:$src2), (implicit PSW)]>;
192def FCMP64rr : Pseudo<(outs), (ins FP64:$src1, FP64:$src2),
193                      "cdbr\t$src1, $src2",
194                      [(SystemZcmp FP64:$src1, FP64:$src2), (implicit PSW)]>;
195
196def FCMP32rm : Pseudo<(outs), (ins FP32:$src1, rriaddr:$src2),
197                      "ceb\t$src1, $src2",
198                      [(SystemZcmp FP32:$src1, (load rriaddr:$src2)),
199                       (implicit PSW)]>;
200def FCMP64rm : Pseudo<(outs), (ins FP64:$src1, rriaddr:$src2),
201                      "cdb\t$src1, $src2",
202                      [(SystemZcmp FP64:$src1, (load rriaddr:$src2)),
203                       (implicit PSW)]>;
204} // Defs = [PSW]
205