SystemZInstrInfo.cpp revision 185ef05ad6fdcaad1e831020b1f88d0046dd15d6
11d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand//===-- SystemZInstrInfo.cpp - SystemZ instruction information ------------===// 21d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand// 31d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand// The LLVM Compiler Infrastructure 41d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand// 51d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand// This file is distributed under the University of Illinois Open Source 61d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand// License. See LICENSE.TXT for details. 71d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand// 81d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand//===----------------------------------------------------------------------===// 91d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand// 101d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand// This file contains the SystemZ implementation of the TargetInstrInfo class. 111d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand// 121d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand//===----------------------------------------------------------------------===// 131d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 141d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand#include "SystemZInstrInfo.h" 1593c2125c3979bcb4656daf3c2fb5748fb3973e1aRichard Sandiford#include "SystemZTargetMachine.h" 161d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand#include "SystemZInstrBuilder.h" 1793c2125c3979bcb4656daf3c2fb5748fb3973e1aRichard Sandiford#include "llvm/CodeGen/LiveVariables.h" 181ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford#include "llvm/CodeGen/MachineRegisterInfo.h" 191d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 201d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand#define GET_INSTRINFO_CTOR 211d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand#define GET_INSTRMAP_INFO 221d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand#include "SystemZGenInstrInfo.inc" 231d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 241d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigandusing namespace llvm; 251d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 26b3f912b510f8040690864126351b7021980558bbRichard Sandiford// Return a mask with Count low bits set. 27b3f912b510f8040690864126351b7021980558bbRichard Sandifordstatic uint64_t allOnes(unsigned int Count) { 28b3f912b510f8040690864126351b7021980558bbRichard Sandiford return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1; 29b3f912b510f8040690864126351b7021980558bbRichard Sandiford} 30b3f912b510f8040690864126351b7021980558bbRichard Sandiford 3155d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford// Reg should be a 32-bit GPR. Return true if it is a high register rather 3255d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford// than a low register. 3355d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandifordstatic bool isHighReg(unsigned int Reg) { 3455d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford if (SystemZ::GRH32BitRegClass.contains(Reg)) 3555d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford return true; 3655d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford assert(SystemZ::GR32BitRegClass.contains(Reg) && "Invalid GRX32"); 3755d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford return false; 3855d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford} 3955d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford 401d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich WeigandSystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm) 411d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP), 4293c2125c3979bcb4656daf3c2fb5748fb3973e1aRichard Sandiford RI(tm), TM(tm) { 431d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand} 441d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 451d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand// MI is a 128-bit load or store. Split it into two 64-bit loads or stores, 461d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand// each having the opcode given by NewOpcode. 471d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigandvoid SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI, 481d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand unsigned NewOpcode) const { 491d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand MachineBasicBlock *MBB = MI->getParent(); 501d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand MachineFunction &MF = *MBB->getParent(); 511d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 521d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // Get two load or store instructions. Use the original instruction for one 531d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // of them (arbitarily the second here) and create a clone for the other. 541d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand MachineInstr *EarlierMI = MF.CloneMachineInstr(MI); 551d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand MBB->insert(MI, EarlierMI); 561d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 571d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // Set up the two 64-bit registers. 581d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand MachineOperand &HighRegOp = EarlierMI->getOperand(0); 591d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand MachineOperand &LowRegOp = MI->getOperand(0); 60745ca1eed7dc0a056b066f16aea750ce6fa8a530Richard Sandiford HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64)); 61745ca1eed7dc0a056b066f16aea750ce6fa8a530Richard Sandiford LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64)); 621d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 631d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // The address in the first (high) instruction is already correct. 641d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // Adjust the offset in the second (low) instruction. 651d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand MachineOperand &HighOffsetOp = EarlierMI->getOperand(2); 661d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand MachineOperand &LowOffsetOp = MI->getOperand(2); 671d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand LowOffsetOp.setImm(LowOffsetOp.getImm() + 8); 681d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 691d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // Set the opcodes. 701d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm()); 711d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm()); 721d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand assert(HighOpcode && LowOpcode && "Both offsets should be in range"); 731d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 741d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand EarlierMI->setDesc(get(HighOpcode)); 751d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand MI->setDesc(get(LowOpcode)); 761d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand} 771d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 781d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand// Split ADJDYNALLOC instruction MI. 791d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigandvoid SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const { 801d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand MachineBasicBlock *MBB = MI->getParent(); 811d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand MachineFunction &MF = *MBB->getParent(); 821d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand MachineFrameInfo *MFFrame = MF.getFrameInfo(); 831d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand MachineOperand &OffsetMO = MI->getOperand(2); 841d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 851d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand uint64_t Offset = (MFFrame->getMaxCallFrameSize() + 861d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand SystemZMC::CallFrameSize + 871d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand OffsetMO.getImm()); 881d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset); 891d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand assert(NewOpcode && "No support for huge argument lists yet"); 901d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand MI->setDesc(get(NewOpcode)); 911d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand OffsetMO.setImm(Offset); 921d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand} 931d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 944c8feae136bbb54ba09d8f8dc7e61714270f7cd5Richard Sandiford// MI is an RI-style pseudo instruction. Replace it with LowOpcode 954c8feae136bbb54ba09d8f8dc7e61714270f7cd5Richard Sandiford// if the first operand is a low GR32 and HighOpcode if the first operand 964c8feae136bbb54ba09d8f8dc7e61714270f7cd5Richard Sandiford// is a high GR32. ConvertHigh is true if LowOpcode takes a signed operand 974c8feae136bbb54ba09d8f8dc7e61714270f7cd5Richard Sandiford// and HighOpcode takes an unsigned 32-bit operand. In those cases, 984c8feae136bbb54ba09d8f8dc7e61714270f7cd5Richard Sandiford// MI has the same kind of operand as LowOpcode, so needs to be converted 994c8feae136bbb54ba09d8f8dc7e61714270f7cd5Richard Sandiford// if HighOpcode is used. 1004c8feae136bbb54ba09d8f8dc7e61714270f7cd5Richard Sandifordvoid SystemZInstrInfo::expandRIPseudo(MachineInstr *MI, unsigned LowOpcode, 1014c8feae136bbb54ba09d8f8dc7e61714270f7cd5Richard Sandiford unsigned HighOpcode, 1024c8feae136bbb54ba09d8f8dc7e61714270f7cd5Richard Sandiford bool ConvertHigh) const { 1034c8feae136bbb54ba09d8f8dc7e61714270f7cd5Richard Sandiford unsigned Reg = MI->getOperand(0).getReg(); 1044c8feae136bbb54ba09d8f8dc7e61714270f7cd5Richard Sandiford bool IsHigh = isHighReg(Reg); 1054c8feae136bbb54ba09d8f8dc7e61714270f7cd5Richard Sandiford MI->setDesc(get(IsHigh ? HighOpcode : LowOpcode)); 1064c8feae136bbb54ba09d8f8dc7e61714270f7cd5Richard Sandiford if (IsHigh && ConvertHigh) 1074c8feae136bbb54ba09d8f8dc7e61714270f7cd5Richard Sandiford MI->getOperand(1).setImm(uint32_t(MI->getOperand(1).getImm())); 1084c8feae136bbb54ba09d8f8dc7e61714270f7cd5Richard Sandiford} 1094c8feae136bbb54ba09d8f8dc7e61714270f7cd5Richard Sandiford 11055d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford// MI is a three-operand RIE-style pseudo instruction. Replace it with 11155d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford// LowOpcode3 if the registers are both low GR32s, otherwise use a move 11255d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford// followed by HighOpcode or LowOpcode, depending on whether the target 11355d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford// is a high or low GR32. 11455d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandifordvoid SystemZInstrInfo::expandRIEPseudo(MachineInstr *MI, unsigned LowOpcode, 11555d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford unsigned LowOpcodeK, 11655d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford unsigned HighOpcode) const { 11755d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford unsigned DestReg = MI->getOperand(0).getReg(); 11855d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford unsigned SrcReg = MI->getOperand(1).getReg(); 11955d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford bool DestIsHigh = isHighReg(DestReg); 12055d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford bool SrcIsHigh = isHighReg(SrcReg); 12179e2ed4d838354d8aeaadbbfe0a3779d63e72b25Richard Sandiford if (!DestIsHigh && !SrcIsHigh) 12279e2ed4d838354d8aeaadbbfe0a3779d63e72b25Richard Sandiford MI->setDesc(get(LowOpcodeK)); 12379e2ed4d838354d8aeaadbbfe0a3779d63e72b25Richard Sandiford else { 12479e2ed4d838354d8aeaadbbfe0a3779d63e72b25Richard Sandiford emitGRX32Move(*MI->getParent(), MI, MI->getDebugLoc(), 12579e2ed4d838354d8aeaadbbfe0a3779d63e72b25Richard Sandiford DestReg, SrcReg, SystemZ::LR, 32, 12679e2ed4d838354d8aeaadbbfe0a3779d63e72b25Richard Sandiford MI->getOperand(1).isKill()); 12779e2ed4d838354d8aeaadbbfe0a3779d63e72b25Richard Sandiford MI->setDesc(get(DestIsHigh ? HighOpcode : LowOpcode)); 12879e2ed4d838354d8aeaadbbfe0a3779d63e72b25Richard Sandiford MI->getOperand(1).setReg(DestReg); 12979e2ed4d838354d8aeaadbbfe0a3779d63e72b25Richard Sandiford } 13079e2ed4d838354d8aeaadbbfe0a3779d63e72b25Richard Sandiford} 13179e2ed4d838354d8aeaadbbfe0a3779d63e72b25Richard Sandiford 13255d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford// MI is an RXY-style pseudo instruction. Replace it with LowOpcode 13355d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford// if the first operand is a low GR32 and HighOpcode if the first operand 13455d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford// is a high GR32. 13555d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandifordvoid SystemZInstrInfo::expandRXYPseudo(MachineInstr *MI, unsigned LowOpcode, 13655d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford unsigned HighOpcode) const { 13755d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford unsigned Reg = MI->getOperand(0).getReg(); 13855d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford unsigned Opcode = getOpcodeForOffset(isHighReg(Reg) ? HighOpcode : LowOpcode, 13955d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford MI->getOperand(2).getImm()); 14055d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford MI->setDesc(get(Opcode)); 14155d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford} 14255d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford 14355d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford// MI is an RR-style pseudo instruction that zero-extends the low Size bits 14455d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford// of one GRX32 into another. Replace it with LowOpcode if both operands 14555d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford// are low registers, otherwise use RISB[LH]G. 14655d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandifordvoid SystemZInstrInfo::expandZExtPseudo(MachineInstr *MI, unsigned LowOpcode, 14755d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford unsigned Size) const { 14855d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford emitGRX32Move(*MI->getParent(), MI, MI->getDebugLoc(), 14955d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford MI->getOperand(0).getReg(), MI->getOperand(1).getReg(), 15055d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford LowOpcode, Size, MI->getOperand(1).isKill()); 15155d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford MI->eraseFromParent(); 15255d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford} 15355d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford 15455d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford// Emit a zero-extending move from 32-bit GPR SrcReg to 32-bit GPR 15555d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford// DestReg before MBBI in MBB. Use LowLowOpcode when both DestReg and SrcReg 15655d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford// are low registers, otherwise use RISB[LH]G. Size is the number of bits 15755d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford// taken from the low end of SrcReg (8 for LLCR, 16 for LLHR and 32 for LR). 15855d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford// KillSrc is true if this move is the last use of SrcReg. 15955d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandifordvoid SystemZInstrInfo::emitGRX32Move(MachineBasicBlock &MBB, 16055d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford MachineBasicBlock::iterator MBBI, 16155d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford DebugLoc DL, unsigned DestReg, 16255d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford unsigned SrcReg, unsigned LowLowOpcode, 1631d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand unsigned Size, bool KillSrc) const { 1641d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand unsigned Opcode; 1651d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand bool DestIsHigh = isHighReg(DestReg); 1661d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand bool SrcIsHigh = isHighReg(SrcReg); 1671d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand if (DestIsHigh && SrcIsHigh) 1681ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford Opcode = SystemZ::RISBHH; 1691ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford else if (DestIsHigh && !SrcIsHigh) 1701d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand Opcode = SystemZ::RISBHL; 1711d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand else if (!DestIsHigh && SrcIsHigh) 1721d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand Opcode = SystemZ::RISBLH; 1731d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand else { 1741d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg) 1751d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand .addReg(SrcReg, getKillRegState(KillSrc)); 1761d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return; 1771d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand } 1781d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0); 1791d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand BuildMI(MBB, MBBI, DL, get(Opcode), DestReg) 1801d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand .addReg(DestReg, RegState::Undef) 1811d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand .addReg(SrcReg, getKillRegState(KillSrc)) 1821d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand .addImm(32 - Size).addImm(128 + 31).addImm(Rotate); 1831d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand} 1841d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 1851d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand// If MI is a simple load or store for a frame object, return the register 1861d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand// it loads or stores and set FrameIndex to the index of the frame object. 1871d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand// Return 0 otherwise. 1881d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand// 1891d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand// Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores. 1901d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigandstatic int isSimpleMove(const MachineInstr *MI, int &FrameIndex, 19171804149a3a6f6c081b874869b27fafe7d3288ceRichard Sandiford unsigned Flag) { 19271804149a3a6f6c081b874869b27fafe7d3288ceRichard Sandiford const MCInstrDesc &MCID = MI->getDesc(); 19371804149a3a6f6c081b874869b27fafe7d3288ceRichard Sandiford if ((MCID.TSFlags & Flag) && 19471804149a3a6f6c081b874869b27fafe7d3288ceRichard Sandiford MI->getOperand(1).isFI() && 19571804149a3a6f6c081b874869b27fafe7d3288ceRichard Sandiford MI->getOperand(2).getImm() == 0 && 19671804149a3a6f6c081b874869b27fafe7d3288ceRichard Sandiford MI->getOperand(3).getReg() == 0) { 19771804149a3a6f6c081b874869b27fafe7d3288ceRichard Sandiford FrameIndex = MI->getOperand(1).getIndex(); 19871804149a3a6f6c081b874869b27fafe7d3288ceRichard Sandiford return MI->getOperand(0).getReg(); 19971804149a3a6f6c081b874869b27fafe7d3288ceRichard Sandiford } 20071804149a3a6f6c081b874869b27fafe7d3288ceRichard Sandiford return 0; 20171804149a3a6f6c081b874869b27fafe7d3288ceRichard Sandiford} 20271804149a3a6f6c081b874869b27fafe7d3288ceRichard Sandiford 20371804149a3a6f6c081b874869b27fafe7d3288ceRichard Sandifordunsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 20471804149a3a6f6c081b874869b27fafe7d3288ceRichard Sandiford int &FrameIndex) const { 20571804149a3a6f6c081b874869b27fafe7d3288ceRichard Sandiford return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXLoad); 20671804149a3a6f6c081b874869b27fafe7d3288ceRichard Sandiford} 20771804149a3a6f6c081b874869b27fafe7d3288ceRichard Sandiford 20871804149a3a6f6c081b874869b27fafe7d3288ceRichard Sandifordunsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 20971804149a3a6f6c081b874869b27fafe7d3288ceRichard Sandiford int &FrameIndex) const { 21071804149a3a6f6c081b874869b27fafe7d3288ceRichard Sandiford return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXStore); 21171804149a3a6f6c081b874869b27fafe7d3288ceRichard Sandiford} 21271804149a3a6f6c081b874869b27fafe7d3288ceRichard Sandiford 21371804149a3a6f6c081b874869b27fafe7d3288ceRichard Sandifordbool SystemZInstrInfo::isStackSlotCopy(const MachineInstr *MI, 21471804149a3a6f6c081b874869b27fafe7d3288ceRichard Sandiford int &DestFrameIndex, 21571804149a3a6f6c081b874869b27fafe7d3288ceRichard Sandiford int &SrcFrameIndex) const { 2161d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // Check for MVC 0(Length,FI1),0(FI2) 2171d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand const MachineFrameInfo *MFI = MI->getParent()->getParent()->getFrameInfo(); 2181d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand if (MI->getOpcode() != SystemZ::MVC || 2191d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand !MI->getOperand(0).isFI() || 2201d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand MI->getOperand(1).getImm() != 0 || 2211d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand !MI->getOperand(3).isFI() || 2221d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand MI->getOperand(4).getImm() != 0) 2231d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return false; 2241d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 2251d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // Check that Length covers the full slots. 2261d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand int64_t Length = MI->getOperand(2).getImm(); 2271d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand unsigned FI1 = MI->getOperand(0).getIndex(); 2281d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand unsigned FI2 = MI->getOperand(3).getIndex(); 2291d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand if (MFI->getObjectSize(FI1) != Length || 2301d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand MFI->getObjectSize(FI2) != Length) 2311d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return false; 2321d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 2331d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand DestFrameIndex = FI1; 2341d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand SrcFrameIndex = FI2; 2351d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return true; 2361d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand} 2371d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 23806c3c9a9e1cc313d911e939e3e994feaf43cc3a7Richard Sandifordbool SystemZInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 2391d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand MachineBasicBlock *&TBB, 2401d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand MachineBasicBlock *&FBB, 2411d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand SmallVectorImpl<MachineOperand> &Cond, 24206c3c9a9e1cc313d911e939e3e994feaf43cc3a7Richard Sandiford bool AllowModify) const { 24306c3c9a9e1cc313d911e939e3e994feaf43cc3a7Richard Sandiford // Most of the code and comments here are boilerplate. 2441d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 2451d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // Start from the bottom of the block and work up, examining the 246d50bcb2162a529534da42748ab4a418bfc9aaf06Richard Sandiford // terminator instructions. 247d50bcb2162a529534da42748ab4a418bfc9aaf06Richard Sandiford MachineBasicBlock::iterator I = MBB.end(); 248d50bcb2162a529534da42748ab4a418bfc9aaf06Richard Sandiford while (I != MBB.begin()) { 249d50bcb2162a529534da42748ab4a418bfc9aaf06Richard Sandiford --I; 25006c3c9a9e1cc313d911e939e3e994feaf43cc3a7Richard Sandiford if (I->isDebugValue()) 2511d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand continue; 2521d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 25306c3c9a9e1cc313d911e939e3e994feaf43cc3a7Richard Sandiford // Working from the bottom, when we see a non-terminator instruction, we're 2541d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // done. 2551d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand if (!isUnpredicatedTerminator(I)) 2561d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand break; 2571d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 2581d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // A terminator that isn't a branch can't easily be handled by this 2591d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // analysis. 2601d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand if (!I->isBranch()) 2611d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return true; 2621d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 2631d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // Can't handle indirect branches. 2641d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand SystemZII::Branch Branch(getBranchInfo(I)); 26506c3c9a9e1cc313d911e939e3e994feaf43cc3a7Richard Sandiford if (!Branch.Target->isMBB()) 2661d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return true; 2671d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 2681d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // Punt on compound branches. 2691d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand if (Branch.Type != SystemZII::BranchNormal) 2701d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return true; 2711d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 2721d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand if (Branch.CCMask == SystemZ::CCMASK_ANY) { 27306c3c9a9e1cc313d911e939e3e994feaf43cc3a7Richard Sandiford // Handle unconditional branches. 2741d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand if (!AllowModify) { 2751d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand TBB = Branch.Target->getMBB(); 2761d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand continue; 2771d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand } 2781d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 2791d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // If the block has any instructions after a JMP, delete them. 2801d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand while (llvm::next(I) != MBB.end()) 28106c3c9a9e1cc313d911e939e3e994feaf43cc3a7Richard Sandiford llvm::next(I)->eraseFromParent(); 2826824f127f90197b26af93cf5d6c13b7941567e54Richard Sandiford 28306c3c9a9e1cc313d911e939e3e994feaf43cc3a7Richard Sandiford Cond.clear(); 2841d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand FBB = 0; 2851d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 2861d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // Delete the JMP if it's equivalent to a fall-through. 2871d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand if (MBB.isLayoutSuccessor(Branch.Target->getMBB())) { 2886824f127f90197b26af93cf5d6c13b7941567e54Richard Sandiford TBB = 0; 2891d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand I->eraseFromParent(); 2901d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand I = MBB.end(); 2911d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand continue; 29206c3c9a9e1cc313d911e939e3e994feaf43cc3a7Richard Sandiford } 2931d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 2941d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // TBB is used to indicate the unconditinal destination. 2951d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand TBB = Branch.Target->getMBB(); 2966824f127f90197b26af93cf5d6c13b7941567e54Richard Sandiford continue; 2976824f127f90197b26af93cf5d6c13b7941567e54Richard Sandiford } 2986824f127f90197b26af93cf5d6c13b7941567e54Richard Sandiford 2991d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // Working from the bottom, handle the first conditional branch. 3001d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand if (Cond.empty()) { 3011d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // FIXME: add X86-style branch swap 3026824f127f90197b26af93cf5d6c13b7941567e54Richard Sandiford FBB = TBB; 3031d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand TBB = Branch.Target->getMBB(); 3041d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand Cond.push_back(MachineOperand::CreateImm(Branch.CCValid)); 3051d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand Cond.push_back(MachineOperand::CreateImm(Branch.CCMask)); 3061d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand continue; 3071d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand } 3081d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 3091d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // Handle subsequent conditional branches. 3101d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand assert(Cond.size() == 2 && TBB && "Should have seen a conditional branch"); 3111d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 3121d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // Only handle the case where all conditional branches branch to the same 3131d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // destination. 3141d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand if (TBB != Branch.Target->getMBB()) 3151d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return true; 3161d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 31706c3c9a9e1cc313d911e939e3e994feaf43cc3a7Richard Sandiford // If the conditions are the same, we can leave them alone. 3181d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand unsigned OldCCValid = Cond[0].getImm(); 31906c3c9a9e1cc313d911e939e3e994feaf43cc3a7Richard Sandiford unsigned OldCCMask = Cond[1].getImm(); 3201d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand if (OldCCValid == Branch.CCValid && OldCCMask == Branch.CCMask) 3211d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand continue; 3221d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 3231d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // FIXME: Try combining conditions like X86 does. Should be easy on Z! 3241d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return false; 3251d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand } 3261d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 3271d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return false; 3281d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand} 3291d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 3306824f127f90197b26af93cf5d6c13b7941567e54Richard Sandifordunsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 3316824f127f90197b26af93cf5d6c13b7941567e54Richard Sandiford // Most of the code and comments here are boilerplate. 3326824f127f90197b26af93cf5d6c13b7941567e54Richard Sandiford MachineBasicBlock::iterator I = MBB.end(); 3336824f127f90197b26af93cf5d6c13b7941567e54Richard Sandiford unsigned Count = 0; 3346824f127f90197b26af93cf5d6c13b7941567e54Richard Sandiford 3356824f127f90197b26af93cf5d6c13b7941567e54Richard Sandiford while (I != MBB.begin()) { 3366824f127f90197b26af93cf5d6c13b7941567e54Richard Sandiford --I; 3371d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand if (I->isDebugValue()) 3381d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand continue; 3391d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand if (!I->isBranch()) 3401d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand break; 3411d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand if (!getBranchInfo(I).Target->isMBB()) 3421d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand break; 3431d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // Remove the branch. 3441d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand I->eraseFromParent(); 3451d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand I = MBB.end(); 3461d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand ++Count; 3471d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand } 3486824f127f90197b26af93cf5d6c13b7941567e54Richard Sandiford 3491d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return Count; 3501d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand} 3511d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 3521d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigandbool SystemZInstrInfo:: 3531d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich WeigandReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 35444b486ed78c60b50aa14d4eed92ee828d4d44293Richard Sandiford assert(Cond.size() == 2 && "Invalid condition"); 3551d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm()); 3561d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return false; 3571d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand} 3581d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 3591d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigandunsigned 3606824f127f90197b26af93cf5d6c13b7941567e54Richard SandifordSystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 3616824f127f90197b26af93cf5d6c13b7941567e54Richard Sandiford MachineBasicBlock *FBB, 3626824f127f90197b26af93cf5d6c13b7941567e54Richard Sandiford const SmallVectorImpl<MachineOperand> &Cond, 3636824f127f90197b26af93cf5d6c13b7941567e54Richard Sandiford DebugLoc DL) const { 3641d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // In this function we output 32-bit branches, which should always 3651d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // have enough range. They can be shortened and relaxed by later code 3661d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // in the pipeline, if desired. 3671d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 36844b486ed78c60b50aa14d4eed92ee828d4d44293Richard Sandiford // Shouldn't be a fall through. 3691d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 3701d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand assert((Cond.size() == 2 || Cond.size() == 0) && 3711d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand "SystemZ branch conditions have one component!"); 3721d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 3731d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand if (Cond.empty()) { 374ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford // Unconditional branch? 375ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford assert(!FBB && "Unconditional branch with multiple successors!"); 376ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB); 377ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford return 1; 378ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford } 379ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford 380ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford // Conditional branch. 381ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford unsigned Count = 0; 382ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford unsigned CCValid = Cond[0].getImm(); 383ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford unsigned CCMask = Cond[1].getImm(); 384ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford BuildMI(&MBB, DL, get(SystemZ::BRC)) 385ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford .addImm(CCValid).addImm(CCMask).addMBB(TBB); 386ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford ++Count; 387ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford 388ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford if (FBB) { 389ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford // Two-way Conditional branch. Insert the second branch. 390ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB); 391ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford ++Count; 3926c51f89498dd813c8dd16e46069decf2897b31b2Richard Sandiford } 3936c51f89498dd813c8dd16e46069decf2897b31b2Richard Sandiford return Count; 3946c51f89498dd813c8dd16e46069decf2897b31b2Richard Sandiford} 395ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford 396ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandifordbool SystemZInstrInfo::analyzeCompare(const MachineInstr *MI, 397ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford unsigned &SrcReg, unsigned &SrcReg2, 398ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford int &Mask, int &Value) const { 399ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford assert(MI->isCompare() && "Caller should have checked for a comparison"); 400ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford 401ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford if (MI->getNumExplicitOperands() == 2 && 402ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford MI->getOperand(0).isReg() && 403ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford MI->getOperand(1).isImm()) { 404ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford SrcReg = MI->getOperand(0).getReg(); 405ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford SrcReg2 = 0; 406ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford Value = MI->getOperand(1).getImm(); 4076c51f89498dd813c8dd16e46069decf2897b31b2Richard Sandiford Mask = ~0; 4086c51f89498dd813c8dd16e46069decf2897b31b2Richard Sandiford return true; 4096c51f89498dd813c8dd16e46069decf2897b31b2Richard Sandiford } 4106c51f89498dd813c8dd16e46069decf2897b31b2Richard Sandiford 4116c51f89498dd813c8dd16e46069decf2897b31b2Richard Sandiford return false; 4126c51f89498dd813c8dd16e46069decf2897b31b2Richard Sandiford} 413ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford 4146c51f89498dd813c8dd16e46069decf2897b31b2Richard Sandiford// If Reg is a virtual register, return its definition, otherwise return null. 4156c51f89498dd813c8dd16e46069decf2897b31b2Richard Sandifordstatic MachineInstr *getDef(unsigned Reg, 4166c51f89498dd813c8dd16e46069decf2897b31b2Richard Sandiford const MachineRegisterInfo *MRI) { 4176c51f89498dd813c8dd16e46069decf2897b31b2Richard Sandiford if (TargetRegisterInfo::isPhysicalRegister(Reg)) 4186c51f89498dd813c8dd16e46069decf2897b31b2Richard Sandiford return 0; 4196c51f89498dd813c8dd16e46069decf2897b31b2Richard Sandiford return MRI->getUniqueVRegDef(Reg); 4206a079fef4fad3e6c2e07c9e1d0776e20a0b05b1eRichard Sandiford} 4216c51f89498dd813c8dd16e46069decf2897b31b2Richard Sandiford 4226a079fef4fad3e6c2e07c9e1d0776e20a0b05b1eRichard Sandiford// Return true if MI is a shift of type Opcode by Imm bits. 4236a079fef4fad3e6c2e07c9e1d0776e20a0b05b1eRichard Sandifordstatic bool isShift(MachineInstr *MI, int Opcode, int64_t Imm) { 4246a079fef4fad3e6c2e07c9e1d0776e20a0b05b1eRichard Sandiford return (MI->getOpcode() == Opcode && 4256a079fef4fad3e6c2e07c9e1d0776e20a0b05b1eRichard Sandiford !MI->getOperand(2).getReg() && 4266c51f89498dd813c8dd16e46069decf2897b31b2Richard Sandiford MI->getOperand(3).getImm() == Imm); 427ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford} 428ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford 4296c51f89498dd813c8dd16e46069decf2897b31b2Richard Sandiford// If the destination of MI has no uses, delete it as dead. 4306c51f89498dd813c8dd16e46069decf2897b31b2Richard Sandifordstatic void eraseIfDead(MachineInstr *MI, const MachineRegisterInfo *MRI) { 431ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford if (MRI->use_nodbg_empty(MI->getOperand(0).getReg())) 432ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford MI->eraseFromParent(); 4336c51f89498dd813c8dd16e46069decf2897b31b2Richard Sandiford} 434ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford 435ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford// Compare compares SrcReg against zero. Check whether SrcReg contains 436ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford// the result of an IPM sequence whose input CC survives until Compare, 437ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford// and whether Compare is therefore redundant. Delete it and return 438ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford// true if so. 439ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandifordstatic bool removeIPMBasedCompare(MachineInstr *Compare, unsigned SrcReg, 440ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford const MachineRegisterInfo *MRI, 441ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford const TargetRegisterInfo *TRI) { 442ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford MachineInstr *LGFR = 0; 4436c51f89498dd813c8dd16e46069decf2897b31b2Richard Sandiford MachineInstr *RLL = getDef(SrcReg, MRI); 444ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford if (RLL && RLL->getOpcode() == SystemZ::LGFR) { 445ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford LGFR = RLL; 446ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford RLL = getDef(LGFR->getOperand(1).getReg(), MRI); 447ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford } 4486a079fef4fad3e6c2e07c9e1d0776e20a0b05b1eRichard Sandiford if (!RLL || !isShift(RLL, SystemZ::RLL, 31)) 4496a079fef4fad3e6c2e07c9e1d0776e20a0b05b1eRichard Sandiford return false; 4506c51f89498dd813c8dd16e46069decf2897b31b2Richard Sandiford 4516c51f89498dd813c8dd16e46069decf2897b31b2Richard Sandiford MachineInstr *SRL = getDef(RLL->getOperand(1).getReg(), MRI); 4526c51f89498dd813c8dd16e46069decf2897b31b2Richard Sandiford if (!SRL || !isShift(SRL, SystemZ::SRL, 28)) 4536c51f89498dd813c8dd16e46069decf2897b31b2Richard Sandiford return false; 454ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford 455ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford MachineInstr *IPM = getDef(SRL->getOperand(1).getReg(), MRI); 456ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford if (!IPM || IPM->getOpcode() != SystemZ::IPM) 457ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford return false; 458ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford 459ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford // Check that there are no assignments to CC between the IPM and Compare, 460ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford if (IPM->getParent() != Compare->getParent()) 461ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford return false; 462ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford MachineBasicBlock::iterator MBBI = IPM, MBBE = Compare; 463ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford for (++MBBI; MBBI != MBBE; ++MBBI) { 464ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford MachineInstr *MI = MBBI; 465ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford if (MI->modifiesRegister(SystemZ::CC, TRI)) 4666c51f89498dd813c8dd16e46069decf2897b31b2Richard Sandiford return false; 467ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford } 468ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford 469ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford Compare->eraseFromParent(); 470ac168b8bc8773a083a10902f64e4ae57a925aee4Richard Sandiford if (LGFR) 471bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford eraseIfDead(LGFR, MRI); 472bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford eraseIfDead(RLL, MRI); 473bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford eraseIfDead(SRL, MRI); 474bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford eraseIfDead(IPM, MRI); 475bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford 476bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford return true; 477bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford} 478bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford 479bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandifordbool 480bf99364f819465536a6b230b95735b239e3fc7a5Richard SandifordSystemZInstrInfo::optimizeCompareInstr(MachineInstr *Compare, 481bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford unsigned SrcReg, unsigned SrcReg2, 482bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford int Mask, int Value, 483bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford const MachineRegisterInfo *MRI) const { 484bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford assert(!SrcReg2 && "Only optimizing constant comparisons so far"); 485bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford bool IsLogical = (Compare->getDesc().TSFlags & SystemZII::IsLogical) != 0; 486bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford if (Value == 0 && 487bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford !IsLogical && 488bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford removeIPMBasedCompare(Compare, SrcReg, MRI, TM.getRegisterInfo())) 489bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford return true; 490bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford return false; 491bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford} 492bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford 493bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford// If Opcode is a move that has a conditional variant, return that variant, 494bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford// otherwise return 0. 495bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandifordstatic unsigned getConditionalMove(unsigned Opcode) { 496bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford switch (Opcode) { 497bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford case SystemZ::LR: return SystemZ::LOCR; 498bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford case SystemZ::LGR: return SystemZ::LOCGR; 499bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford default: return 0; 500bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford } 501bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford} 502bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford 503bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandifordbool SystemZInstrInfo::isPredicable(MachineInstr *MI) const { 504bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford unsigned Opcode = MI->getOpcode(); 505bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford if (TM.getSubtargetImpl()->hasLoadStoreOnCond() && 506bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford getConditionalMove(Opcode)) 507bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford return true; 508bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford return false; 509bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford} 5106824f127f90197b26af93cf5d6c13b7941567e54Richard Sandiford 5116824f127f90197b26af93cf5d6c13b7941567e54Richard Sandifordbool SystemZInstrInfo:: 5126824f127f90197b26af93cf5d6c13b7941567e54Richard SandifordisProfitableToIfCvt(MachineBasicBlock &MBB, 513bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford unsigned NumCycles, unsigned ExtraPredCycles, 514bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford const BranchProbability &Probability) const { 515bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford // For now only convert single instructions. 516bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford return NumCycles == 1; 517bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford} 5186824f127f90197b26af93cf5d6c13b7941567e54Richard Sandiford 5198f0ad5ae8f2699f6ab13a229941a0b192273cae8Richard Sandifordbool SystemZInstrInfo:: 5208f0ad5ae8f2699f6ab13a229941a0b192273cae8Richard SandifordisProfitableToIfCvt(MachineBasicBlock &TMBB, 521bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford unsigned NumCyclesT, unsigned ExtraPredCyclesT, 522bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford MachineBasicBlock &FMBB, 523bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford unsigned NumCyclesF, unsigned ExtraPredCyclesF, 524bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford const BranchProbability &Probability) const { 525bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford // For now avoid converting mutually-exclusive cases. 526bf99364f819465536a6b230b95735b239e3fc7a5Richard Sandiford return false; 5271d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand} 5281d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 5291d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigandbool SystemZInstrInfo:: 5301d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich WeigandPredicateInstruction(MachineInstr *MI, 5311d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand const SmallVectorImpl<MachineOperand> &Pred) const { 5321d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand assert(Pred.size() == 2 && "Invalid condition"); 5331d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand unsigned CCValid = Pred[0].getImm(); 534745ca1eed7dc0a056b066f16aea750ce6fa8a530Richard Sandiford unsigned CCMask = Pred[1].getImm(); 535745ca1eed7dc0a056b066f16aea750ce6fa8a530Richard Sandiford assert(CCMask > 0 && CCMask < 15 && "Invalid predicate"); 536745ca1eed7dc0a056b066f16aea750ce6fa8a530Richard Sandiford unsigned Opcode = MI->getOpcode(); 537745ca1eed7dc0a056b066f16aea750ce6fa8a530Richard Sandiford if (TM.getSubtargetImpl()->hasLoadStoreOnCond()) { 5381d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand if (unsigned CondOpcode = getConditionalMove(Opcode)) { 5391d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand MI->setDesc(get(CondOpcode)); 5401d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand MachineInstrBuilder(*MI->getParent()->getParent(), MI) 54155d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford .addImm(CCValid).addImm(CCMask) 54255d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford .addReg(SystemZ::CC, RegState::Implicit);; 54355d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford return true; 54455d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford } 54555d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford } 5461d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return false; 5471d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand} 54855d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford 5491d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigandvoid 5501d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich WeigandSystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 5511d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand MachineBasicBlock::iterator MBBI, DebugLoc DL, 5521d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand unsigned DestReg, unsigned SrcReg, 5531d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand bool KillSrc) const { 5541d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // Split 128-bit GPR moves into two 64-bit moves. This handles ADDR128 too. 5551d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) { 5561d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_h64), 5571d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc); 5581d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_l64), 5591d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc); 5601d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return; 5611d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand } 5621d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 5631d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand if (SystemZ::GRX32BitRegClass.contains(DestReg, SrcReg)) { 5641d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand emitGRX32Move(MBB, MBBI, DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc); 5651d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return; 5661d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand } 5671d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 5681d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // Everything else needs only one instruction. 5691d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand unsigned Opcode; 5701d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg)) 5711d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand Opcode = SystemZ::LGR; 5721d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg)) 5731d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand Opcode = SystemZ::LER; 5741d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg)) 5751d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand Opcode = SystemZ::LDR; 5761d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg)) 5771d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand Opcode = SystemZ::LXR; 5781d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand else 5791d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand llvm_unreachable("Impossible reg-to-reg copy"); 5801d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 5811d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand BuildMI(MBB, MBBI, DL, get(Opcode), DestReg) 5821d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand .addReg(SrcReg, getKillRegState(KillSrc)); 5831d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand} 5841d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 5851d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigandvoid 5861d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich WeigandSystemZInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 5871d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand MachineBasicBlock::iterator MBBI, 5881d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand unsigned SrcReg, bool isKill, 5891d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand int FrameIdx, 5901d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand const TargetRegisterClass *RC, 5911d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand const TargetRegisterInfo *TRI) const { 5921d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 5931d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 5941d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // Callers may expect a single instruction, so keep 128-bit moves 5951d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // together for now and lower them after register allocation. 5961ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford unsigned LoadOpcode, StoreOpcode; 5971ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode); 5981ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode)) 5991ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford .addReg(SrcReg, getKillRegState(isKill)), FrameIdx); 6001ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford} 6011ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford 6021ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandifordvoid 6031ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard SandifordSystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 6041ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford MachineBasicBlock::iterator MBBI, 605b3f912b510f8040690864126351b7021980558bbRichard Sandiford unsigned DestReg, int FrameIdx, 606b3f912b510f8040690864126351b7021980558bbRichard Sandiford const TargetRegisterClass *RC, 607b3f912b510f8040690864126351b7021980558bbRichard Sandiford const TargetRegisterInfo *TRI) const { 608b3f912b510f8040690864126351b7021980558bbRichard Sandiford DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 609b3f912b510f8040690864126351b7021980558bbRichard Sandiford 610b3f912b510f8040690864126351b7021980558bbRichard Sandiford // Callers may expect a single instruction, so keep 128-bit moves 611b3f912b510f8040690864126351b7021980558bbRichard Sandiford // together for now and lower them after register allocation. 612b3f912b510f8040690864126351b7021980558bbRichard Sandiford unsigned LoadOpcode, StoreOpcode; 613b3f912b510f8040690864126351b7021980558bbRichard Sandiford getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode); 614b3f912b510f8040690864126351b7021980558bbRichard Sandiford addFrameReference(BuildMI(MBB, MBBI, DL, get(LoadOpcode), DestReg), 615b3f912b510f8040690864126351b7021980558bbRichard Sandiford FrameIdx); 616b3f912b510f8040690864126351b7021980558bbRichard Sandiford} 617b3f912b510f8040690864126351b7021980558bbRichard Sandiford 618b3f912b510f8040690864126351b7021980558bbRichard Sandiford// Return true if MI is a simple load or store with a 12-bit displacement 619259a6006e89576704e52e7392ef2bfd83f277ce3Richard Sandiford// and no index. Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores. 620259a6006e89576704e52e7392ef2bfd83f277ce3Richard Sandifordstatic bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) { 621259a6006e89576704e52e7392ef2bfd83f277ce3Richard Sandiford const MCInstrDesc &MCID = MI->getDesc(); 622259a6006e89576704e52e7392ef2bfd83f277ce3Richard Sandiford return ((MCID.TSFlags & Flag) && 623b3f912b510f8040690864126351b7021980558bbRichard Sandiford isUInt<12>(MI->getOperand(2).getImm()) && 624b3f912b510f8040690864126351b7021980558bbRichard Sandiford MI->getOperand(3).getReg() == 0); 625259a6006e89576704e52e7392ef2bfd83f277ce3Richard Sandiford} 626259a6006e89576704e52e7392ef2bfd83f277ce3Richard Sandiford 627b3f912b510f8040690864126351b7021980558bbRichard Sandifordnamespace { 628b3f912b510f8040690864126351b7021980558bbRichard Sandiford struct LogicOp { 629b3f912b510f8040690864126351b7021980558bbRichard Sandiford LogicOp() : RegSize(0), ImmLSB(0), ImmSize(0) {} 630b3f912b510f8040690864126351b7021980558bbRichard Sandiford LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize) 631b3f912b510f8040690864126351b7021980558bbRichard Sandiford : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {} 632b3f912b510f8040690864126351b7021980558bbRichard Sandiford 633b3f912b510f8040690864126351b7021980558bbRichard Sandiford operator bool() const { return RegSize; } 634b3f912b510f8040690864126351b7021980558bbRichard Sandiford 635b3f912b510f8040690864126351b7021980558bbRichard Sandiford unsigned RegSize, ImmLSB, ImmSize; 636b3f912b510f8040690864126351b7021980558bbRichard Sandiford }; 637b3f912b510f8040690864126351b7021980558bbRichard Sandiford} 638b3f912b510f8040690864126351b7021980558bbRichard Sandiford 639b3f912b510f8040690864126351b7021980558bbRichard Sandifordstatic LogicOp interpretAndImmediate(unsigned Opcode) { 640b3f912b510f8040690864126351b7021980558bbRichard Sandiford switch (Opcode) { 641b3f912b510f8040690864126351b7021980558bbRichard Sandiford case SystemZ::NILMux: return LogicOp(32, 0, 16); 642b3f912b510f8040690864126351b7021980558bbRichard Sandiford case SystemZ::NIHMux: return LogicOp(32, 16, 16); 643b3f912b510f8040690864126351b7021980558bbRichard Sandiford case SystemZ::NILL64: return LogicOp(64, 0, 16); 644b3f912b510f8040690864126351b7021980558bbRichard Sandiford case SystemZ::NILH64: return LogicOp(64, 16, 16); 645b3f912b510f8040690864126351b7021980558bbRichard Sandiford case SystemZ::NIHL64: return LogicOp(64, 32, 16); 646b3f912b510f8040690864126351b7021980558bbRichard Sandiford case SystemZ::NIHH64: return LogicOp(64, 48, 16); 647b3f912b510f8040690864126351b7021980558bbRichard Sandiford case SystemZ::NIFMux: return LogicOp(32, 0, 32); 6481ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford case SystemZ::NILF64: return LogicOp(64, 0, 32); 64993c2125c3979bcb4656daf3c2fb5748fb3973e1aRichard Sandiford case SystemZ::NIHF64: return LogicOp(64, 32, 32); 65093c2125c3979bcb4656daf3c2fb5748fb3973e1aRichard Sandiford default: return LogicOp(); 65193c2125c3979bcb4656daf3c2fb5748fb3973e1aRichard Sandiford } 65293c2125c3979bcb4656daf3c2fb5748fb3973e1aRichard Sandiford} 65393c2125c3979bcb4656daf3c2fb5748fb3973e1aRichard Sandiford 65493c2125c3979bcb4656daf3c2fb5748fb3973e1aRichard Sandiford// Used to return from convertToThreeAddress after replacing two-address 65593c2125c3979bcb4656daf3c2fb5748fb3973e1aRichard Sandiford// instruction OldMI with three-address instruction NewMI. 65693c2125c3979bcb4656daf3c2fb5748fb3973e1aRichard Sandifordstatic MachineInstr *finishConvertToThreeAddress(MachineInstr *OldMI, 65793c2125c3979bcb4656daf3c2fb5748fb3973e1aRichard Sandiford MachineInstr *NewMI, 65893c2125c3979bcb4656daf3c2fb5748fb3973e1aRichard Sandiford LiveVariables *LV) { 65993c2125c3979bcb4656daf3c2fb5748fb3973e1aRichard Sandiford if (LV) { 66093c2125c3979bcb4656daf3c2fb5748fb3973e1aRichard Sandiford unsigned NumOps = OldMI->getNumOperands(); 66193c2125c3979bcb4656daf3c2fb5748fb3973e1aRichard Sandiford for (unsigned I = 1; I < NumOps; ++I) { 66293c2125c3979bcb4656daf3c2fb5748fb3973e1aRichard Sandiford MachineOperand &Op = OldMI->getOperand(I); 66393c2125c3979bcb4656daf3c2fb5748fb3973e1aRichard Sandiford if (Op.isReg() && Op.isKill()) 66493c2125c3979bcb4656daf3c2fb5748fb3973e1aRichard Sandiford LV->replaceKillInstruction(Op.getReg(), OldMI, NewMI); 665b3f912b510f8040690864126351b7021980558bbRichard Sandiford } 66693c2125c3979bcb4656daf3c2fb5748fb3973e1aRichard Sandiford } 667b3f912b510f8040690864126351b7021980558bbRichard Sandiford return NewMI; 668b3f912b510f8040690864126351b7021980558bbRichard Sandiford} 669b3f912b510f8040690864126351b7021980558bbRichard Sandiford 67093c2125c3979bcb4656daf3c2fb5748fb3973e1aRichard SandifordMachineInstr * 671b3f912b510f8040690864126351b7021980558bbRichard SandifordSystemZInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 67293c2125c3979bcb4656daf3c2fb5748fb3973e1aRichard Sandiford MachineBasicBlock::iterator &MBBI, 67393c2125c3979bcb4656daf3c2fb5748fb3973e1aRichard Sandiford LiveVariables *LV) const { 67493c2125c3979bcb4656daf3c2fb5748fb3973e1aRichard Sandiford MachineInstr *MI = MBBI; 675b3f912b510f8040690864126351b7021980558bbRichard Sandiford MachineBasicBlock *MBB = MI->getParent(); 676b3f912b510f8040690864126351b7021980558bbRichard Sandiford MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 677b3f912b510f8040690864126351b7021980558bbRichard Sandiford 678b3f912b510f8040690864126351b7021980558bbRichard Sandiford unsigned Opcode = MI->getOpcode(); 679b3f912b510f8040690864126351b7021980558bbRichard Sandiford unsigned NumOps = MI->getNumOperands(); 680b3f912b510f8040690864126351b7021980558bbRichard Sandiford 681b3f912b510f8040690864126351b7021980558bbRichard Sandiford // Try to convert something like SLL into SLLK, if supported. 682b3f912b510f8040690864126351b7021980558bbRichard Sandiford // We prefer to keep the two-operand form where possible both 683b3f912b510f8040690864126351b7021980558bbRichard Sandiford // because it tends to be shorter and because some instructions 684b3f912b510f8040690864126351b7021980558bbRichard Sandiford // have memory forms that can be used during spilling. 68555d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford if (TM.getSubtargetImpl()->hasDistinctOps()) { 686b3f912b510f8040690864126351b7021980558bbRichard Sandiford MachineOperand &Dest = MI->getOperand(0); 687b3f912b510f8040690864126351b7021980558bbRichard Sandiford MachineOperand &Src = MI->getOperand(1); 688b3f912b510f8040690864126351b7021980558bbRichard Sandiford unsigned DestReg = Dest.getReg(); 689b3f912b510f8040690864126351b7021980558bbRichard Sandiford unsigned SrcReg = Src.getReg(); 690b3f912b510f8040690864126351b7021980558bbRichard Sandiford // AHIMux is only really a three-operand instruction when both operands 691b3f912b510f8040690864126351b7021980558bbRichard Sandiford // are low registers. Try to constrain both operands to be low if 692b3f912b510f8040690864126351b7021980558bbRichard Sandiford // possible. 693b3f912b510f8040690864126351b7021980558bbRichard Sandiford if (Opcode == SystemZ::AHIMux && 694b3f912b510f8040690864126351b7021980558bbRichard Sandiford TargetRegisterInfo::isVirtualRegister(DestReg) && 695b3f912b510f8040690864126351b7021980558bbRichard Sandiford TargetRegisterInfo::isVirtualRegister(SrcReg) && 69655d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford MRI.getRegClass(DestReg)->contains(SystemZ::R1L) && 697b3f912b510f8040690864126351b7021980558bbRichard Sandiford MRI.getRegClass(SrcReg)->contains(SystemZ::R1L)) { 698b3f912b510f8040690864126351b7021980558bbRichard Sandiford MRI.constrainRegClass(DestReg, &SystemZ::GR32BitRegClass); 69993c2125c3979bcb4656daf3c2fb5748fb3973e1aRichard Sandiford MRI.constrainRegClass(SrcReg, &SystemZ::GR32BitRegClass); 700b3f912b510f8040690864126351b7021980558bbRichard Sandiford } 701b3f912b510f8040690864126351b7021980558bbRichard Sandiford int ThreeOperandOpcode = SystemZ::getThreeOperandOpcode(Opcode); 702b3f912b510f8040690864126351b7021980558bbRichard Sandiford if (ThreeOperandOpcode >= 0) { 703b3f912b510f8040690864126351b7021980558bbRichard Sandiford MachineInstrBuilder MIB = 704b3f912b510f8040690864126351b7021980558bbRichard Sandiford BuildMI(*MBB, MBBI, MI->getDebugLoc(), get(ThreeOperandOpcode)) 705b3f912b510f8040690864126351b7021980558bbRichard Sandiford .addOperand(Dest); 706b3f912b510f8040690864126351b7021980558bbRichard Sandiford // Keep the kill state, but drop the tied flag. 707b3f912b510f8040690864126351b7021980558bbRichard Sandiford MIB.addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg()); 70893c2125c3979bcb4656daf3c2fb5748fb3973e1aRichard Sandiford // Keep the remaining operands as-is. 70993c2125c3979bcb4656daf3c2fb5748fb3973e1aRichard Sandiford for (unsigned I = 2; I < NumOps; ++I) 71093c2125c3979bcb4656daf3c2fb5748fb3973e1aRichard Sandiford MIB.addOperand(MI->getOperand(I)); 71193c2125c3979bcb4656daf3c2fb5748fb3973e1aRichard Sandiford return finishConvertToThreeAddress(MI, MIB, LV); 71293c2125c3979bcb4656daf3c2fb5748fb3973e1aRichard Sandiford } 71393c2125c3979bcb4656daf3c2fb5748fb3973e1aRichard Sandiford } 71493c2125c3979bcb4656daf3c2fb5748fb3973e1aRichard Sandiford 7151ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford // Try to convert an AND into an RISBG-type instruction. 7161ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford if (LogicOp And = interpretAndImmediate(Opcode)) { 7171ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford uint64_t Imm = MI->getOperand(2).getImm() << And.ImmLSB; 7181ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford // AND IMMEDIATE leaves the other bits of the register unchanged. 7191ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB); 7201ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford unsigned Start, End; 7211ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford if (isRxSBGMask(Imm, And.RegSize, Start, End)) { 7221ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford unsigned NewOpcode; 7231ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford if (And.RegSize == 64) 7241ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford NewOpcode = SystemZ::RISBG; 7251ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford else { 7261ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford NewOpcode = SystemZ::RISBMux; 727985148ea873db018dbd2b53f066f5817a9b11aadNAKAMURA Takumi Start &= 31; 728985148ea873db018dbd2b53f066f5817a9b11aadNAKAMURA Takumi End &= 31; 72924dd7dbe7f2a3338a20314b3863f6b738cc1c298Benjamin Kramer } 7301ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford MachineOperand &Dest = MI->getOperand(0); 7316cf3cfa0ab1da0c52730fec103bbc69eb0370081Richard Sandiford MachineOperand &Src = MI->getOperand(1); 7326cf3cfa0ab1da0c52730fec103bbc69eb0370081Richard Sandiford MachineInstrBuilder MIB = 7336cf3cfa0ab1da0c52730fec103bbc69eb0370081Richard Sandiford BuildMI(*MBB, MI, MI->getDebugLoc(), get(NewOpcode)) 7346cf3cfa0ab1da0c52730fec103bbc69eb0370081Richard Sandiford .addOperand(Dest).addReg(0) 7356cf3cfa0ab1da0c52730fec103bbc69eb0370081Richard Sandiford .addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg()) 7366cf3cfa0ab1da0c52730fec103bbc69eb0370081Richard Sandiford .addImm(Start).addImm(End + 128).addImm(0); 7376cf3cfa0ab1da0c52730fec103bbc69eb0370081Richard Sandiford return finishConvertToThreeAddress(MI, MIB, LV); 7386cf3cfa0ab1da0c52730fec103bbc69eb0370081Richard Sandiford } 7396cf3cfa0ab1da0c52730fec103bbc69eb0370081Richard Sandiford } 7406cf3cfa0ab1da0c52730fec103bbc69eb0370081Richard Sandiford return 0; 7416cf3cfa0ab1da0c52730fec103bbc69eb0370081Richard Sandiford} 7426cf3cfa0ab1da0c52730fec103bbc69eb0370081Richard Sandiford 7436cf3cfa0ab1da0c52730fec103bbc69eb0370081Richard SandifordMachineInstr * 7446cf3cfa0ab1da0c52730fec103bbc69eb0370081Richard SandifordSystemZInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 7456cf3cfa0ab1da0c52730fec103bbc69eb0370081Richard Sandiford MachineInstr *MI, 7466cf3cfa0ab1da0c52730fec103bbc69eb0370081Richard Sandiford const SmallVectorImpl<unsigned> &Ops, 7476cf3cfa0ab1da0c52730fec103bbc69eb0370081Richard Sandiford int FrameIndex) const { 7486cf3cfa0ab1da0c52730fec103bbc69eb0370081Richard Sandiford const MachineFrameInfo *MFI = MF.getFrameInfo(); 7496cf3cfa0ab1da0c52730fec103bbc69eb0370081Richard Sandiford unsigned Size = MFI->getObjectSize(FrameIndex); 7506cf3cfa0ab1da0c52730fec103bbc69eb0370081Richard Sandiford 7516cf3cfa0ab1da0c52730fec103bbc69eb0370081Richard Sandiford // Eary exit for cases we don't care about 7526cf3cfa0ab1da0c52730fec103bbc69eb0370081Richard Sandiford if (Ops.size() != 1) 7531ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford return 0; 7541ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford 7551ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford unsigned OpNum = Ops[0]; 7561ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford assert(Size == MF.getRegInfo() 7571ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford .getRegClass(MI->getOperand(OpNum).getReg())->getSize() && 7580548a5487ab8648c7c017f87c507ea1bc38bbb1fRichard Sandiford "Invalid size combination"); 7590548a5487ab8648c7c017f87c507ea1bc38bbb1fRichard Sandiford 7600548a5487ab8648c7c017f87c507ea1bc38bbb1fRichard Sandiford unsigned Opcode = MI->getOpcode(); 7610548a5487ab8648c7c017f87c507ea1bc38bbb1fRichard Sandiford if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) { 7620548a5487ab8648c7c017f87c507ea1bc38bbb1fRichard Sandiford bool Op0IsGPR = (Opcode == SystemZ::LGDR); 7630548a5487ab8648c7c017f87c507ea1bc38bbb1fRichard Sandiford bool Op1IsGPR = (Opcode == SystemZ::LDGR); 7640548a5487ab8648c7c017f87c507ea1bc38bbb1fRichard Sandiford // If we're spilling the destination of an LDGR or LGDR, store the 7650548a5487ab8648c7c017f87c507ea1bc38bbb1fRichard Sandiford // source register instead. 7661ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford if (OpNum == 0) { 7671ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD; 7681ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford return BuildMI(MF, MI->getDebugLoc(), get(StoreOpcode)) 7691ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford .addOperand(MI->getOperand(1)).addFrameIndex(FrameIndex) 770cf1b5bd60ab7cf907bef20c3997ffb249b4fe90aRichard Sandiford .addImm(0).addReg(0); 7711ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford } 772e684b96e3c6513f88137afee7c344a4d2d9f0694Richard Sandiford // If we're spilling the source of an LDGR or LGDR, load the 7731ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford // destination register instead. 774e684b96e3c6513f88137afee7c344a4d2d9f0694Richard Sandiford if (OpNum == 1) { 7751ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD; 7761ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford unsigned Dest = MI->getOperand(0).getReg(); 777cf1b5bd60ab7cf907bef20c3997ffb249b4fe90aRichard Sandiford return BuildMI(MF, MI->getDebugLoc(), get(LoadOpcode), Dest) 7781ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford .addFrameIndex(FrameIndex).addImm(0).addReg(0); 7791ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford } 780e684b96e3c6513f88137afee7c344a4d2d9f0694Richard Sandiford } 781e684b96e3c6513f88137afee7c344a4d2d9f0694Richard Sandiford 7821ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford // Look for cases where the source of a simple store or the destination 7831ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford // of a simple load is being spilled. Try to use MVC instead. 7841ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford // 7851ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford // Although MVC is in practice a fast choice in these cases, it is still 786fa487e83a83c260d6a50f3df00a0eb012553a912Richard Sandiford // logically a bytewise copy. This means that we cannot use it if the 787fa487e83a83c260d6a50f3df00a0eb012553a912Richard Sandiford // load or store is volatile. We also wouldn't be able to use MVC if 7886cf3cfa0ab1da0c52730fec103bbc69eb0370081Richard Sandiford // the two memories partially overlap, but that case cannot occur here, 789fa487e83a83c260d6a50f3df00a0eb012553a912Richard Sandiford // because we know that one of the memories is a full frame index. 790fa487e83a83c260d6a50f3df00a0eb012553a912Richard Sandiford // 791fa487e83a83c260d6a50f3df00a0eb012553a912Richard Sandiford // For performance reasons, we also want to avoid using MVC if the addresses 792fa487e83a83c260d6a50f3df00a0eb012553a912Richard Sandiford // might be equal. We don't worry about that case here, because spill slot 793fa487e83a83c260d6a50f3df00a0eb012553a912Richard Sandiford // coloring happens later, and because we have special code to remove 794fa487e83a83c260d6a50f3df00a0eb012553a912Richard Sandiford // MVCs that turn out to be redundant. 795fa487e83a83c260d6a50f3df00a0eb012553a912Richard Sandiford if (OpNum == 0 && MI->hasOneMemOperand()) { 796fa487e83a83c260d6a50f3df00a0eb012553a912Richard Sandiford MachineMemOperand *MMO = *MI->memoperands_begin(); 797fa487e83a83c260d6a50f3df00a0eb012553a912Richard Sandiford if (MMO->getSize() == Size && !MMO->isVolatile()) { 798fa487e83a83c260d6a50f3df00a0eb012553a912Richard Sandiford // Handle conversion of loads. 799fa487e83a83c260d6a50f3df00a0eb012553a912Richard Sandiford if (isSimpleBD12Move(MI, SystemZII::SimpleBDXLoad)) { 800fa487e83a83c260d6a50f3df00a0eb012553a912Richard Sandiford return BuildMI(MF, MI->getDebugLoc(), get(SystemZ::MVC)) 801fa487e83a83c260d6a50f3df00a0eb012553a912Richard Sandiford .addFrameIndex(FrameIndex).addImm(0).addImm(Size) 802fa487e83a83c260d6a50f3df00a0eb012553a912Richard Sandiford .addOperand(MI->getOperand(1)).addImm(MI->getOperand(2).getImm()) 803fa487e83a83c260d6a50f3df00a0eb012553a912Richard Sandiford .addMemOperand(MMO); 804fa487e83a83c260d6a50f3df00a0eb012553a912Richard Sandiford } 805fa487e83a83c260d6a50f3df00a0eb012553a912Richard Sandiford // Handle conversion of stores. 806fa487e83a83c260d6a50f3df00a0eb012553a912Richard Sandiford if (isSimpleBD12Move(MI, SystemZII::SimpleBDXStore)) { 8071ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford return BuildMI(MF, MI->getDebugLoc(), get(SystemZ::MVC)) 8081ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford .addOperand(MI->getOperand(1)).addImm(MI->getOperand(2).getImm()) 8091ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford .addImm(Size).addFrameIndex(FrameIndex).addImm(0) 8101ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford .addMemOperand(MMO); 8111ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford } 8121ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford } 8131ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford } 8141ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford 8151ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford // If the spilled operand is the final one, try to change <INSN>R 8161ce4894a3f1ce6e63c1b109c24235d81dea2908fRichard Sandiford // into <INSN>. 8171d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand int MemOpcode = SystemZ::getMemOpcode(Opcode); 8181d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand if (MemOpcode >= 0) { 8191d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand unsigned NumOps = MI->getNumExplicitOperands(); 8201d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand if (OpNum == NumOps - 1) { 8211d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand const MCInstrDesc &MemDesc = get(MemOpcode); 8221d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand uint64_t AccessBytes = SystemZII::getAccessSize(MemDesc.TSFlags); 8231d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand assert(AccessBytes != 0 && "Size of access should be known"); 8241d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand assert(AccessBytes <= Size && "Access outside the frame index"); 8251d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand uint64_t Offset = Size - AccessBytes; 8261d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(MemOpcode)); 8271d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand for (unsigned I = 0; I < OpNum; ++I) 8281d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand MIB.addOperand(MI->getOperand(I)); 8291d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand MIB.addFrameIndex(FrameIndex).addImm(Offset); 8301d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand if (MemDesc.TSFlags & SystemZII::HasIndex) 8311d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand MIB.addReg(0); 8321d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return MIB; 8331d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand } 8341d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand } 8351d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 836ced450f0e6266eb8c2624fc1895cbc2749d715c3Richard Sandiford return 0; 837ced450f0e6266eb8c2624fc1895cbc2749d715c3Richard Sandiford} 838ced450f0e6266eb8c2624fc1895cbc2749d715c3Richard Sandiford 839ced450f0e6266eb8c2624fc1895cbc2749d715c3Richard SandifordMachineInstr * 840ced450f0e6266eb8c2624fc1895cbc2749d715c3Richard SandifordSystemZInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI, 841ced450f0e6266eb8c2624fc1895cbc2749d715c3Richard Sandiford const SmallVectorImpl<unsigned> &Ops, 842ced450f0e6266eb8c2624fc1895cbc2749d715c3Richard Sandiford MachineInstr* LoadMI) const { 843ced450f0e6266eb8c2624fc1895cbc2749d715c3Richard Sandiford return 0; 84479e2ed4d838354d8aeaadbbfe0a3779d63e72b25Richard Sandiford} 84579e2ed4d838354d8aeaadbbfe0a3779d63e72b25Richard Sandiford 84679e2ed4d838354d8aeaadbbfe0a3779d63e72b25Richard Sandifordbool 84779e2ed4d838354d8aeaadbbfe0a3779d63e72b25Richard SandifordSystemZInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { 84879e2ed4d838354d8aeaadbbfe0a3779d63e72b25Richard Sandiford switch (MI->getOpcode()) { 84979e2ed4d838354d8aeaadbbfe0a3779d63e72b25Richard Sandiford case SystemZ::L128: 85079e2ed4d838354d8aeaadbbfe0a3779d63e72b25Richard Sandiford splitMove(MI, SystemZ::LG); 85179e2ed4d838354d8aeaadbbfe0a3779d63e72b25Richard Sandiford return true; 8529a05f040e70494ab0092faa9ed10dc70ff1f4e66Richard Sandiford 8539a05f040e70494ab0092faa9ed10dc70ff1f4e66Richard Sandiford case SystemZ::ST128: 8549a05f040e70494ab0092faa9ed10dc70ff1f4e66Richard Sandiford splitMove(MI, SystemZ::STG); 8559a05f040e70494ab0092faa9ed10dc70ff1f4e66Richard Sandiford return true; 8569a05f040e70494ab0092faa9ed10dc70ff1f4e66Richard Sandiford 8579a05f040e70494ab0092faa9ed10dc70ff1f4e66Richard Sandiford case SystemZ::LX: 8589a05f040e70494ab0092faa9ed10dc70ff1f4e66Richard Sandiford splitMove(MI, SystemZ::LD); 8599a05f040e70494ab0092faa9ed10dc70ff1f4e66Richard Sandiford return true; 86055d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford 86155d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford case SystemZ::STX: 86255d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford splitMove(MI, SystemZ::STD); 86355d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford return true; 8649813dbf396e63f6d4fd99fe0f6651e831cb7414bRichard Sandiford 8659813dbf396e63f6d4fd99fe0f6651e831cb7414bRichard Sandiford case SystemZ::LBMux: 8669813dbf396e63f6d4fd99fe0f6651e831cb7414bRichard Sandiford expandRXYPseudo(MI, SystemZ::LB, SystemZ::LBH); 8679813dbf396e63f6d4fd99fe0f6651e831cb7414bRichard Sandiford return true; 8689813dbf396e63f6d4fd99fe0f6651e831cb7414bRichard Sandiford 8699813dbf396e63f6d4fd99fe0f6651e831cb7414bRichard Sandiford case SystemZ::LHMux: 8709813dbf396e63f6d4fd99fe0f6651e831cb7414bRichard Sandiford expandRXYPseudo(MI, SystemZ::LH, SystemZ::LHH); 8719813dbf396e63f6d4fd99fe0f6651e831cb7414bRichard Sandiford return true; 87255d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford 87355d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford case SystemZ::LLCRMux: 87455d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford expandZExtPseudo(MI, SystemZ::LLCR, 8); 87555d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford return true; 8764c8feae136bbb54ba09d8f8dc7e61714270f7cd5Richard Sandiford 8774c8feae136bbb54ba09d8f8dc7e61714270f7cd5Richard Sandiford case SystemZ::LLHRMux: 8784c8feae136bbb54ba09d8f8dc7e61714270f7cd5Richard Sandiford expandZExtPseudo(MI, SystemZ::LLHR, 16); 8794c8feae136bbb54ba09d8f8dc7e61714270f7cd5Richard Sandiford return true; 8804c8feae136bbb54ba09d8f8dc7e61714270f7cd5Richard Sandiford 8814c8feae136bbb54ba09d8f8dc7e61714270f7cd5Richard Sandiford case SystemZ::LLCMux: 8824c8feae136bbb54ba09d8f8dc7e61714270f7cd5Richard Sandiford expandRXYPseudo(MI, SystemZ::LLC, SystemZ::LLCH); 8834c8feae136bbb54ba09d8f8dc7e61714270f7cd5Richard Sandiford return true; 8841d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 8851d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand case SystemZ::LLHMux: 8861d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand expandRXYPseudo(MI, SystemZ::LLH, SystemZ::LLHH); 8871d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return true; 8881d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 8891d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand case SystemZ::LMux: 8901d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand expandRXYPseudo(MI, SystemZ::L, SystemZ::LFH); 8911d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return true; 8921d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 89344b486ed78c60b50aa14d4eed92ee828d4d44293Richard Sandiford case SystemZ::STCMux: 89444b486ed78c60b50aa14d4eed92ee828d4d44293Richard Sandiford expandRXYPseudo(MI, SystemZ::STC, SystemZ::STCH); 89544b486ed78c60b50aa14d4eed92ee828d4d44293Richard Sandiford return true; 89644b486ed78c60b50aa14d4eed92ee828d4d44293Richard Sandiford 89744b486ed78c60b50aa14d4eed92ee828d4d44293Richard Sandiford case SystemZ::STHMux: 89844b486ed78c60b50aa14d4eed92ee828d4d44293Richard Sandiford expandRXYPseudo(MI, SystemZ::STH, SystemZ::STHH); 89944b486ed78c60b50aa14d4eed92ee828d4d44293Richard Sandiford return true; 90044b486ed78c60b50aa14d4eed92ee828d4d44293Richard Sandiford 90144b486ed78c60b50aa14d4eed92ee828d4d44293Richard Sandiford case SystemZ::STMux: 90206c3c9a9e1cc313d911e939e3e994feaf43cc3a7Richard Sandiford expandRXYPseudo(MI, SystemZ::ST, SystemZ::STFH); 90306c3c9a9e1cc313d911e939e3e994feaf43cc3a7Richard Sandiford return true; 9041d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 9051d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand case SystemZ::LHIMux: 9061d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand expandRIPseudo(MI, SystemZ::LHI, SystemZ::IIHF, true); 9071d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return true; 908d50bcb2162a529534da42748ab4a418bfc9aaf06Richard Sandiford 9096824f127f90197b26af93cf5d6c13b7941567e54Richard Sandiford case SystemZ::IIFMux: 9101d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand expandRIPseudo(MI, SystemZ::IILF, SystemZ::IIHF, false); 9111d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return true; 9121d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 913d50bcb2162a529534da42748ab4a418bfc9aaf06Richard Sandiford case SystemZ::IILMux: 9146824f127f90197b26af93cf5d6c13b7941567e54Richard Sandiford expandRIPseudo(MI, SystemZ::IILL, SystemZ::IIHL, false); 9156824f127f90197b26af93cf5d6c13b7941567e54Richard Sandiford return true; 916d50bcb2162a529534da42748ab4a418bfc9aaf06Richard Sandiford 91793795574785de252703591e7fcc8f052c762f25eRichard Sandiford case SystemZ::IIHMux: 91893795574785de252703591e7fcc8f052c762f25eRichard Sandiford expandRIPseudo(MI, SystemZ::IILH, SystemZ::IIHH, false); 91993795574785de252703591e7fcc8f052c762f25eRichard Sandiford return true; 92093795574785de252703591e7fcc8f052c762f25eRichard Sandiford 92193795574785de252703591e7fcc8f052c762f25eRichard Sandiford case SystemZ::NIFMux: 92293795574785de252703591e7fcc8f052c762f25eRichard Sandiford expandRIPseudo(MI, SystemZ::NILF, SystemZ::NIHF, false); 92393795574785de252703591e7fcc8f052c762f25eRichard Sandiford return true; 92493795574785de252703591e7fcc8f052c762f25eRichard Sandiford 9252d664abbfca8b9fa3d99e8a2f74bd52faf007f12Richard Sandiford case SystemZ::NILMux: 926d50bcb2162a529534da42748ab4a418bfc9aaf06Richard Sandiford expandRIPseudo(MI, SystemZ::NILL, SystemZ::NIHL, false); 9276824f127f90197b26af93cf5d6c13b7941567e54Richard Sandiford return true; 9286824f127f90197b26af93cf5d6c13b7941567e54Richard Sandiford 929d50bcb2162a529534da42748ab4a418bfc9aaf06Richard Sandiford case SystemZ::NIHMux: 930e2d6f91d63a2e8cf77b07794cda7d9ef72504769Richard Sandiford expandRIPseudo(MI, SystemZ::NILH, SystemZ::NIHH, false); 931e2d6f91d63a2e8cf77b07794cda7d9ef72504769Richard Sandiford return true; 932e2d6f91d63a2e8cf77b07794cda7d9ef72504769Richard Sandiford 933e2d6f91d63a2e8cf77b07794cda7d9ef72504769Richard Sandiford case SystemZ::OIFMux: 934e2d6f91d63a2e8cf77b07794cda7d9ef72504769Richard Sandiford expandRIPseudo(MI, SystemZ::OILF, SystemZ::OIHF, false); 9352d664abbfca8b9fa3d99e8a2f74bd52faf007f12Richard Sandiford return true; 936d50bcb2162a529534da42748ab4a418bfc9aaf06Richard Sandiford 9376824f127f90197b26af93cf5d6c13b7941567e54Richard Sandiford case SystemZ::OILMux: 9386824f127f90197b26af93cf5d6c13b7941567e54Richard Sandiford expandRIPseudo(MI, SystemZ::OILL, SystemZ::OIHL, false); 9391d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return true; 940e2d6f91d63a2e8cf77b07794cda7d9ef72504769Richard Sandiford 941e2d6f91d63a2e8cf77b07794cda7d9ef72504769Richard Sandiford case SystemZ::OIHMux: 942e2d6f91d63a2e8cf77b07794cda7d9ef72504769Richard Sandiford expandRIPseudo(MI, SystemZ::OILH, SystemZ::OIHH, false); 943e2d6f91d63a2e8cf77b07794cda7d9ef72504769Richard Sandiford return true; 944e2d6f91d63a2e8cf77b07794cda7d9ef72504769Richard Sandiford 9451d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand case SystemZ::XIFMux: 94606c3c9a9e1cc313d911e939e3e994feaf43cc3a7Richard Sandiford expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF, false); 9471d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return true; 9481d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 9491d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand case SystemZ::TMLMux: 9501d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand expandRIPseudo(MI, SystemZ::TMLL, SystemZ::TMHL, false); 9511d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return true; 9521d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 9531d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand case SystemZ::TMHMux: 9541d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand expandRIPseudo(MI, SystemZ::TMLH, SystemZ::TMHH, false); 955e39a156b921f47a374f091b43205555ee90cd555Richard Sandiford return true; 95655d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford 95755d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford case SystemZ::AHIMux: 95855d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford expandRIPseudo(MI, SystemZ::AHI, SystemZ::AIH, false); 95955d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford return true; 96055d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford 96155d7d83b6c9e55fa73d667660c8e90f92999385bRichard Sandiford case SystemZ::AHIMuxK: 9621d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand expandRIEPseudo(MI, SystemZ::AHI, SystemZ::AHIK, SystemZ::AIH); 9631d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return true; 9641d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 9651d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand case SystemZ::AFIMux: 9661d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand expandRIPseudo(MI, SystemZ::AFI, SystemZ::AIH, false); 9671d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return true; 9681d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 9691d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand case SystemZ::CFIMux: 9701d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand expandRIPseudo(MI, SystemZ::CFI, SystemZ::CIH, false); 9711d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return true; 9721d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 9731d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand case SystemZ::CLFIMux: 9741d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand expandRIPseudo(MI, SystemZ::CLFI, SystemZ::CLIH, false); 9751d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return true; 9761d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 9771d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand case SystemZ::RISBMux: { 9781d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand bool DestIsHigh = isHighReg(MI->getOperand(0).getReg()); 9791d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand bool SrcIsHigh = isHighReg(MI->getOperand(2).getReg()); 9801d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand if (SrcIsHigh == DestIsHigh) 9811d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand MI->setDesc(get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL)); 9821d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand else { 9831d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand MI->setDesc(get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH)); 9841d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand MI->getOperand(5).setImm(MI->getOperand(5).getImm() ^ 32); 9851d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand } 9861d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return true; 9871d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand } 9881d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 9891d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand case SystemZ::ADJDYNALLOC: 9901d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand splitAdjDynAlloc(MI); 9911d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return true; 9921d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 9931d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand default: 9941d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return false; 9951d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand } 9961d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand} 9971d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 9981d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weiganduint64_t SystemZInstrInfo::getInstSizeInBytes(const MachineInstr *MI) const { 9991d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand if (MI->getOpcode() == TargetOpcode::INLINEASM) { 10001d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand const MachineFunction *MF = MI->getParent()->getParent(); 10011d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand const char *AsmStr = MI->getOperand(0).getSymbolName(); 10021d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo()); 10031d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand } 10041d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return MI->getDesc().getSize(); 10051d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand} 10061d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 10071d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich WeigandSystemZII::Branch 10081d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich WeigandSystemZInstrInfo::getBranchInfo(const MachineInstr *MI) const { 10091d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand switch (MI->getOpcode()) { 10109b05c709c65ba05645853ca49bc2a1ea8b554f37Richard Sandiford case SystemZ::BR: 10119b05c709c65ba05645853ca49bc2a1ea8b554f37Richard Sandiford case SystemZ::J: 10129b05c709c65ba05645853ca49bc2a1ea8b554f37Richard Sandiford case SystemZ::JG: 10139b05c709c65ba05645853ca49bc2a1ea8b554f37Richard Sandiford return SystemZII::Branch(SystemZII::BranchNormal, SystemZ::CCMASK_ANY, 10149b05c709c65ba05645853ca49bc2a1ea8b554f37Richard Sandiford SystemZ::CCMASK_ANY, &MI->getOperand(0)); 10159b05c709c65ba05645853ca49bc2a1ea8b554f37Richard Sandiford 10169b05c709c65ba05645853ca49bc2a1ea8b554f37Richard Sandiford case SystemZ::BRC: 10179b05c709c65ba05645853ca49bc2a1ea8b554f37Richard Sandiford case SystemZ::BRCL: 10189b05c709c65ba05645853ca49bc2a1ea8b554f37Richard Sandiford return SystemZII::Branch(SystemZII::BranchNormal, 101929e873ddb6b21c4a934926a0cf7809e98ac1fff0Richard Sandiford MI->getOperand(0).getImm(), 102029e873ddb6b21c4a934926a0cf7809e98ac1fff0Richard Sandiford MI->getOperand(1).getImm(), &MI->getOperand(2)); 102129e873ddb6b21c4a934926a0cf7809e98ac1fff0Richard Sandiford 10229b05c709c65ba05645853ca49bc2a1ea8b554f37Richard Sandiford case SystemZ::BRCT: 10239b05c709c65ba05645853ca49bc2a1ea8b554f37Richard Sandiford return SystemZII::Branch(SystemZII::BranchCT, SystemZ::CCMASK_ICMP, 10249b05c709c65ba05645853ca49bc2a1ea8b554f37Richard Sandiford SystemZ::CCMASK_CMP_NE, &MI->getOperand(2)); 10259b05c709c65ba05645853ca49bc2a1ea8b554f37Richard Sandiford 1026b3f912b510f8040690864126351b7021980558bbRichard Sandiford case SystemZ::BRCTG: 1027b3f912b510f8040690864126351b7021980558bbRichard Sandiford return SystemZII::Branch(SystemZII::BranchCTG, SystemZ::CCMASK_ICMP, 1028b3f912b510f8040690864126351b7021980558bbRichard Sandiford SystemZ::CCMASK_CMP_NE, &MI->getOperand(2)); 1029b3f912b510f8040690864126351b7021980558bbRichard Sandiford 1030b3f912b510f8040690864126351b7021980558bbRichard Sandiford case SystemZ::CIJ: 1031b3f912b510f8040690864126351b7021980558bbRichard Sandiford case SystemZ::CRJ: 1032b3f912b510f8040690864126351b7021980558bbRichard Sandiford return SystemZII::Branch(SystemZII::BranchC, SystemZ::CCMASK_ICMP, 1033b3f912b510f8040690864126351b7021980558bbRichard Sandiford MI->getOperand(2).getImm(), &MI->getOperand(3)); 1034b3f912b510f8040690864126351b7021980558bbRichard Sandiford 1035b3f912b510f8040690864126351b7021980558bbRichard Sandiford case SystemZ::CLIJ: 1036b3f912b510f8040690864126351b7021980558bbRichard Sandiford case SystemZ::CLRJ: 1037b3f912b510f8040690864126351b7021980558bbRichard Sandiford return SystemZII::Branch(SystemZII::BranchCL, SystemZ::CCMASK_ICMP, 1038b3f912b510f8040690864126351b7021980558bbRichard Sandiford MI->getOperand(2).getImm(), &MI->getOperand(3)); 1039b3f912b510f8040690864126351b7021980558bbRichard Sandiford 1040b3f912b510f8040690864126351b7021980558bbRichard Sandiford case SystemZ::CGIJ: 1041b3f912b510f8040690864126351b7021980558bbRichard Sandiford case SystemZ::CGRJ: 1042b3f912b510f8040690864126351b7021980558bbRichard Sandiford return SystemZII::Branch(SystemZII::BranchCG, SystemZ::CCMASK_ICMP, 1043b3f912b510f8040690864126351b7021980558bbRichard Sandiford MI->getOperand(2).getImm(), &MI->getOperand(3)); 1044b3f912b510f8040690864126351b7021980558bbRichard Sandiford 1045b3f912b510f8040690864126351b7021980558bbRichard Sandiford case SystemZ::CLGIJ: 1046b3f912b510f8040690864126351b7021980558bbRichard Sandiford case SystemZ::CLGRJ: 1047b3f912b510f8040690864126351b7021980558bbRichard Sandiford return SystemZII::Branch(SystemZII::BranchCLG, SystemZ::CCMASK_ICMP, 1048b3f912b510f8040690864126351b7021980558bbRichard Sandiford MI->getOperand(2).getImm(), &MI->getOperand(3)); 1049b3f912b510f8040690864126351b7021980558bbRichard Sandiford 1050b3f912b510f8040690864126351b7021980558bbRichard Sandiford default: 1051b3f912b510f8040690864126351b7021980558bbRichard Sandiford llvm_unreachable("Unrecognized branch opcode"); 1052b3f912b510f8040690864126351b7021980558bbRichard Sandiford } 1053b3f912b510f8040690864126351b7021980558bbRichard Sandiford} 1054b3f912b510f8040690864126351b7021980558bbRichard Sandiford 1055b3f912b510f8040690864126351b7021980558bbRichard Sandifordvoid SystemZInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC, 1056b3f912b510f8040690864126351b7021980558bbRichard Sandiford unsigned &LoadOpcode, 1057b3f912b510f8040690864126351b7021980558bbRichard Sandiford unsigned &StoreOpcode) const { 1058b3f912b510f8040690864126351b7021980558bbRichard Sandiford if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) { 1059b3f912b510f8040690864126351b7021980558bbRichard Sandiford LoadOpcode = SystemZ::L; 1060b3f912b510f8040690864126351b7021980558bbRichard Sandiford StoreOpcode = SystemZ::ST; 1061b3f912b510f8040690864126351b7021980558bbRichard Sandiford } else if (RC == &SystemZ::GRH32BitRegClass) { 1062b3f912b510f8040690864126351b7021980558bbRichard Sandiford LoadOpcode = SystemZ::LFH; 1063b3f912b510f8040690864126351b7021980558bbRichard Sandiford StoreOpcode = SystemZ::STFH; 1064b3f912b510f8040690864126351b7021980558bbRichard Sandiford } else if (RC == &SystemZ::GRX32BitRegClass) { 1065b3f912b510f8040690864126351b7021980558bbRichard Sandiford LoadOpcode = SystemZ::LMux; 1066b3f912b510f8040690864126351b7021980558bbRichard Sandiford StoreOpcode = SystemZ::STMux; 1067b3f912b510f8040690864126351b7021980558bbRichard Sandiford } else if (RC == &SystemZ::GR64BitRegClass || 10682d664abbfca8b9fa3d99e8a2f74bd52faf007f12Richard Sandiford RC == &SystemZ::ADDR64BitRegClass) { 10692d664abbfca8b9fa3d99e8a2f74bd52faf007f12Richard Sandiford LoadOpcode = SystemZ::LG; 1070d50bcb2162a529534da42748ab4a418bfc9aaf06Richard Sandiford StoreOpcode = SystemZ::STG; 1071d50bcb2162a529534da42748ab4a418bfc9aaf06Richard Sandiford } else if (RC == &SystemZ::GR128BitRegClass || 1072d50bcb2162a529534da42748ab4a418bfc9aaf06Richard Sandiford RC == &SystemZ::ADDR128BitRegClass) { 1073d50bcb2162a529534da42748ab4a418bfc9aaf06Richard Sandiford LoadOpcode = SystemZ::L128; 1074d50bcb2162a529534da42748ab4a418bfc9aaf06Richard Sandiford StoreOpcode = SystemZ::ST128; 10752d664abbfca8b9fa3d99e8a2f74bd52faf007f12Richard Sandiford } else if (RC == &SystemZ::FP32BitRegClass) { 10762d664abbfca8b9fa3d99e8a2f74bd52faf007f12Richard Sandiford LoadOpcode = SystemZ::LE; 10772d664abbfca8b9fa3d99e8a2f74bd52faf007f12Richard Sandiford StoreOpcode = SystemZ::STE; 10782d664abbfca8b9fa3d99e8a2f74bd52faf007f12Richard Sandiford } else if (RC == &SystemZ::FP64BitRegClass) { 1079e2d6f91d63a2e8cf77b07794cda7d9ef72504769Richard Sandiford LoadOpcode = SystemZ::LD; 1080e2d6f91d63a2e8cf77b07794cda7d9ef72504769Richard Sandiford StoreOpcode = SystemZ::STD; 1081e2d6f91d63a2e8cf77b07794cda7d9ef72504769Richard Sandiford } else if (RC == &SystemZ::FP128BitRegClass) { 1082e2d6f91d63a2e8cf77b07794cda7d9ef72504769Richard Sandiford LoadOpcode = SystemZ::LX; 1083e2d6f91d63a2e8cf77b07794cda7d9ef72504769Richard Sandiford StoreOpcode = SystemZ::STX; 1084e2d6f91d63a2e8cf77b07794cda7d9ef72504769Richard Sandiford } else 1085e2d6f91d63a2e8cf77b07794cda7d9ef72504769Richard Sandiford llvm_unreachable("Unsupported regclass to load or store"); 1086e2d6f91d63a2e8cf77b07794cda7d9ef72504769Richard Sandiford} 1087d50bcb2162a529534da42748ab4a418bfc9aaf06Richard Sandiford 1088d50bcb2162a529534da42748ab4a418bfc9aaf06Richard Sandifordunsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode, 1089d50bcb2162a529534da42748ab4a418bfc9aaf06Richard Sandiford int64_t Offset) const { 1090d50bcb2162a529534da42748ab4a418bfc9aaf06Richard Sandiford const MCInstrDesc &MCID = get(Opcode); 1091d50bcb2162a529534da42748ab4a418bfc9aaf06Richard Sandiford int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset); 10921d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand if (isUInt<12>(Offset) && isUInt<12>(Offset2)) { 10931d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // Get the instruction to use for unsigned 12-bit displacements. 10941d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode); 10951d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand if (Disp12Opcode >= 0) 10961d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return Disp12Opcode; 10971d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 10981d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // All address-related instructions can use unsigned 12-bit 10991d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // displacements. 11001d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return Opcode; 11011d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand } 11021d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand if (isInt<20>(Offset) && isInt<20>(Offset2)) { 11031d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // Get the instruction to use for signed 20-bit displacements. 11041d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode); 11051d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand if (Disp20Opcode >= 0) 11061d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand return Disp20Opcode; 11071d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand 11081d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand // Check whether Opcode allows signed 20-bit displacements. 11091d09d56fe1e3f3faadd4bf4ccf3e585ddb3c3b07Ulrich Weigand if (MCID.TSFlags & SystemZII::Has20BitOffset) 1110 return Opcode; 1111 } 1112 return 0; 1113} 1114 1115unsigned SystemZInstrInfo::getLoadAndTest(unsigned Opcode) const { 1116 switch (Opcode) { 1117 case SystemZ::L: return SystemZ::LT; 1118 case SystemZ::LY: return SystemZ::LT; 1119 case SystemZ::LG: return SystemZ::LTG; 1120 case SystemZ::LGF: return SystemZ::LTGF; 1121 case SystemZ::LR: return SystemZ::LTR; 1122 case SystemZ::LGFR: return SystemZ::LTGFR; 1123 case SystemZ::LGR: return SystemZ::LTGR; 1124 case SystemZ::LER: return SystemZ::LTEBR; 1125 case SystemZ::LDR: return SystemZ::LTDBR; 1126 case SystemZ::LXR: return SystemZ::LTXBR; 1127 default: return 0; 1128 } 1129} 1130 1131// Return true if Mask matches the regexp 0*1+0*, given that zero masks 1132// have already been filtered out. Store the first set bit in LSB and 1133// the number of set bits in Length if so. 1134static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length) { 1135 unsigned First = findFirstSet(Mask); 1136 uint64_t Top = (Mask >> First) + 1; 1137 if ((Top & -Top) == Top) { 1138 LSB = First; 1139 Length = findFirstSet(Top); 1140 return true; 1141 } 1142 return false; 1143} 1144 1145bool SystemZInstrInfo::isRxSBGMask(uint64_t Mask, unsigned BitSize, 1146 unsigned &Start, unsigned &End) const { 1147 // Reject trivial all-zero masks. 1148 if (Mask == 0) 1149 return false; 1150 1151 // Handle the 1+0+ or 0+1+0* cases. Start then specifies the index of 1152 // the msb and End specifies the index of the lsb. 1153 unsigned LSB, Length; 1154 if (isStringOfOnes(Mask, LSB, Length)) { 1155 Start = 63 - (LSB + Length - 1); 1156 End = 63 - LSB; 1157 return true; 1158 } 1159 1160 // Handle the wrap-around 1+0+1+ cases. Start then specifies the msb 1161 // of the low 1s and End specifies the lsb of the high 1s. 1162 if (isStringOfOnes(Mask ^ allOnes(BitSize), LSB, Length)) { 1163 assert(LSB > 0 && "Bottom bit must be set"); 1164 assert(LSB + Length < BitSize && "Top bit must be set"); 1165 Start = 63 - (LSB - 1); 1166 End = 63 - (LSB + Length); 1167 return true; 1168 } 1169 1170 return false; 1171} 1172 1173unsigned SystemZInstrInfo::getCompareAndBranch(unsigned Opcode, 1174 const MachineInstr *MI) const { 1175 switch (Opcode) { 1176 case SystemZ::CR: 1177 return SystemZ::CRJ; 1178 case SystemZ::CGR: 1179 return SystemZ::CGRJ; 1180 case SystemZ::CHI: 1181 return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CIJ : 0; 1182 case SystemZ::CGHI: 1183 return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CGIJ : 0; 1184 case SystemZ::CLR: 1185 return SystemZ::CLRJ; 1186 case SystemZ::CLGR: 1187 return SystemZ::CLGRJ; 1188 case SystemZ::CLFI: 1189 return MI && isUInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CLIJ : 0; 1190 case SystemZ::CLGFI: 1191 return MI && isUInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CLGIJ : 0; 1192 default: 1193 return 0; 1194 } 1195} 1196 1197void SystemZInstrInfo::loadImmediate(MachineBasicBlock &MBB, 1198 MachineBasicBlock::iterator MBBI, 1199 unsigned Reg, uint64_t Value) const { 1200 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 1201 unsigned Opcode; 1202 if (isInt<16>(Value)) 1203 Opcode = SystemZ::LGHI; 1204 else if (SystemZ::isImmLL(Value)) 1205 Opcode = SystemZ::LLILL; 1206 else if (SystemZ::isImmLH(Value)) { 1207 Opcode = SystemZ::LLILH; 1208 Value >>= 16; 1209 } else { 1210 assert(isInt<32>(Value) && "Huge values not handled yet"); 1211 Opcode = SystemZ::LGFI; 1212 } 1213 BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value); 1214} 1215