SystemZInstrInfo.cpp revision 2457f2c66184e978d4ed8fa9e2128effff26cb0b 
1//===- SystemZInstrInfo.cpp - SystemZ Instruction Information --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SystemZ implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SystemZ.h"
15#include "SystemZInstrBuilder.h"
16#include "SystemZInstrInfo.h"
17#include "SystemZMachineFunctionInfo.h"
18#include "SystemZTargetMachine.h"
19#include "SystemZGenInstrInfo.inc"
20#include "llvm/Function.h"
21#include "llvm/CodeGen/MachineFrameInfo.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/CodeGen/PseudoSourceValue.h"
25#include "llvm/Support/ErrorHandling.h"
26using namespace llvm;
27
28SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm)
29  : TargetInstrInfoImpl(SystemZInsts, array_lengthof(SystemZInsts)),
30    RI(tm, *this), TM(tm) {
31  // Fill the spill offsets map
32  static const unsigned SpillOffsTab[][2] = {
33    { SystemZ::R2D,  0x10 },
34    { SystemZ::R3D,  0x18 },
35    { SystemZ::R4D,  0x20 },
36    { SystemZ::R5D,  0x28 },
37    { SystemZ::R6D,  0x30 },
38    { SystemZ::R7D,  0x38 },
39    { SystemZ::R8D,  0x40 },
40    { SystemZ::R9D,  0x48 },
41    { SystemZ::R10D, 0x50 },
42    { SystemZ::R11D, 0x58 },
43    { SystemZ::R12D, 0x60 },
44    { SystemZ::R13D, 0x68 },
45    { SystemZ::R14D, 0x70 },
46    { SystemZ::R15D, 0x78 }
47  };
48
49  RegSpillOffsets.grow(SystemZ::NUM_TARGET_REGS);
50
51  for (unsigned i = 0, e = array_lengthof(SpillOffsTab); i != e; ++i)
52    RegSpillOffsets[SpillOffsTab[i][0]] = SpillOffsTab[i][1];
53}
54
55/// isGVStub - Return true if the GV requires an extra load to get the
56/// real address.
57static inline bool isGVStub(GlobalValue *GV, SystemZTargetMachine &TM) {
58  return TM.getSubtarget<SystemZSubtarget>().GVRequiresExtraLoad(GV, TM, false);
59}
60
61void SystemZInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
62                                          MachineBasicBlock::iterator MI,
63                                    unsigned SrcReg, bool isKill, int FrameIdx,
64                                           const TargetRegisterClass *RC,
65                                           const TargetRegisterInfo *TRI) const {
66  DebugLoc DL;
67  if (MI != MBB.end()) DL = MI->getDebugLoc();
68
69  unsigned Opc = 0;
70  if (RC == &SystemZ::GR32RegClass ||
71      RC == &SystemZ::ADDR32RegClass)
72    Opc = SystemZ::MOV32mr;
73  else if (RC == &SystemZ::GR64RegClass ||
74           RC == &SystemZ::ADDR64RegClass) {
75    Opc = SystemZ::MOV64mr;
76  } else if (RC == &SystemZ::FP32RegClass) {
77    Opc = SystemZ::FMOV32mr;
78  } else if (RC == &SystemZ::FP64RegClass) {
79    Opc = SystemZ::FMOV64mr;
80  } else if (RC == &SystemZ::GR64PRegClass) {
81    Opc = SystemZ::MOV64Pmr;
82  } else if (RC == &SystemZ::GR128RegClass) {
83    Opc = SystemZ::MOV128mr;
84  } else
85    llvm_unreachable("Unsupported regclass to store");
86
87  addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
88    .addReg(SrcReg, getKillRegState(isKill));
89}
90
91void SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
92                                           MachineBasicBlock::iterator MI,
93                                           unsigned DestReg, int FrameIdx,
94                                            const TargetRegisterClass *RC,
95                                            const TargetRegisterInfo *TRI) const{
96  DebugLoc DL;
97  if (MI != MBB.end()) DL = MI->getDebugLoc();
98
99  unsigned Opc = 0;
100  if (RC == &SystemZ::GR32RegClass ||
101      RC == &SystemZ::ADDR32RegClass)
102    Opc = SystemZ::MOV32rm;
103  else if (RC == &SystemZ::GR64RegClass ||
104           RC == &SystemZ::ADDR64RegClass) {
105    Opc = SystemZ::MOV64rm;
106  } else if (RC == &SystemZ::FP32RegClass) {
107    Opc = SystemZ::FMOV32rm;
108  } else if (RC == &SystemZ::FP64RegClass) {
109    Opc = SystemZ::FMOV64rm;
110  } else if (RC == &SystemZ::GR64PRegClass) {
111    Opc = SystemZ::MOV64Prm;
112  } else if (RC == &SystemZ::GR128RegClass) {
113    Opc = SystemZ::MOV128rm;
114  } else
115    llvm_unreachable("Unsupported regclass to load");
116
117  addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
118}
119
120bool SystemZInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
121                                    MachineBasicBlock::iterator I,
122                                    unsigned DestReg, unsigned SrcReg,
123                                    const TargetRegisterClass *DestRC,
124                                    const TargetRegisterClass *SrcRC,
125                                    DebugLoc DL) const {
126
127  // Determine if DstRC and SrcRC have a common superclass.
128  const TargetRegisterClass *CommonRC = DestRC;
129  if (DestRC == SrcRC)
130    /* Same regclass for source and dest */;
131  else if (CommonRC->hasSuperClass(SrcRC))
132    CommonRC = SrcRC;
133  else if (!CommonRC->hasSubClass(SrcRC))
134    CommonRC = 0;
135
136  if (CommonRC) {
137    if (CommonRC == &SystemZ::GR64RegClass ||
138        CommonRC == &SystemZ::ADDR64RegClass) {
139      BuildMI(MBB, I, DL, get(SystemZ::MOV64rr), DestReg).addReg(SrcReg);
140    } else if (CommonRC == &SystemZ::GR32RegClass ||
141               CommonRC == &SystemZ::ADDR32RegClass) {
142      BuildMI(MBB, I, DL, get(SystemZ::MOV32rr), DestReg).addReg(SrcReg);
143    } else if (CommonRC == &SystemZ::GR64PRegClass) {
144      BuildMI(MBB, I, DL, get(SystemZ::MOV64rrP), DestReg).addReg(SrcReg);
145    } else if (CommonRC == &SystemZ::GR128RegClass) {
146      BuildMI(MBB, I, DL, get(SystemZ::MOV128rr), DestReg).addReg(SrcReg);
147    } else if (CommonRC == &SystemZ::FP32RegClass) {
148      BuildMI(MBB, I, DL, get(SystemZ::FMOV32rr), DestReg).addReg(SrcReg);
149    } else if (CommonRC == &SystemZ::FP64RegClass) {
150      BuildMI(MBB, I, DL, get(SystemZ::FMOV64rr), DestReg).addReg(SrcReg);
151    } else {
152      return false;
153    }
154
155    return true;
156  }
157
158  if ((SrcRC == &SystemZ::GR64RegClass &&
159       DestRC == &SystemZ::ADDR64RegClass) ||
160      (DestRC == &SystemZ::GR64RegClass &&
161       SrcRC == &SystemZ::ADDR64RegClass)) {
162    BuildMI(MBB, I, DL, get(SystemZ::MOV64rr), DestReg).addReg(SrcReg);
163    return true;
164  } else if ((SrcRC == &SystemZ::GR32RegClass &&
165              DestRC == &SystemZ::ADDR32RegClass) ||
166             (DestRC == &SystemZ::GR32RegClass &&
167              SrcRC == &SystemZ::ADDR32RegClass)) {
168    BuildMI(MBB, I, DL, get(SystemZ::MOV32rr), DestReg).addReg(SrcReg);
169    return true;
170  }
171
172  return false;
173}
174
175bool
176SystemZInstrInfo::isMoveInstr(const MachineInstr& MI,
177                              unsigned &SrcReg, unsigned &DstReg,
178                              unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
179  switch (MI.getOpcode()) {
180  default:
181    return false;
182  case SystemZ::MOV32rr:
183  case SystemZ::MOV64rr:
184  case SystemZ::MOV64rrP:
185  case SystemZ::MOV128rr:
186  case SystemZ::FMOV32rr:
187  case SystemZ::FMOV64rr:
188    assert(MI.getNumOperands() >= 2 &&
189           MI.getOperand(0).isReg() &&
190           MI.getOperand(1).isReg() &&
191           "invalid register-register move instruction");
192    SrcReg = MI.getOperand(1).getReg();
193    DstReg = MI.getOperand(0).getReg();
194    SrcSubIdx = MI.getOperand(1).getSubReg();
195    DstSubIdx = MI.getOperand(0).getSubReg();
196    return true;
197  }
198}
199
200unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
201                                               int &FrameIndex) const {
202  switch (MI->getOpcode()) {
203  default: break;
204  case SystemZ::MOV32rm:
205  case SystemZ::MOV32rmy:
206  case SystemZ::MOV64rm:
207  case SystemZ::MOVSX32rm8:
208  case SystemZ::MOVSX32rm16y:
209  case SystemZ::MOVSX64rm8:
210  case SystemZ::MOVSX64rm16:
211  case SystemZ::MOVSX64rm32:
212  case SystemZ::MOVZX32rm8:
213  case SystemZ::MOVZX32rm16:
214  case SystemZ::MOVZX64rm8:
215  case SystemZ::MOVZX64rm16:
216  case SystemZ::MOVZX64rm32:
217  case SystemZ::FMOV32rm:
218  case SystemZ::FMOV32rmy:
219  case SystemZ::FMOV64rm:
220  case SystemZ::FMOV64rmy:
221  case SystemZ::MOV64Prm:
222  case SystemZ::MOV64Prmy:
223  case SystemZ::MOV128rm:
224    if (MI->getOperand(1).isFI() &&
225        MI->getOperand(2).isImm() && MI->getOperand(3).isReg() &&
226        MI->getOperand(2).getImm() == 0 && MI->getOperand(3).getReg() == 0) {
227      FrameIndex = MI->getOperand(1).getIndex();
228      return MI->getOperand(0).getReg();
229    }
230    break;
231  }
232  return 0;
233}
234
235unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
236                                              int &FrameIndex) const {
237  switch (MI->getOpcode()) {
238  default: break;
239  case SystemZ::MOV32mr:
240  case SystemZ::MOV32mry:
241  case SystemZ::MOV64mr:
242  case SystemZ::MOV32m8r:
243  case SystemZ::MOV32m8ry:
244  case SystemZ::MOV32m16r:
245  case SystemZ::MOV32m16ry:
246  case SystemZ::MOV64m8r:
247  case SystemZ::MOV64m8ry:
248  case SystemZ::MOV64m16r:
249  case SystemZ::MOV64m16ry:
250  case SystemZ::MOV64m32r:
251  case SystemZ::MOV64m32ry:
252  case SystemZ::FMOV32mr:
253  case SystemZ::FMOV32mry:
254  case SystemZ::FMOV64mr:
255  case SystemZ::FMOV64mry:
256  case SystemZ::MOV64Pmr:
257  case SystemZ::MOV64Pmry:
258  case SystemZ::MOV128mr:
259    if (MI->getOperand(0).isFI() &&
260        MI->getOperand(1).isImm() && MI->getOperand(2).isReg() &&
261        MI->getOperand(1).getImm() == 0 && MI->getOperand(2).getReg() == 0) {
262      FrameIndex = MI->getOperand(0).getIndex();
263      return MI->getOperand(3).getReg();
264    }
265    break;
266  }
267  return 0;
268}
269
270bool
271SystemZInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
272                                           MachineBasicBlock::iterator MI,
273                                        const std::vector<CalleeSavedInfo> &CSI,
274                                          const TargetRegisterInfo *TRI) const {
275  if (CSI.empty())
276    return false;
277
278  DebugLoc DL;
279  if (MI != MBB.end()) DL = MI->getDebugLoc();
280
281  MachineFunction &MF = *MBB.getParent();
282  SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>();
283  unsigned CalleeFrameSize = 0;
284
285  // Scan the callee-saved and find the bounds of register spill area.
286  unsigned LowReg = 0, HighReg = 0, StartOffset = -1U, EndOffset = 0;
287  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
288    unsigned Reg = CSI[i].getReg();
289    const TargetRegisterClass *RegClass = CSI[i].getRegClass();
290    if (RegClass != &SystemZ::FP64RegClass) {
291      unsigned Offset = RegSpillOffsets[Reg];
292      CalleeFrameSize += 8;
293      if (StartOffset > Offset) {
294        LowReg = Reg; StartOffset = Offset;
295      }
296      if (EndOffset < Offset) {
297        HighReg = Reg; EndOffset = RegSpillOffsets[Reg];
298      }
299    }
300  }
301
302  // Save information for epilogue inserter.
303  MFI->setCalleeSavedFrameSize(CalleeFrameSize);
304  MFI->setLowReg(LowReg); MFI->setHighReg(HighReg);
305
306  // Save GPRs
307  if (StartOffset) {
308    // Build a store instruction. Use STORE MULTIPLE instruction if there are many
309    // registers to store, otherwise - just STORE.
310    MachineInstrBuilder MIB =
311      BuildMI(MBB, MI, DL, get((LowReg == HighReg ?
312                                SystemZ::MOV64mr : SystemZ::MOV64mrm)));
313
314    // Add store operands.
315    MIB.addReg(SystemZ::R15D).addImm(StartOffset);
316    if (LowReg == HighReg)
317      MIB.addReg(0);
318    MIB.addReg(LowReg, RegState::Kill);
319    if (LowReg != HighReg)
320      MIB.addReg(HighReg, RegState::Kill);
321
322    // Do a second scan adding regs as being killed by instruction
323    for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
324      unsigned Reg = CSI[i].getReg();
325      // Add the callee-saved register as live-in. It's killed at the spill.
326      MBB.addLiveIn(Reg);
327      if (Reg != LowReg && Reg != HighReg)
328        MIB.addReg(Reg, RegState::ImplicitKill);
329    }
330  }
331
332  // Save FPRs
333  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
334    unsigned Reg = CSI[i].getReg();
335    const TargetRegisterClass *RegClass = CSI[i].getRegClass();
336    if (RegClass == &SystemZ::FP64RegClass) {
337      MBB.addLiveIn(Reg);
338      storeRegToStackSlot(MBB, MI, Reg, true, CSI[i].getFrameIdx(), RegClass,
339                          &RI);
340    }
341  }
342
343  return true;
344}
345
346bool
347SystemZInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
348                                             MachineBasicBlock::iterator MI,
349                                        const std::vector<CalleeSavedInfo> &CSI,
350                                          const TargetRegisterInfo *TRI) const {
351  if (CSI.empty())
352    return false;
353
354  DebugLoc DL;
355  if (MI != MBB.end()) DL = MI->getDebugLoc();
356
357  MachineFunction &MF = *MBB.getParent();
358  const TargetRegisterInfo *RegInfo= MF.getTarget().getRegisterInfo();
359  SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>();
360
361  // Restore FP registers
362  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
363    unsigned Reg = CSI[i].getReg();
364    const TargetRegisterClass *RegClass = CSI[i].getRegClass();
365    if (RegClass == &SystemZ::FP64RegClass)
366      loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass, &RI);
367  }
368
369  // Restore GP registers
370  unsigned LowReg = MFI->getLowReg(), HighReg = MFI->getHighReg();
371  unsigned StartOffset = RegSpillOffsets[LowReg];
372
373  if (StartOffset) {
374    // Build a load instruction. Use LOAD MULTIPLE instruction if there are many
375    // registers to load, otherwise - just LOAD.
376    MachineInstrBuilder MIB =
377      BuildMI(MBB, MI, DL, get((LowReg == HighReg ?
378                                SystemZ::MOV64rm : SystemZ::MOV64rmm)));
379    // Add store operands.
380    MIB.addReg(LowReg, RegState::Define);
381    if (LowReg != HighReg)
382      MIB.addReg(HighReg, RegState::Define);
383
384    MIB.addReg((RegInfo->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D));
385    MIB.addImm(StartOffset);
386    if (LowReg == HighReg)
387      MIB.addReg(0);
388
389    // Do a second scan adding regs as being defined by instruction
390    for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
391      unsigned Reg = CSI[i].getReg();
392      if (Reg != LowReg && Reg != HighReg)
393        MIB.addReg(Reg, RegState::ImplicitDefine);
394    }
395  }
396
397  return true;
398}
399
400bool SystemZInstrInfo::
401ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
402  assert(Cond.size() == 1 && "Invalid Xbranch condition!");
403
404  SystemZCC::CondCodes CC = static_cast<SystemZCC::CondCodes>(Cond[0].getImm());
405  Cond[0].setImm(getOppositeCondition(CC));
406  return false;
407}
408
409bool SystemZInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
410  const TargetInstrDesc &TID = MI->getDesc();
411  if (!TID.isTerminator()) return false;
412
413  // Conditional branch is a special case.
414  if (TID.isBranch() && !TID.isBarrier())
415    return true;
416  if (!TID.isPredicable())
417    return true;
418  return !isPredicated(MI);
419}
420
421bool SystemZInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
422                                     MachineBasicBlock *&TBB,
423                                     MachineBasicBlock *&FBB,
424                                     SmallVectorImpl<MachineOperand> &Cond,
425                                     bool AllowModify) const {
426  // Start from the bottom of the block and work up, examining the
427  // terminator instructions.
428  MachineBasicBlock::iterator I = MBB.end();
429  while (I != MBB.begin()) {
430    --I;
431    if (I->isDebugValue())
432      continue;
433    // Working from the bottom, when we see a non-terminator
434    // instruction, we're done.
435    if (!isUnpredicatedTerminator(I))
436      break;
437
438    // A terminator that isn't a branch can't easily be handled
439    // by this analysis.
440    if (!I->getDesc().isBranch())
441      return true;
442
443    // Handle unconditional branches.
444    if (I->getOpcode() == SystemZ::JMP) {
445      if (!AllowModify) {
446        TBB = I->getOperand(0).getMBB();
447        continue;
448      }
449
450      // If the block has any instructions after a JMP, delete them.
451      while (llvm::next(I) != MBB.end())
452        llvm::next(I)->eraseFromParent();
453      Cond.clear();
454      FBB = 0;
455
456      // Delete the JMP if it's equivalent to a fall-through.
457      if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
458        TBB = 0;
459        I->eraseFromParent();
460        I = MBB.end();
461        continue;
462      }
463
464      // TBB is used to indicate the unconditinal destination.
465      TBB = I->getOperand(0).getMBB();
466      continue;
467    }
468
469    // Handle conditional branches.
470    SystemZCC::CondCodes BranchCode = getCondFromBranchOpc(I->getOpcode());
471    if (BranchCode == SystemZCC::INVALID)
472      return true;  // Can't handle indirect branch.
473
474    // Working from the bottom, handle the first conditional branch.
475    if (Cond.empty()) {
476      FBB = TBB;
477      TBB = I->getOperand(0).getMBB();
478      Cond.push_back(MachineOperand::CreateImm(BranchCode));
479      continue;
480    }
481
482    // Handle subsequent conditional branches. Only handle the case where all
483    // conditional branches branch to the same destination.
484    assert(Cond.size() == 1);
485    assert(TBB);
486
487    // Only handle the case where all conditional branches branch to
488    // the same destination.
489    if (TBB != I->getOperand(0).getMBB())
490      return true;
491
492    SystemZCC::CondCodes OldBranchCode = (SystemZCC::CondCodes)Cond[0].getImm();
493    // If the conditions are the same, we can leave them alone.
494    if (OldBranchCode == BranchCode)
495      continue;
496
497    return true;
498  }
499
500  return false;
501}
502
503unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
504  MachineBasicBlock::iterator I = MBB.end();
505  unsigned Count = 0;
506
507  while (I != MBB.begin()) {
508    --I;
509    if (I->isDebugValue())
510      continue;
511    if (I->getOpcode() != SystemZ::JMP &&
512        getCondFromBranchOpc(I->getOpcode()) == SystemZCC::INVALID)
513      break;
514    // Remove the branch.
515    I->eraseFromParent();
516    I = MBB.end();
517    ++Count;
518  }
519
520  return Count;
521}
522
523unsigned
524SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
525                               MachineBasicBlock *FBB,
526                            const SmallVectorImpl<MachineOperand> &Cond) const {
527  // FIXME: this should probably have a DebugLoc operand
528  DebugLoc DL;
529  // Shouldn't be a fall through.
530  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
531  assert((Cond.size() == 1 || Cond.size() == 0) &&
532         "SystemZ branch conditions have one component!");
533
534  if (Cond.empty()) {
535    // Unconditional branch?
536    assert(!FBB && "Unconditional branch with multiple successors!");
537    BuildMI(&MBB, DL, get(SystemZ::JMP)).addMBB(TBB);
538    return 1;
539  }
540
541  // Conditional branch.
542  unsigned Count = 0;
543  SystemZCC::CondCodes CC = (SystemZCC::CondCodes)Cond[0].getImm();
544  BuildMI(&MBB, DL, getBrCond(CC)).addMBB(TBB);
545  ++Count;
546
547  if (FBB) {
548    // Two-way Conditional branch. Insert the second branch.
549    BuildMI(&MBB, DL, get(SystemZ::JMP)).addMBB(FBB);
550    ++Count;
551  }
552  return Count;
553}
554
555const TargetInstrDesc&
556SystemZInstrInfo::getBrCond(SystemZCC::CondCodes CC) const {
557  switch (CC) {
558  default:
559   llvm_unreachable("Unknown condition code!");
560  case SystemZCC::O:   return get(SystemZ::JO);
561  case SystemZCC::H:   return get(SystemZ::JH);
562  case SystemZCC::NLE: return get(SystemZ::JNLE);
563  case SystemZCC::L:   return get(SystemZ::JL);
564  case SystemZCC::NHE: return get(SystemZ::JNHE);
565  case SystemZCC::LH:  return get(SystemZ::JLH);
566  case SystemZCC::NE:  return get(SystemZ::JNE);
567  case SystemZCC::E:   return get(SystemZ::JE);
568  case SystemZCC::NLH: return get(SystemZ::JNLH);
569  case SystemZCC::HE:  return get(SystemZ::JHE);
570  case SystemZCC::NL:  return get(SystemZ::JNL);
571  case SystemZCC::LE:  return get(SystemZ::JLE);
572  case SystemZCC::NH:  return get(SystemZ::JNH);
573  case SystemZCC::NO:  return get(SystemZ::JNO);
574  }
575}
576
577SystemZCC::CondCodes
578SystemZInstrInfo::getCondFromBranchOpc(unsigned Opc) const {
579  switch (Opc) {
580  default:            return SystemZCC::INVALID;
581  case SystemZ::JO:   return SystemZCC::O;
582  case SystemZ::JH:   return SystemZCC::H;
583  case SystemZ::JNLE: return SystemZCC::NLE;
584  case SystemZ::JL:   return SystemZCC::L;
585  case SystemZ::JNHE: return SystemZCC::NHE;
586  case SystemZ::JLH:  return SystemZCC::LH;
587  case SystemZ::JNE:  return SystemZCC::NE;
588  case SystemZ::JE:   return SystemZCC::E;
589  case SystemZ::JNLH: return SystemZCC::NLH;
590  case SystemZ::JHE:  return SystemZCC::HE;
591  case SystemZ::JNL:  return SystemZCC::NL;
592  case SystemZ::JLE:  return SystemZCC::LE;
593  case SystemZ::JNH:  return SystemZCC::NH;
594  case SystemZ::JNO:  return SystemZCC::NO;
595  }
596}
597
598SystemZCC::CondCodes
599SystemZInstrInfo::getOppositeCondition(SystemZCC::CondCodes CC) const {
600  switch (CC) {
601  default:
602    llvm_unreachable("Invalid condition!");
603  case SystemZCC::O:   return SystemZCC::NO;
604  case SystemZCC::H:   return SystemZCC::NH;
605  case SystemZCC::NLE: return SystemZCC::LE;
606  case SystemZCC::L:   return SystemZCC::NL;
607  case SystemZCC::NHE: return SystemZCC::HE;
608  case SystemZCC::LH:  return SystemZCC::NLH;
609  case SystemZCC::NE:  return SystemZCC::E;
610  case SystemZCC::E:   return SystemZCC::NE;
611  case SystemZCC::NLH: return SystemZCC::LH;
612  case SystemZCC::HE:  return SystemZCC::NHE;
613  case SystemZCC::NL:  return SystemZCC::L;
614  case SystemZCC::LE:  return SystemZCC::NLE;
615  case SystemZCC::NH:  return SystemZCC::H;
616  case SystemZCC::NO:  return SystemZCC::O;
617  }
618}
619
620const TargetInstrDesc&
621SystemZInstrInfo::getLongDispOpc(unsigned Opc) const {
622  switch (Opc) {
623  default:
624    llvm_unreachable("Don't have long disp version of this instruction");
625  case SystemZ::MOV32mr:   return get(SystemZ::MOV32mry);
626  case SystemZ::MOV32rm:   return get(SystemZ::MOV32rmy);
627  case SystemZ::MOVSX32rm16: return get(SystemZ::MOVSX32rm16y);
628  case SystemZ::MOV32m8r:  return get(SystemZ::MOV32m8ry);
629  case SystemZ::MOV32m16r: return get(SystemZ::MOV32m16ry);
630  case SystemZ::MOV64m8r:  return get(SystemZ::MOV64m8ry);
631  case SystemZ::MOV64m16r: return get(SystemZ::MOV64m16ry);
632  case SystemZ::MOV64m32r: return get(SystemZ::MOV64m32ry);
633  case SystemZ::MOV8mi:    return get(SystemZ::MOV8miy);
634  case SystemZ::MUL32rm:   return get(SystemZ::MUL32rmy);
635  case SystemZ::CMP32rm:   return get(SystemZ::CMP32rmy);
636  case SystemZ::UCMP32rm:  return get(SystemZ::UCMP32rmy);
637  case SystemZ::FMOV32mr:  return get(SystemZ::FMOV32mry);
638  case SystemZ::FMOV64mr:  return get(SystemZ::FMOV64mry);
639  case SystemZ::FMOV32rm:  return get(SystemZ::FMOV32rmy);
640  case SystemZ::FMOV64rm:  return get(SystemZ::FMOV64rmy);
641  case SystemZ::MOV64Pmr:  return get(SystemZ::MOV64Pmry);
642  case SystemZ::MOV64Prm:  return get(SystemZ::MOV64Prmy);
643  }
644}
645