SystemZInstrInfo.cpp revision 645d250b84fe0d097e7813b980ae58daeca2c2e6 
1//===-- SystemZInstrInfo.cpp - SystemZ instruction information ------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SystemZ implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SystemZInstrInfo.h"
15#include "SystemZTargetMachine.h"
16#include "SystemZInstrBuilder.h"
17#include "llvm/CodeGen/LiveVariables.h"
18#include "llvm/CodeGen/MachineRegisterInfo.h"
19
20#define GET_INSTRINFO_CTOR
21#define GET_INSTRMAP_INFO
22#include "SystemZGenInstrInfo.inc"
23
24using namespace llvm;
25
26// Return a mask with Count low bits set.
27static uint64_t allOnes(unsigned int Count) {
28  return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
29}
30
31// Reg should be a 32-bit GPR.  Return true if it is a high register rather
32// than a low register.
33static bool isHighReg(unsigned int Reg) {
34  if (SystemZ::GRH32BitRegClass.contains(Reg))
35    return true;
36  assert(SystemZ::GR32BitRegClass.contains(Reg) && "Invalid GRX32");
37  return false;
38}
39
40SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm)
41  : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
42    RI(tm), TM(tm) {
43}
44
45// MI is a 128-bit load or store.  Split it into two 64-bit loads or stores,
46// each having the opcode given by NewOpcode.
47void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
48                                 unsigned NewOpcode) const {
49  MachineBasicBlock *MBB = MI->getParent();
50  MachineFunction &MF = *MBB->getParent();
51
52  // Get two load or store instructions.  Use the original instruction for one
53  // of them (arbitarily the second here) and create a clone for the other.
54  MachineInstr *EarlierMI = MF.CloneMachineInstr(MI);
55  MBB->insert(MI, EarlierMI);
56
57  // Set up the two 64-bit registers.
58  MachineOperand &HighRegOp = EarlierMI->getOperand(0);
59  MachineOperand &LowRegOp = MI->getOperand(0);
60  HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
61  LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));
62
63  // The address in the first (high) instruction is already correct.
64  // Adjust the offset in the second (low) instruction.
65  MachineOperand &HighOffsetOp = EarlierMI->getOperand(2);
66  MachineOperand &LowOffsetOp = MI->getOperand(2);
67  LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);
68
69  // Set the opcodes.
70  unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
71  unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
72  assert(HighOpcode && LowOpcode && "Both offsets should be in range");
73
74  EarlierMI->setDesc(get(HighOpcode));
75  MI->setDesc(get(LowOpcode));
76}
77
78// Split ADJDYNALLOC instruction MI.
79void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const {
80  MachineBasicBlock *MBB = MI->getParent();
81  MachineFunction &MF = *MBB->getParent();
82  MachineFrameInfo *MFFrame = MF.getFrameInfo();
83  MachineOperand &OffsetMO = MI->getOperand(2);
84
85  uint64_t Offset = (MFFrame->getMaxCallFrameSize() +
86                     SystemZMC::CallFrameSize +
87                     OffsetMO.getImm());
88  unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset);
89  assert(NewOpcode && "No support for huge argument lists yet");
90  MI->setDesc(get(NewOpcode));
91  OffsetMO.setImm(Offset);
92}
93
94// MI is an RI-style pseudo instruction.  Replace it with LowOpcode
95// if the first operand is a low GR32 and HighOpcode if the first operand
96// is a high GR32.  ConvertHigh is true if LowOpcode takes a signed operand
97// and HighOpcode takes an unsigned 32-bit operand.  In those cases,
98// MI has the same kind of operand as LowOpcode, so needs to be converted
99// if HighOpcode is used.
100void SystemZInstrInfo::expandRIPseudo(MachineInstr *MI, unsigned LowOpcode,
101                                      unsigned HighOpcode,
102                                      bool ConvertHigh) const {
103  unsigned Reg = MI->getOperand(0).getReg();
104  bool IsHigh = isHighReg(Reg);
105  MI->setDesc(get(IsHigh ? HighOpcode : LowOpcode));
106  if (IsHigh && ConvertHigh)
107    MI->getOperand(1).setImm(uint32_t(MI->getOperand(1).getImm()));
108}
109
110// MI is an RXY-style pseudo instruction.  Replace it with LowOpcode
111// if the first operand is a low GR32 and HighOpcode if the first operand
112// is a high GR32.
113void SystemZInstrInfo::expandRXYPseudo(MachineInstr *MI, unsigned LowOpcode,
114                                       unsigned HighOpcode) const {
115  unsigned Reg = MI->getOperand(0).getReg();
116  unsigned Opcode = getOpcodeForOffset(isHighReg(Reg) ? HighOpcode : LowOpcode,
117                                       MI->getOperand(2).getImm());
118  MI->setDesc(get(Opcode));
119}
120
121// MI is an RR-style pseudo instruction that zero-extends the low Size bits
122// of one GRX32 into another.  Replace it with LowOpcode if both operands
123// are low registers, otherwise use RISB[LH]G.
124void SystemZInstrInfo::expandZExtPseudo(MachineInstr *MI, unsigned LowOpcode,
125                                        unsigned Size) const {
126  emitGRX32Move(*MI->getParent(), MI, MI->getDebugLoc(),
127                MI->getOperand(0).getReg(), MI->getOperand(1).getReg(),
128                LowOpcode, Size, MI->getOperand(1).isKill());
129  MI->eraseFromParent();
130}
131
132// Emit a zero-extending move from 32-bit GPR SrcReg to 32-bit GPR
133// DestReg before MBBI in MBB.  Use LowLowOpcode when both DestReg and SrcReg
134// are low registers, otherwise use RISB[LH]G.  Size is the number of bits
135// taken from the low end of SrcReg (8 for LLCR, 16 for LLHR and 32 for LR).
136// KillSrc is true if this move is the last use of SrcReg.
137void SystemZInstrInfo::emitGRX32Move(MachineBasicBlock &MBB,
138                                     MachineBasicBlock::iterator MBBI,
139                                     DebugLoc DL, unsigned DestReg,
140                                     unsigned SrcReg, unsigned LowLowOpcode,
141                                     unsigned Size, bool KillSrc) const {
142  unsigned Opcode;
143  bool DestIsHigh = isHighReg(DestReg);
144  bool SrcIsHigh = isHighReg(SrcReg);
145  if (DestIsHigh && SrcIsHigh)
146    Opcode = SystemZ::RISBHH;
147  else if (DestIsHigh && !SrcIsHigh)
148    Opcode = SystemZ::RISBHL;
149  else if (!DestIsHigh && SrcIsHigh)
150    Opcode = SystemZ::RISBLH;
151  else {
152    BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg)
153      .addReg(SrcReg, getKillRegState(KillSrc));
154    return;
155  }
156  unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0);
157  BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
158    .addReg(DestReg, RegState::Undef)
159    .addReg(SrcReg, getKillRegState(KillSrc))
160    .addImm(32 - Size).addImm(128 + 31).addImm(Rotate);
161}
162
163// If MI is a simple load or store for a frame object, return the register
164// it loads or stores and set FrameIndex to the index of the frame object.
165// Return 0 otherwise.
166//
167// Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
168static int isSimpleMove(const MachineInstr *MI, int &FrameIndex,
169                        unsigned Flag) {
170  const MCInstrDesc &MCID = MI->getDesc();
171  if ((MCID.TSFlags & Flag) &&
172      MI->getOperand(1).isFI() &&
173      MI->getOperand(2).getImm() == 0 &&
174      MI->getOperand(3).getReg() == 0) {
175    FrameIndex = MI->getOperand(1).getIndex();
176    return MI->getOperand(0).getReg();
177  }
178  return 0;
179}
180
181unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
182                                               int &FrameIndex) const {
183  return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXLoad);
184}
185
186unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
187                                              int &FrameIndex) const {
188  return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXStore);
189}
190
191bool SystemZInstrInfo::isStackSlotCopy(const MachineInstr *MI,
192                                       int &DestFrameIndex,
193                                       int &SrcFrameIndex) const {
194  // Check for MVC 0(Length,FI1),0(FI2)
195  const MachineFrameInfo *MFI = MI->getParent()->getParent()->getFrameInfo();
196  if (MI->getOpcode() != SystemZ::MVC ||
197      !MI->getOperand(0).isFI() ||
198      MI->getOperand(1).getImm() != 0 ||
199      !MI->getOperand(3).isFI() ||
200      MI->getOperand(4).getImm() != 0)
201    return false;
202
203  // Check that Length covers the full slots.
204  int64_t Length = MI->getOperand(2).getImm();
205  unsigned FI1 = MI->getOperand(0).getIndex();
206  unsigned FI2 = MI->getOperand(3).getIndex();
207  if (MFI->getObjectSize(FI1) != Length ||
208      MFI->getObjectSize(FI2) != Length)
209    return false;
210
211  DestFrameIndex = FI1;
212  SrcFrameIndex = FI2;
213  return true;
214}
215
216bool SystemZInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
217                                     MachineBasicBlock *&TBB,
218                                     MachineBasicBlock *&FBB,
219                                     SmallVectorImpl<MachineOperand> &Cond,
220                                     bool AllowModify) const {
221  // Most of the code and comments here are boilerplate.
222
223  // Start from the bottom of the block and work up, examining the
224  // terminator instructions.
225  MachineBasicBlock::iterator I = MBB.end();
226  while (I != MBB.begin()) {
227    --I;
228    if (I->isDebugValue())
229      continue;
230
231    // Working from the bottom, when we see a non-terminator instruction, we're
232    // done.
233    if (!isUnpredicatedTerminator(I))
234      break;
235
236    // A terminator that isn't a branch can't easily be handled by this
237    // analysis.
238    if (!I->isBranch())
239      return true;
240
241    // Can't handle indirect branches.
242    SystemZII::Branch Branch(getBranchInfo(I));
243    if (!Branch.Target->isMBB())
244      return true;
245
246    // Punt on compound branches.
247    if (Branch.Type != SystemZII::BranchNormal)
248      return true;
249
250    if (Branch.CCMask == SystemZ::CCMASK_ANY) {
251      // Handle unconditional branches.
252      if (!AllowModify) {
253        TBB = Branch.Target->getMBB();
254        continue;
255      }
256
257      // If the block has any instructions after a JMP, delete them.
258      while (llvm::next(I) != MBB.end())
259        llvm::next(I)->eraseFromParent();
260
261      Cond.clear();
262      FBB = 0;
263
264      // Delete the JMP if it's equivalent to a fall-through.
265      if (MBB.isLayoutSuccessor(Branch.Target->getMBB())) {
266        TBB = 0;
267        I->eraseFromParent();
268        I = MBB.end();
269        continue;
270      }
271
272      // TBB is used to indicate the unconditinal destination.
273      TBB = Branch.Target->getMBB();
274      continue;
275    }
276
277    // Working from the bottom, handle the first conditional branch.
278    if (Cond.empty()) {
279      // FIXME: add X86-style branch swap
280      FBB = TBB;
281      TBB = Branch.Target->getMBB();
282      Cond.push_back(MachineOperand::CreateImm(Branch.CCValid));
283      Cond.push_back(MachineOperand::CreateImm(Branch.CCMask));
284      continue;
285    }
286
287    // Handle subsequent conditional branches.
288    assert(Cond.size() == 2 && TBB && "Should have seen a conditional branch");
289
290    // Only handle the case where all conditional branches branch to the same
291    // destination.
292    if (TBB != Branch.Target->getMBB())
293      return true;
294
295    // If the conditions are the same, we can leave them alone.
296    unsigned OldCCValid = Cond[0].getImm();
297    unsigned OldCCMask = Cond[1].getImm();
298    if (OldCCValid == Branch.CCValid && OldCCMask == Branch.CCMask)
299      continue;
300
301    // FIXME: Try combining conditions like X86 does.  Should be easy on Z!
302    return false;
303  }
304
305  return false;
306}
307
308unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
309  // Most of the code and comments here are boilerplate.
310  MachineBasicBlock::iterator I = MBB.end();
311  unsigned Count = 0;
312
313  while (I != MBB.begin()) {
314    --I;
315    if (I->isDebugValue())
316      continue;
317    if (!I->isBranch())
318      break;
319    if (!getBranchInfo(I).Target->isMBB())
320      break;
321    // Remove the branch.
322    I->eraseFromParent();
323    I = MBB.end();
324    ++Count;
325  }
326
327  return Count;
328}
329
330bool SystemZInstrInfo::
331ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
332  assert(Cond.size() == 2 && "Invalid condition");
333  Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm());
334  return false;
335}
336
337unsigned
338SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
339                               MachineBasicBlock *FBB,
340                               const SmallVectorImpl<MachineOperand> &Cond,
341                               DebugLoc DL) const {
342  // In this function we output 32-bit branches, which should always
343  // have enough range.  They can be shortened and relaxed by later code
344  // in the pipeline, if desired.
345
346  // Shouldn't be a fall through.
347  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
348  assert((Cond.size() == 2 || Cond.size() == 0) &&
349         "SystemZ branch conditions have one component!");
350
351  if (Cond.empty()) {
352    // Unconditional branch?
353    assert(!FBB && "Unconditional branch with multiple successors!");
354    BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
355    return 1;
356  }
357
358  // Conditional branch.
359  unsigned Count = 0;
360  unsigned CCValid = Cond[0].getImm();
361  unsigned CCMask = Cond[1].getImm();
362  BuildMI(&MBB, DL, get(SystemZ::BRC))
363    .addImm(CCValid).addImm(CCMask).addMBB(TBB);
364  ++Count;
365
366  if (FBB) {
367    // Two-way Conditional branch. Insert the second branch.
368    BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
369    ++Count;
370  }
371  return Count;
372}
373
374bool SystemZInstrInfo::analyzeCompare(const MachineInstr *MI,
375                                      unsigned &SrcReg, unsigned &SrcReg2,
376                                      int &Mask, int &Value) const {
377  assert(MI->isCompare() && "Caller should have checked for a comparison");
378
379  if (MI->getNumExplicitOperands() == 2 &&
380      MI->getOperand(0).isReg() &&
381      MI->getOperand(1).isImm()) {
382    SrcReg = MI->getOperand(0).getReg();
383    SrcReg2 = 0;
384    Value = MI->getOperand(1).getImm();
385    Mask = ~0;
386    return true;
387  }
388
389  return false;
390}
391
392// If Reg is a virtual register, return its definition, otherwise return null.
393static MachineInstr *getDef(unsigned Reg,
394                            const MachineRegisterInfo *MRI) {
395  if (TargetRegisterInfo::isPhysicalRegister(Reg))
396    return 0;
397  return MRI->getUniqueVRegDef(Reg);
398}
399
400// Return true if MI is a shift of type Opcode by Imm bits.
401static bool isShift(MachineInstr *MI, int Opcode, int64_t Imm) {
402  return (MI->getOpcode() == Opcode &&
403          !MI->getOperand(2).getReg() &&
404          MI->getOperand(3).getImm() == Imm);
405}
406
407// If the destination of MI has no uses, delete it as dead.
408static void eraseIfDead(MachineInstr *MI, const MachineRegisterInfo *MRI) {
409  if (MRI->use_nodbg_empty(MI->getOperand(0).getReg()))
410    MI->eraseFromParent();
411}
412
413// Compare compares SrcReg against zero.  Check whether SrcReg contains
414// the result of an IPM sequence whose input CC survives until Compare,
415// and whether Compare is therefore redundant.  Delete it and return
416// true if so.
417static bool removeIPMBasedCompare(MachineInstr *Compare, unsigned SrcReg,
418                                  const MachineRegisterInfo *MRI,
419                                  const TargetRegisterInfo *TRI) {
420  MachineInstr *LGFR = 0;
421  MachineInstr *RLL = getDef(SrcReg, MRI);
422  if (RLL && RLL->getOpcode() == SystemZ::LGFR) {
423    LGFR = RLL;
424    RLL = getDef(LGFR->getOperand(1).getReg(), MRI);
425  }
426  if (!RLL || !isShift(RLL, SystemZ::RLL, 31))
427    return false;
428
429  MachineInstr *SRL = getDef(RLL->getOperand(1).getReg(), MRI);
430  if (!SRL || !isShift(SRL, SystemZ::SRL, 28))
431    return false;
432
433  MachineInstr *IPM = getDef(SRL->getOperand(1).getReg(), MRI);
434  if (!IPM || IPM->getOpcode() != SystemZ::IPM)
435    return false;
436
437  // Check that there are no assignments to CC between the IPM and Compare,
438  if (IPM->getParent() != Compare->getParent())
439    return false;
440  MachineBasicBlock::iterator MBBI = IPM, MBBE = Compare;
441  for (++MBBI; MBBI != MBBE; ++MBBI) {
442    MachineInstr *MI = MBBI;
443    if (MI->modifiesRegister(SystemZ::CC, TRI))
444      return false;
445  }
446
447  Compare->eraseFromParent();
448  if (LGFR)
449    eraseIfDead(LGFR, MRI);
450  eraseIfDead(RLL, MRI);
451  eraseIfDead(SRL, MRI);
452  eraseIfDead(IPM, MRI);
453
454  return true;
455}
456
457bool
458SystemZInstrInfo::optimizeCompareInstr(MachineInstr *Compare,
459                                       unsigned SrcReg, unsigned SrcReg2,
460                                       int Mask, int Value,
461                                       const MachineRegisterInfo *MRI) const {
462  assert(!SrcReg2 && "Only optimizing constant comparisons so far");
463  bool IsLogical = (Compare->getDesc().TSFlags & SystemZII::IsLogical) != 0;
464  if (Value == 0 &&
465      !IsLogical &&
466      removeIPMBasedCompare(Compare, SrcReg, MRI, TM.getRegisterInfo()))
467    return true;
468  return false;
469}
470
471// If Opcode is a move that has a conditional variant, return that variant,
472// otherwise return 0.
473static unsigned getConditionalMove(unsigned Opcode) {
474  switch (Opcode) {
475  case SystemZ::LR:  return SystemZ::LOCR;
476  case SystemZ::LGR: return SystemZ::LOCGR;
477  default:           return 0;
478  }
479}
480
481bool SystemZInstrInfo::isPredicable(MachineInstr *MI) const {
482  unsigned Opcode = MI->getOpcode();
483  if (TM.getSubtargetImpl()->hasLoadStoreOnCond() &&
484      getConditionalMove(Opcode))
485    return true;
486  return false;
487}
488
489bool SystemZInstrInfo::
490isProfitableToIfCvt(MachineBasicBlock &MBB,
491                    unsigned NumCycles, unsigned ExtraPredCycles,
492                    const BranchProbability &Probability) const {
493  // For now only convert single instructions.
494  return NumCycles == 1;
495}
496
497bool SystemZInstrInfo::
498isProfitableToIfCvt(MachineBasicBlock &TMBB,
499                    unsigned NumCyclesT, unsigned ExtraPredCyclesT,
500                    MachineBasicBlock &FMBB,
501                    unsigned NumCyclesF, unsigned ExtraPredCyclesF,
502                    const BranchProbability &Probability) const {
503  // For now avoid converting mutually-exclusive cases.
504  return false;
505}
506
507bool SystemZInstrInfo::
508PredicateInstruction(MachineInstr *MI,
509                     const SmallVectorImpl<MachineOperand> &Pred) const {
510  assert(Pred.size() == 2 && "Invalid condition");
511  unsigned CCValid = Pred[0].getImm();
512  unsigned CCMask = Pred[1].getImm();
513  assert(CCMask > 0 && CCMask < 15 && "Invalid predicate");
514  unsigned Opcode = MI->getOpcode();
515  if (TM.getSubtargetImpl()->hasLoadStoreOnCond()) {
516    if (unsigned CondOpcode = getConditionalMove(Opcode)) {
517      MI->setDesc(get(CondOpcode));
518      MachineInstrBuilder(*MI->getParent()->getParent(), MI)
519        .addImm(CCValid).addImm(CCMask)
520        .addReg(SystemZ::CC, RegState::Implicit);;
521      return true;
522    }
523  }
524  return false;
525}
526
527void
528SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
529			      MachineBasicBlock::iterator MBBI, DebugLoc DL,
530			      unsigned DestReg, unsigned SrcReg,
531			      bool KillSrc) const {
532  // Split 128-bit GPR moves into two 64-bit moves.  This handles ADDR128 too.
533  if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) {
534    copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_h64),
535                RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc);
536    copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_l64),
537                RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc);
538    return;
539  }
540
541  if (SystemZ::GRX32BitRegClass.contains(DestReg, SrcReg)) {
542    emitGRX32Move(MBB, MBBI, DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc);
543    return;
544  }
545
546  // Everything else needs only one instruction.
547  unsigned Opcode;
548  if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg))
549    Opcode = SystemZ::LGR;
550  else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg))
551    Opcode = SystemZ::LER;
552  else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg))
553    Opcode = SystemZ::LDR;
554  else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg))
555    Opcode = SystemZ::LXR;
556  else
557    llvm_unreachable("Impossible reg-to-reg copy");
558
559  BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
560    .addReg(SrcReg, getKillRegState(KillSrc));
561}
562
563void
564SystemZInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
565				      MachineBasicBlock::iterator MBBI,
566				      unsigned SrcReg, bool isKill,
567				      int FrameIdx,
568				      const TargetRegisterClass *RC,
569				      const TargetRegisterInfo *TRI) const {
570  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
571
572  // Callers may expect a single instruction, so keep 128-bit moves
573  // together for now and lower them after register allocation.
574  unsigned LoadOpcode, StoreOpcode;
575  getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
576  addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode))
577		    .addReg(SrcReg, getKillRegState(isKill)), FrameIdx);
578}
579
580void
581SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
582				       MachineBasicBlock::iterator MBBI,
583				       unsigned DestReg, int FrameIdx,
584				       const TargetRegisterClass *RC,
585				       const TargetRegisterInfo *TRI) const {
586  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
587
588  // Callers may expect a single instruction, so keep 128-bit moves
589  // together for now and lower them after register allocation.
590  unsigned LoadOpcode, StoreOpcode;
591  getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
592  addFrameReference(BuildMI(MBB, MBBI, DL, get(LoadOpcode), DestReg),
593                    FrameIdx);
594}
595
596// Return true if MI is a simple load or store with a 12-bit displacement
597// and no index.  Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
598static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) {
599  const MCInstrDesc &MCID = MI->getDesc();
600  return ((MCID.TSFlags & Flag) &&
601          isUInt<12>(MI->getOperand(2).getImm()) &&
602          MI->getOperand(3).getReg() == 0);
603}
604
605namespace {
606  struct LogicOp {
607    LogicOp() : RegSize(0), ImmLSB(0), ImmSize(0) {}
608    LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize)
609      : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
610
611    operator bool() const { return RegSize; }
612
613    unsigned RegSize, ImmLSB, ImmSize;
614  };
615}
616
617static LogicOp interpretAndImmediate(unsigned Opcode) {
618  switch (Opcode) {
619  case SystemZ::NILL:   return LogicOp(32,  0, 16);
620  case SystemZ::NILH:   return LogicOp(32, 16, 16);
621  case SystemZ::NILL64: return LogicOp(64,  0, 16);
622  case SystemZ::NILH64: return LogicOp(64, 16, 16);
623  case SystemZ::NIHL:   return LogicOp(64, 32, 16);
624  case SystemZ::NIHH:   return LogicOp(64, 48, 16);
625  case SystemZ::NILF:   return LogicOp(32,  0, 32);
626  case SystemZ::NILF64: return LogicOp(64,  0, 32);
627  case SystemZ::NIHF:   return LogicOp(64, 32, 32);
628  default:              return LogicOp();
629  }
630}
631
632// Used to return from convertToThreeAddress after replacing two-address
633// instruction OldMI with three-address instruction NewMI.
634static MachineInstr *finishConvertToThreeAddress(MachineInstr *OldMI,
635                                                 MachineInstr *NewMI,
636                                                 LiveVariables *LV) {
637  if (LV) {
638    unsigned NumOps = OldMI->getNumOperands();
639    for (unsigned I = 1; I < NumOps; ++I) {
640      MachineOperand &Op = OldMI->getOperand(I);
641      if (Op.isReg() && Op.isKill())
642        LV->replaceKillInstruction(Op.getReg(), OldMI, NewMI);
643    }
644  }
645  return NewMI;
646}
647
648MachineInstr *
649SystemZInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
650                                        MachineBasicBlock::iterator &MBBI,
651                                        LiveVariables *LV) const {
652  MachineInstr *MI = MBBI;
653  MachineBasicBlock *MBB = MI->getParent();
654
655  unsigned Opcode = MI->getOpcode();
656  unsigned NumOps = MI->getNumOperands();
657
658  // Try to convert something like SLL into SLLK, if supported.
659  // We prefer to keep the two-operand form where possible both
660  // because it tends to be shorter and because some instructions
661  // have memory forms that can be used during spilling.
662  if (TM.getSubtargetImpl()->hasDistinctOps()) {
663    int ThreeOperandOpcode = SystemZ::getThreeOperandOpcode(Opcode);
664    if (ThreeOperandOpcode >= 0) {
665      MachineOperand &Dest = MI->getOperand(0);
666      MachineOperand &Src = MI->getOperand(1);
667      MachineInstrBuilder MIB =
668        BuildMI(*MBB, MBBI, MI->getDebugLoc(), get(ThreeOperandOpcode))
669        .addOperand(Dest);
670      // Keep the kill state, but drop the tied flag.
671      MIB.addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg());
672      // Keep the remaining operands as-is.
673      for (unsigned I = 2; I < NumOps; ++I)
674        MIB.addOperand(MI->getOperand(I));
675      return finishConvertToThreeAddress(MI, MIB, LV);
676    }
677  }
678
679  // Try to convert an AND into an RISBG-type instruction.
680  if (LogicOp And = interpretAndImmediate(Opcode)) {
681    unsigned NewOpcode;
682    if (And.RegSize == 64)
683      NewOpcode = SystemZ::RISBG;
684    else if (TM.getSubtargetImpl()->hasHighWord())
685      NewOpcode = SystemZ::RISBLL;
686    else
687      // We can't use RISBG for 32-bit operations because it clobbers the
688      // high word of the destination too.
689      NewOpcode = 0;
690    if (NewOpcode) {
691      uint64_t Imm = MI->getOperand(2).getImm() << And.ImmLSB;
692      // AND IMMEDIATE leaves the other bits of the register unchanged.
693      Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
694      unsigned Start, End;
695      if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
696        if (NewOpcode == SystemZ::RISBLL) {
697          Start &= 31;
698          End &= 31;
699        }
700        MachineOperand &Dest = MI->getOperand(0);
701        MachineOperand &Src = MI->getOperand(1);
702        MachineInstrBuilder MIB =
703          BuildMI(*MBB, MI, MI->getDebugLoc(), get(NewOpcode))
704          .addOperand(Dest).addReg(0)
705          .addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg())
706          .addImm(Start).addImm(End + 128).addImm(0);
707        return finishConvertToThreeAddress(MI, MIB, LV);
708      }
709    }
710  }
711  return 0;
712}
713
714MachineInstr *
715SystemZInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
716                                        MachineInstr *MI,
717                                        const SmallVectorImpl<unsigned> &Ops,
718                                        int FrameIndex) const {
719  const MachineFrameInfo *MFI = MF.getFrameInfo();
720  unsigned Size = MFI->getObjectSize(FrameIndex);
721
722  // Eary exit for cases we don't care about
723  if (Ops.size() != 1)
724    return 0;
725
726  unsigned OpNum = Ops[0];
727  assert(Size == MF.getRegInfo()
728         .getRegClass(MI->getOperand(OpNum).getReg())->getSize() &&
729         "Invalid size combination");
730
731  unsigned Opcode = MI->getOpcode();
732  if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
733    bool Op0IsGPR = (Opcode == SystemZ::LGDR);
734    bool Op1IsGPR = (Opcode == SystemZ::LDGR);
735    // If we're spilling the destination of an LDGR or LGDR, store the
736    // source register instead.
737    if (OpNum == 0) {
738      unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;
739      return BuildMI(MF, MI->getDebugLoc(), get(StoreOpcode))
740        .addOperand(MI->getOperand(1)).addFrameIndex(FrameIndex)
741        .addImm(0).addReg(0);
742    }
743    // If we're spilling the source of an LDGR or LGDR, load the
744    // destination register instead.
745    if (OpNum == 1) {
746      unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD;
747      unsigned Dest = MI->getOperand(0).getReg();
748      return BuildMI(MF, MI->getDebugLoc(), get(LoadOpcode), Dest)
749        .addFrameIndex(FrameIndex).addImm(0).addReg(0);
750    }
751  }
752
753  // Look for cases where the source of a simple store or the destination
754  // of a simple load is being spilled.  Try to use MVC instead.
755  //
756  // Although MVC is in practice a fast choice in these cases, it is still
757  // logically a bytewise copy.  This means that we cannot use it if the
758  // load or store is volatile.  We also wouldn't be able to use MVC if
759  // the two memories partially overlap, but that case cannot occur here,
760  // because we know that one of the memories is a full frame index.
761  //
762  // For performance reasons, we also want to avoid using MVC if the addresses
763  // might be equal.  We don't worry about that case here, because spill slot
764  // coloring happens later, and because we have special code to remove
765  // MVCs that turn out to be redundant.
766  if (OpNum == 0 && MI->hasOneMemOperand()) {
767    MachineMemOperand *MMO = *MI->memoperands_begin();
768    if (MMO->getSize() == Size && !MMO->isVolatile()) {
769      // Handle conversion of loads.
770      if (isSimpleBD12Move(MI, SystemZII::SimpleBDXLoad)) {
771        return BuildMI(MF, MI->getDebugLoc(), get(SystemZ::MVC))
772          .addFrameIndex(FrameIndex).addImm(0).addImm(Size)
773          .addOperand(MI->getOperand(1)).addImm(MI->getOperand(2).getImm())
774          .addMemOperand(MMO);
775      }
776      // Handle conversion of stores.
777      if (isSimpleBD12Move(MI, SystemZII::SimpleBDXStore)) {
778        return BuildMI(MF, MI->getDebugLoc(), get(SystemZ::MVC))
779          .addOperand(MI->getOperand(1)).addImm(MI->getOperand(2).getImm())
780          .addImm(Size).addFrameIndex(FrameIndex).addImm(0)
781          .addMemOperand(MMO);
782      }
783    }
784  }
785
786  // If the spilled operand is the final one, try to change <INSN>R
787  // into <INSN>.
788  int MemOpcode = SystemZ::getMemOpcode(Opcode);
789  if (MemOpcode >= 0) {
790    unsigned NumOps = MI->getNumExplicitOperands();
791    if (OpNum == NumOps - 1) {
792      const MCInstrDesc &MemDesc = get(MemOpcode);
793      uint64_t AccessBytes = SystemZII::getAccessSize(MemDesc.TSFlags);
794      assert(AccessBytes != 0 && "Size of access should be known");
795      assert(AccessBytes <= Size && "Access outside the frame index");
796      uint64_t Offset = Size - AccessBytes;
797      MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(MemOpcode));
798      for (unsigned I = 0; I < OpNum; ++I)
799        MIB.addOperand(MI->getOperand(I));
800      MIB.addFrameIndex(FrameIndex).addImm(Offset);
801      if (MemDesc.TSFlags & SystemZII::HasIndex)
802        MIB.addReg(0);
803      return MIB;
804    }
805  }
806
807  return 0;
808}
809
810MachineInstr *
811SystemZInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI,
812                                        const SmallVectorImpl<unsigned> &Ops,
813                                        MachineInstr* LoadMI) const {
814  return 0;
815}
816
817bool
818SystemZInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
819  switch (MI->getOpcode()) {
820  case SystemZ::L128:
821    splitMove(MI, SystemZ::LG);
822    return true;
823
824  case SystemZ::ST128:
825    splitMove(MI, SystemZ::STG);
826    return true;
827
828  case SystemZ::LX:
829    splitMove(MI, SystemZ::LD);
830    return true;
831
832  case SystemZ::STX:
833    splitMove(MI, SystemZ::STD);
834    return true;
835
836  case SystemZ::LBMux:
837    expandRXYPseudo(MI, SystemZ::LB, SystemZ::LBH);
838    return true;
839
840  case SystemZ::LHMux:
841    expandRXYPseudo(MI, SystemZ::LH, SystemZ::LHH);
842    return true;
843
844  case SystemZ::LLCRMux:
845    expandZExtPseudo(MI, SystemZ::LLCR, 8);
846    return true;
847
848  case SystemZ::LLHRMux:
849    expandZExtPseudo(MI, SystemZ::LLHR, 16);
850    return true;
851
852  case SystemZ::LLCMux:
853    expandRXYPseudo(MI, SystemZ::LLC, SystemZ::LLCH);
854    return true;
855
856  case SystemZ::LLHMux:
857    expandRXYPseudo(MI, SystemZ::LLH, SystemZ::LLHH);
858    return true;
859
860  case SystemZ::LMux:
861    expandRXYPseudo(MI, SystemZ::L, SystemZ::LFH);
862    return true;
863
864  case SystemZ::STCMux:
865    expandRXYPseudo(MI, SystemZ::STC, SystemZ::STCH);
866    return true;
867
868  case SystemZ::STHMux:
869    expandRXYPseudo(MI, SystemZ::STH, SystemZ::STHH);
870    return true;
871
872  case SystemZ::STMux:
873    expandRXYPseudo(MI, SystemZ::ST, SystemZ::STFH);
874    return true;
875
876  case SystemZ::LHIMux:
877    expandRIPseudo(MI, SystemZ::LHI, SystemZ::IIHF, true);
878    return true;
879
880  case SystemZ::IIFMux:
881    expandRIPseudo(MI, SystemZ::IILF, SystemZ::IIHF, false);
882    return true;
883
884  case SystemZ::IILMux:
885    expandRIPseudo(MI, SystemZ::IILL, SystemZ::IIHL, false);
886    return true;
887
888  case SystemZ::IIHMux:
889    expandRIPseudo(MI, SystemZ::IILH, SystemZ::IIHH, false);
890    return true;
891
892  case SystemZ::ADJDYNALLOC:
893    splitAdjDynAlloc(MI);
894    return true;
895
896  default:
897    return false;
898  }
899}
900
901uint64_t SystemZInstrInfo::getInstSizeInBytes(const MachineInstr *MI) const {
902  if (MI->getOpcode() == TargetOpcode::INLINEASM) {
903    const MachineFunction *MF = MI->getParent()->getParent();
904    const char *AsmStr = MI->getOperand(0).getSymbolName();
905    return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
906  }
907  return MI->getDesc().getSize();
908}
909
910SystemZII::Branch
911SystemZInstrInfo::getBranchInfo(const MachineInstr *MI) const {
912  switch (MI->getOpcode()) {
913  case SystemZ::BR:
914  case SystemZ::J:
915  case SystemZ::JG:
916    return SystemZII::Branch(SystemZII::BranchNormal, SystemZ::CCMASK_ANY,
917                             SystemZ::CCMASK_ANY, &MI->getOperand(0));
918
919  case SystemZ::BRC:
920  case SystemZ::BRCL:
921    return SystemZII::Branch(SystemZII::BranchNormal,
922                             MI->getOperand(0).getImm(),
923                             MI->getOperand(1).getImm(), &MI->getOperand(2));
924
925  case SystemZ::BRCT:
926    return SystemZII::Branch(SystemZII::BranchCT, SystemZ::CCMASK_ICMP,
927                             SystemZ::CCMASK_CMP_NE, &MI->getOperand(2));
928
929  case SystemZ::BRCTG:
930    return SystemZII::Branch(SystemZII::BranchCTG, SystemZ::CCMASK_ICMP,
931                             SystemZ::CCMASK_CMP_NE, &MI->getOperand(2));
932
933  case SystemZ::CIJ:
934  case SystemZ::CRJ:
935    return SystemZII::Branch(SystemZII::BranchC, SystemZ::CCMASK_ICMP,
936                             MI->getOperand(2).getImm(), &MI->getOperand(3));
937
938  case SystemZ::CLIJ:
939  case SystemZ::CLRJ:
940    return SystemZII::Branch(SystemZII::BranchCL, SystemZ::CCMASK_ICMP,
941                             MI->getOperand(2).getImm(), &MI->getOperand(3));
942
943  case SystemZ::CGIJ:
944  case SystemZ::CGRJ:
945    return SystemZII::Branch(SystemZII::BranchCG, SystemZ::CCMASK_ICMP,
946                             MI->getOperand(2).getImm(), &MI->getOperand(3));
947
948  case SystemZ::CLGIJ:
949  case SystemZ::CLGRJ:
950    return SystemZII::Branch(SystemZII::BranchCLG, SystemZ::CCMASK_ICMP,
951                             MI->getOperand(2).getImm(), &MI->getOperand(3));
952
953  default:
954    llvm_unreachable("Unrecognized branch opcode");
955  }
956}
957
958void SystemZInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC,
959                                           unsigned &LoadOpcode,
960                                           unsigned &StoreOpcode) const {
961  if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
962    LoadOpcode = SystemZ::L;
963    StoreOpcode = SystemZ::ST;
964  } else if (RC == &SystemZ::GRH32BitRegClass) {
965    LoadOpcode = SystemZ::LFH;
966    StoreOpcode = SystemZ::STFH;
967  } else if (RC == &SystemZ::GRX32BitRegClass) {
968    LoadOpcode = SystemZ::LMux;
969    StoreOpcode = SystemZ::STMux;
970  } else if (RC == &SystemZ::GR64BitRegClass ||
971             RC == &SystemZ::ADDR64BitRegClass) {
972    LoadOpcode = SystemZ::LG;
973    StoreOpcode = SystemZ::STG;
974  } else if (RC == &SystemZ::GR128BitRegClass ||
975             RC == &SystemZ::ADDR128BitRegClass) {
976    LoadOpcode = SystemZ::L128;
977    StoreOpcode = SystemZ::ST128;
978  } else if (RC == &SystemZ::FP32BitRegClass) {
979    LoadOpcode = SystemZ::LE;
980    StoreOpcode = SystemZ::STE;
981  } else if (RC == &SystemZ::FP64BitRegClass) {
982    LoadOpcode = SystemZ::LD;
983    StoreOpcode = SystemZ::STD;
984  } else if (RC == &SystemZ::FP128BitRegClass) {
985    LoadOpcode = SystemZ::LX;
986    StoreOpcode = SystemZ::STX;
987  } else
988    llvm_unreachable("Unsupported regclass to load or store");
989}
990
991unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode,
992                                              int64_t Offset) const {
993  const MCInstrDesc &MCID = get(Opcode);
994  int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset);
995  if (isUInt<12>(Offset) && isUInt<12>(Offset2)) {
996    // Get the instruction to use for unsigned 12-bit displacements.
997    int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
998    if (Disp12Opcode >= 0)
999      return Disp12Opcode;
1000
1001    // All address-related instructions can use unsigned 12-bit
1002    // displacements.
1003    return Opcode;
1004  }
1005  if (isInt<20>(Offset) && isInt<20>(Offset2)) {
1006    // Get the instruction to use for signed 20-bit displacements.
1007    int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
1008    if (Disp20Opcode >= 0)
1009      return Disp20Opcode;
1010
1011    // Check whether Opcode allows signed 20-bit displacements.
1012    if (MCID.TSFlags & SystemZII::Has20BitOffset)
1013      return Opcode;
1014  }
1015  return 0;
1016}
1017
1018unsigned SystemZInstrInfo::getLoadAndTest(unsigned Opcode) const {
1019  switch (Opcode) {
1020  case SystemZ::L:    return SystemZ::LT;
1021  case SystemZ::LY:   return SystemZ::LT;
1022  case SystemZ::LG:   return SystemZ::LTG;
1023  case SystemZ::LGF:  return SystemZ::LTGF;
1024  case SystemZ::LR:   return SystemZ::LTR;
1025  case SystemZ::LGFR: return SystemZ::LTGFR;
1026  case SystemZ::LGR:  return SystemZ::LTGR;
1027  case SystemZ::LER:  return SystemZ::LTEBR;
1028  case SystemZ::LDR:  return SystemZ::LTDBR;
1029  case SystemZ::LXR:  return SystemZ::LTXBR;
1030  default:            return 0;
1031  }
1032}
1033
1034// Return true if Mask matches the regexp 0*1+0*, given that zero masks
1035// have already been filtered out.  Store the first set bit in LSB and
1036// the number of set bits in Length if so.
1037static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length) {
1038  unsigned First = findFirstSet(Mask);
1039  uint64_t Top = (Mask >> First) + 1;
1040  if ((Top & -Top) == Top) {
1041    LSB = First;
1042    Length = findFirstSet(Top);
1043    return true;
1044  }
1045  return false;
1046}
1047
1048bool SystemZInstrInfo::isRxSBGMask(uint64_t Mask, unsigned BitSize,
1049                                   unsigned &Start, unsigned &End) const {
1050  // Reject trivial all-zero masks.
1051  if (Mask == 0)
1052    return false;
1053
1054  // Handle the 1+0+ or 0+1+0* cases.  Start then specifies the index of
1055  // the msb and End specifies the index of the lsb.
1056  unsigned LSB, Length;
1057  if (isStringOfOnes(Mask, LSB, Length)) {
1058    Start = 63 - (LSB + Length - 1);
1059    End = 63 - LSB;
1060    return true;
1061  }
1062
1063  // Handle the wrap-around 1+0+1+ cases.  Start then specifies the msb
1064  // of the low 1s and End specifies the lsb of the high 1s.
1065  if (isStringOfOnes(Mask ^ allOnes(BitSize), LSB, Length)) {
1066    assert(LSB > 0 && "Bottom bit must be set");
1067    assert(LSB + Length < BitSize && "Top bit must be set");
1068    Start = 63 - (LSB - 1);
1069    End = 63 - (LSB + Length);
1070    return true;
1071  }
1072
1073  return false;
1074}
1075
1076unsigned SystemZInstrInfo::getCompareAndBranch(unsigned Opcode,
1077                                               const MachineInstr *MI) const {
1078  switch (Opcode) {
1079  case SystemZ::CR:
1080    return SystemZ::CRJ;
1081  case SystemZ::CGR:
1082    return SystemZ::CGRJ;
1083  case SystemZ::CHI:
1084    return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CIJ : 0;
1085  case SystemZ::CGHI:
1086    return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CGIJ : 0;
1087  case SystemZ::CLR:
1088    return SystemZ::CLRJ;
1089  case SystemZ::CLGR:
1090    return SystemZ::CLGRJ;
1091  case SystemZ::CLFI:
1092    return MI && isUInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CLIJ : 0;
1093  case SystemZ::CLGFI:
1094    return MI && isUInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CLGIJ : 0;
1095  default:
1096    return 0;
1097  }
1098}
1099
1100void SystemZInstrInfo::loadImmediate(MachineBasicBlock &MBB,
1101                                     MachineBasicBlock::iterator MBBI,
1102                                     unsigned Reg, uint64_t Value) const {
1103  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1104  unsigned Opcode;
1105  if (isInt<16>(Value))
1106    Opcode = SystemZ::LGHI;
1107  else if (SystemZ::isImmLL(Value))
1108    Opcode = SystemZ::LLILL;
1109  else if (SystemZ::isImmLH(Value)) {
1110    Opcode = SystemZ::LLILH;
1111    Value >>= 16;
1112  } else {
1113    assert(isInt<32>(Value) && "Huge values not handled yet");
1114    Opcode = SystemZ::LGFI;
1115  }
1116  BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);
1117}
1118