SystemZInstrInfo.cpp revision 864e2efce2cb5d02e376933933d96074723fe77c 
1//===- SystemZInstrInfo.cpp - SystemZ Instruction Information --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SystemZ implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SystemZ.h"
15#include "SystemZInstrBuilder.h"
16#include "SystemZInstrInfo.h"
17#include "SystemZMachineFunctionInfo.h"
18#include "SystemZTargetMachine.h"
19#include "SystemZGenInstrInfo.inc"
20#include "llvm/Function.h"
21#include "llvm/CodeGen/MachineFrameInfo.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/CodeGen/PseudoSourceValue.h"
25#include "llvm/Support/ErrorHandling.h"
26using namespace llvm;
27
28SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm)
29  : TargetInstrInfoImpl(SystemZInsts, array_lengthof(SystemZInsts)),
30    RI(tm, *this), TM(tm) {
31  // Fill the spill offsets map
32  static const unsigned SpillOffsTab[][2] = {
33    { SystemZ::R2D,  0x10 },
34    { SystemZ::R3D,  0x18 },
35    { SystemZ::R4D,  0x20 },
36    { SystemZ::R5D,  0x28 },
37    { SystemZ::R6D,  0x30 },
38    { SystemZ::R7D,  0x38 },
39    { SystemZ::R8D,  0x40 },
40    { SystemZ::R9D,  0x48 },
41    { SystemZ::R10D, 0x50 },
42    { SystemZ::R11D, 0x58 },
43    { SystemZ::R12D, 0x60 },
44    { SystemZ::R13D, 0x68 },
45    { SystemZ::R14D, 0x70 },
46    { SystemZ::R15D, 0x78 }
47  };
48
49  RegSpillOffsets.grow(SystemZ::NUM_TARGET_REGS);
50
51  for (unsigned i = 0, e = array_lengthof(SpillOffsTab); i != e; ++i)
52    RegSpillOffsets[SpillOffsTab[i][0]] = SpillOffsTab[i][1];
53}
54
55/// isGVStub - Return true if the GV requires an extra load to get the
56/// real address.
57static inline bool isGVStub(GlobalValue *GV, SystemZTargetMachine &TM) {
58  return TM.getSubtarget<SystemZSubtarget>().GVRequiresExtraLoad(GV, TM, false);
59}
60
61void SystemZInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
62                                          MachineBasicBlock::iterator MI,
63                                    unsigned SrcReg, bool isKill, int FrameIdx,
64                                    const TargetRegisterClass *RC) const {
65  DebugLoc DL = DebugLoc::getUnknownLoc();
66  if (MI != MBB.end()) DL = MI->getDebugLoc();
67
68  unsigned Opc = 0;
69  if (RC == &SystemZ::GR32RegClass ||
70      RC == &SystemZ::ADDR32RegClass)
71    Opc = SystemZ::MOV32mr;
72  else if (RC == &SystemZ::GR64RegClass ||
73           RC == &SystemZ::ADDR64RegClass) {
74    Opc = SystemZ::MOV64mr;
75  } else if (RC == &SystemZ::FP32RegClass) {
76    Opc = SystemZ::FMOV32mr;
77  } else if (RC == &SystemZ::FP64RegClass) {
78    Opc = SystemZ::FMOV64mr;
79  } else if (RC == &SystemZ::GR64PRegClass) {
80    Opc = SystemZ::MOV64Pmr;
81  } else if (RC == &SystemZ::GR128RegClass) {
82    Opc = SystemZ::MOV128mr;
83  } else
84    llvm_unreachable("Unsupported regclass to store");
85
86  addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
87    .addReg(SrcReg, getKillRegState(isKill));
88}
89
90void SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
91                                           MachineBasicBlock::iterator MI,
92                                           unsigned DestReg, int FrameIdx,
93                                           const TargetRegisterClass *RC) const{
94  DebugLoc DL = DebugLoc::getUnknownLoc();
95  if (MI != MBB.end()) DL = MI->getDebugLoc();
96
97  unsigned Opc = 0;
98  if (RC == &SystemZ::GR32RegClass ||
99      RC == &SystemZ::ADDR32RegClass)
100    Opc = SystemZ::MOV32rm;
101  else if (RC == &SystemZ::GR64RegClass ||
102           RC == &SystemZ::ADDR64RegClass) {
103    Opc = SystemZ::MOV64rm;
104  } else if (RC == &SystemZ::FP32RegClass) {
105    Opc = SystemZ::FMOV32rm;
106  } else if (RC == &SystemZ::FP64RegClass) {
107    Opc = SystemZ::FMOV64rm;
108  } else if (RC == &SystemZ::GR64PRegClass) {
109    Opc = SystemZ::MOV64Prm;
110  } else if (RC == &SystemZ::GR128RegClass) {
111    Opc = SystemZ::MOV128rm;
112  } else
113    llvm_unreachable("Unsupported regclass to load");
114
115  addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
116}
117
118bool SystemZInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
119                                    MachineBasicBlock::iterator I,
120                                    unsigned DestReg, unsigned SrcReg,
121                                    const TargetRegisterClass *DestRC,
122                                    const TargetRegisterClass *SrcRC) const {
123  DebugLoc DL = DebugLoc::getUnknownLoc();
124  if (I != MBB.end()) DL = I->getDebugLoc();
125
126  // Determine if DstRC and SrcRC have a common superclass.
127  const TargetRegisterClass *CommonRC = DestRC;
128  if (DestRC == SrcRC)
129    /* Same regclass for source and dest */;
130  else if (CommonRC->hasSuperClass(SrcRC))
131    CommonRC = SrcRC;
132  else if (!CommonRC->hasSubClass(SrcRC))
133    CommonRC = 0;
134
135  if (CommonRC) {
136    if (CommonRC == &SystemZ::GR64RegClass ||
137        CommonRC == &SystemZ::ADDR64RegClass) {
138      BuildMI(MBB, I, DL, get(SystemZ::MOV64rr), DestReg).addReg(SrcReg);
139    } else if (CommonRC == &SystemZ::GR32RegClass ||
140               CommonRC == &SystemZ::ADDR32RegClass) {
141      BuildMI(MBB, I, DL, get(SystemZ::MOV32rr), DestReg).addReg(SrcReg);
142    } else if (CommonRC == &SystemZ::GR64PRegClass) {
143      BuildMI(MBB, I, DL, get(SystemZ::MOV64rrP), DestReg).addReg(SrcReg);
144    } else if (CommonRC == &SystemZ::GR128RegClass) {
145      BuildMI(MBB, I, DL, get(SystemZ::MOV128rr), DestReg).addReg(SrcReg);
146    } else if (CommonRC == &SystemZ::FP32RegClass) {
147      BuildMI(MBB, I, DL, get(SystemZ::FMOV32rr), DestReg).addReg(SrcReg);
148    } else if (CommonRC == &SystemZ::FP64RegClass) {
149      BuildMI(MBB, I, DL, get(SystemZ::FMOV64rr), DestReg).addReg(SrcReg);
150    } else {
151      return false;
152    }
153
154    return true;
155  }
156
157  if ((SrcRC == &SystemZ::GR64RegClass &&
158       DestRC == &SystemZ::ADDR64RegClass) ||
159      (DestRC == &SystemZ::GR64RegClass &&
160       SrcRC == &SystemZ::ADDR64RegClass)) {
161    BuildMI(MBB, I, DL, get(SystemZ::MOV64rr), DestReg).addReg(SrcReg);
162    return true;
163  } else if ((SrcRC == &SystemZ::GR32RegClass &&
164              DestRC == &SystemZ::ADDR32RegClass) ||
165             (DestRC == &SystemZ::GR32RegClass &&
166              SrcRC == &SystemZ::ADDR32RegClass)) {
167    BuildMI(MBB, I, DL, get(SystemZ::MOV32rr), DestReg).addReg(SrcReg);
168    return true;
169  }
170
171  return false;
172}
173
174bool
175SystemZInstrInfo::isMoveInstr(const MachineInstr& MI,
176                              unsigned &SrcReg, unsigned &DstReg,
177                              unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
178  switch (MI.getOpcode()) {
179  default:
180    return false;
181  case SystemZ::MOV32rr:
182  case SystemZ::MOV64rr:
183  case SystemZ::MOV64rrP:
184  case SystemZ::MOV128rr:
185  case SystemZ::FMOV32rr:
186  case SystemZ::FMOV64rr:
187    assert(MI.getNumOperands() >= 2 &&
188           MI.getOperand(0).isReg() &&
189           MI.getOperand(1).isReg() &&
190           "invalid register-register move instruction");
191    SrcReg = MI.getOperand(1).getReg();
192    DstReg = MI.getOperand(0).getReg();
193    SrcSubIdx = MI.getOperand(1).getSubReg();
194    DstSubIdx = MI.getOperand(0).getSubReg();
195    return true;
196  }
197}
198
199unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
200                                               int &FrameIndex) const {
201  switch (MI->getOpcode()) {
202  default: break;
203  case SystemZ::MOV32rm:
204  case SystemZ::MOV32rmy:
205  case SystemZ::MOV64rm:
206  case SystemZ::MOVSX32rm8:
207  case SystemZ::MOVSX32rm16y:
208  case SystemZ::MOVSX64rm8:
209  case SystemZ::MOVSX64rm16:
210  case SystemZ::MOVSX64rm32:
211  case SystemZ::MOVZX32rm8:
212  case SystemZ::MOVZX32rm16:
213  case SystemZ::MOVZX64rm8:
214  case SystemZ::MOVZX64rm16:
215  case SystemZ::MOVZX64rm32:
216  case SystemZ::FMOV32rm:
217  case SystemZ::FMOV32rmy:
218  case SystemZ::FMOV64rm:
219  case SystemZ::FMOV64rmy:
220  case SystemZ::MOV64Prm:
221  case SystemZ::MOV64Prmy:
222  case SystemZ::MOV128rm:
223    if (MI->getOperand(1).isFI() &&
224        MI->getOperand(2).isImm() && MI->getOperand(3).isReg() &&
225        MI->getOperand(2).getImm() == 0 && MI->getOperand(3).getReg() == 0) {
226      FrameIndex = MI->getOperand(1).getIndex();
227      return MI->getOperand(0).getReg();
228    }
229    break;
230  }
231  return 0;
232}
233
234unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
235                                              int &FrameIndex) const {
236  switch (MI->getOpcode()) {
237  default: break;
238  case SystemZ::MOV32mr:
239  case SystemZ::MOV32mry:
240  case SystemZ::MOV64mr:
241  case SystemZ::MOV32m8r:
242  case SystemZ::MOV32m8ry:
243  case SystemZ::MOV32m16r:
244  case SystemZ::MOV32m16ry:
245  case SystemZ::MOV64m8r:
246  case SystemZ::MOV64m8ry:
247  case SystemZ::MOV64m16r:
248  case SystemZ::MOV64m16ry:
249  case SystemZ::MOV64m32r:
250  case SystemZ::MOV64m32ry:
251  case SystemZ::FMOV32mr:
252  case SystemZ::FMOV32mry:
253  case SystemZ::FMOV64mr:
254  case SystemZ::FMOV64mry:
255  case SystemZ::MOV64Pmr:
256  case SystemZ::MOV64Pmry:
257  case SystemZ::MOV128mr:
258    if (MI->getOperand(0).isFI() &&
259        MI->getOperand(1).isImm() && MI->getOperand(2).isReg() &&
260        MI->getOperand(1).getImm() == 0 && MI->getOperand(2).getReg() == 0) {
261      FrameIndex = MI->getOperand(0).getIndex();
262      return MI->getOperand(3).getReg();
263    }
264    break;
265  }
266  return 0;
267}
268
269bool
270SystemZInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
271                                           MachineBasicBlock::iterator MI,
272                                const std::vector<CalleeSavedInfo> &CSI) const {
273  if (CSI.empty())
274    return false;
275
276  DebugLoc DL = DebugLoc::getUnknownLoc();
277  if (MI != MBB.end()) DL = MI->getDebugLoc();
278
279  MachineFunction &MF = *MBB.getParent();
280  SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>();
281  unsigned CalleeFrameSize = 0;
282
283  // Scan the callee-saved and find the bounds of register spill area.
284  unsigned LowReg = 0, HighReg = 0, StartOffset = -1U, EndOffset = 0;
285  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
286    unsigned Reg = CSI[i].getReg();
287    const TargetRegisterClass *RegClass = CSI[i].getRegClass();
288    if (RegClass != &SystemZ::FP64RegClass) {
289      unsigned Offset = RegSpillOffsets[Reg];
290      CalleeFrameSize += 8;
291      if (StartOffset > Offset) {
292        LowReg = Reg; StartOffset = Offset;
293      }
294      if (EndOffset < Offset) {
295        HighReg = Reg; EndOffset = RegSpillOffsets[Reg];
296      }
297    }
298  }
299
300  // Save information for epilogue inserter.
301  MFI->setCalleeSavedFrameSize(CalleeFrameSize);
302  MFI->setLowReg(LowReg); MFI->setHighReg(HighReg);
303
304  // Save GPRs
305  if (StartOffset) {
306    // Build a store instruction. Use STORE MULTIPLE instruction if there are many
307    // registers to store, otherwise - just STORE.
308    MachineInstrBuilder MIB =
309      BuildMI(MBB, MI, DL, get((LowReg == HighReg ?
310                                SystemZ::MOV64mr : SystemZ::MOV64mrm)));
311
312    // Add store operands.
313    MIB.addReg(SystemZ::R15D).addImm(StartOffset);
314    if (LowReg == HighReg)
315      MIB.addReg(0);
316    MIB.addReg(LowReg, RegState::Kill);
317    if (LowReg != HighReg)
318      MIB.addReg(HighReg, RegState::Kill);
319
320    // Do a second scan adding regs as being killed by instruction
321    for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
322      unsigned Reg = CSI[i].getReg();
323      // Add the callee-saved register as live-in. It's killed at the spill.
324      MBB.addLiveIn(Reg);
325      if (Reg != LowReg && Reg != HighReg)
326        MIB.addReg(Reg, RegState::ImplicitKill);
327    }
328  }
329
330  // Save FPRs
331  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
332    unsigned Reg = CSI[i].getReg();
333    const TargetRegisterClass *RegClass = CSI[i].getRegClass();
334    if (RegClass == &SystemZ::FP64RegClass) {
335      MBB.addLiveIn(Reg);
336      storeRegToStackSlot(MBB, MI, Reg, true, CSI[i].getFrameIdx(), RegClass);
337    }
338  }
339
340  return true;
341}
342
343bool
344SystemZInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
345                                             MachineBasicBlock::iterator MI,
346                                const std::vector<CalleeSavedInfo> &CSI) const {
347  if (CSI.empty())
348    return false;
349
350  DebugLoc DL = DebugLoc::getUnknownLoc();
351  if (MI != MBB.end()) DL = MI->getDebugLoc();
352
353  MachineFunction &MF = *MBB.getParent();
354  const TargetRegisterInfo *RegInfo= MF.getTarget().getRegisterInfo();
355  SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>();
356
357  // Restore FP registers
358  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
359    unsigned Reg = CSI[i].getReg();
360    const TargetRegisterClass *RegClass = CSI[i].getRegClass();
361    if (RegClass == &SystemZ::FP64RegClass)
362      loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass);
363  }
364
365  // Restore GP registers
366  unsigned LowReg = MFI->getLowReg(), HighReg = MFI->getHighReg();
367  unsigned StartOffset = RegSpillOffsets[LowReg];
368
369  if (StartOffset) {
370    // Build a load instruction. Use LOAD MULTIPLE instruction if there are many
371    // registers to load, otherwise - just LOAD.
372    MachineInstrBuilder MIB =
373      BuildMI(MBB, MI, DL, get((LowReg == HighReg ?
374                                SystemZ::MOV64rm : SystemZ::MOV64rmm)));
375    // Add store operands.
376    MIB.addReg(LowReg, RegState::Define);
377    if (LowReg != HighReg)
378      MIB.addReg(HighReg, RegState::Define);
379
380    MIB.addReg((RegInfo->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D));
381    MIB.addImm(StartOffset);
382    if (LowReg == HighReg)
383      MIB.addReg(0);
384
385    // Do a second scan adding regs as being defined by instruction
386    for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
387      unsigned Reg = CSI[i].getReg();
388      if (Reg != LowReg && Reg != HighReg)
389        MIB.addReg(Reg, RegState::ImplicitDefine);
390    }
391  }
392
393  return true;
394}
395
396bool SystemZInstrInfo::
397ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
398  assert(Cond.size() == 1 && "Invalid Xbranch condition!");
399
400  SystemZCC::CondCodes CC = static_cast<SystemZCC::CondCodes>(Cond[0].getImm());
401  Cond[0].setImm(getOppositeCondition(CC));
402  return false;
403}
404
405bool SystemZInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
406  const TargetInstrDesc &TID = MI->getDesc();
407  if (!TID.isTerminator()) return false;
408
409  // Conditional branch is a special case.
410  if (TID.isBranch() && !TID.isBarrier())
411    return true;
412  if (!TID.isPredicable())
413    return true;
414  return !isPredicated(MI);
415}
416
417bool SystemZInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
418                                     MachineBasicBlock *&TBB,
419                                     MachineBasicBlock *&FBB,
420                                     SmallVectorImpl<MachineOperand> &Cond,
421                                     bool AllowModify) const {
422  // Start from the bottom of the block and work up, examining the
423  // terminator instructions.
424  MachineBasicBlock::iterator I = MBB.end();
425  while (I != MBB.begin()) {
426    --I;
427    // Working from the bottom, when we see a non-terminator
428    // instruction, we're done.
429    if (!isUnpredicatedTerminator(I))
430      break;
431
432    // A terminator that isn't a branch can't easily be handled
433    // by this analysis.
434    if (!I->getDesc().isBranch())
435      return true;
436
437    // Handle unconditional branches.
438    if (I->getOpcode() == SystemZ::JMP) {
439      if (!AllowModify) {
440        TBB = I->getOperand(0).getMBB();
441        continue;
442      }
443
444      // If the block has any instructions after a JMP, delete them.
445      while (llvm::next(I) != MBB.end())
446        llvm::next(I)->eraseFromParent();
447      Cond.clear();
448      FBB = 0;
449
450      // Delete the JMP if it's equivalent to a fall-through.
451      if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
452        TBB = 0;
453        I->eraseFromParent();
454        I = MBB.end();
455        continue;
456      }
457
458      // TBB is used to indicate the unconditinal destination.
459      TBB = I->getOperand(0).getMBB();
460      continue;
461    }
462
463    // Handle conditional branches.
464    SystemZCC::CondCodes BranchCode = getCondFromBranchOpc(I->getOpcode());
465    if (BranchCode == SystemZCC::INVALID)
466      return true;  // Can't handle indirect branch.
467
468    // Working from the bottom, handle the first conditional branch.
469    if (Cond.empty()) {
470      FBB = TBB;
471      TBB = I->getOperand(0).getMBB();
472      Cond.push_back(MachineOperand::CreateImm(BranchCode));
473      continue;
474    }
475
476    // Handle subsequent conditional branches. Only handle the case where all
477    // conditional branches branch to the same destination.
478    assert(Cond.size() == 1);
479    assert(TBB);
480
481    // Only handle the case where all conditional branches branch to
482    // the same destination.
483    if (TBB != I->getOperand(0).getMBB())
484      return true;
485
486    SystemZCC::CondCodes OldBranchCode = (SystemZCC::CondCodes)Cond[0].getImm();
487    // If the conditions are the same, we can leave them alone.
488    if (OldBranchCode == BranchCode)
489      continue;
490
491    return true;
492  }
493
494  return false;
495}
496
497unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
498  MachineBasicBlock::iterator I = MBB.end();
499  unsigned Count = 0;
500
501  while (I != MBB.begin()) {
502    --I;
503    if (I->getOpcode() != SystemZ::JMP &&
504        getCondFromBranchOpc(I->getOpcode()) == SystemZCC::INVALID)
505      break;
506    // Remove the branch.
507    I->eraseFromParent();
508    I = MBB.end();
509    ++Count;
510  }
511
512  return Count;
513}
514
515unsigned
516SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
517                               MachineBasicBlock *FBB,
518                            const SmallVectorImpl<MachineOperand> &Cond) const {
519  // FIXME: this should probably have a DebugLoc operand
520  DebugLoc dl = DebugLoc::getUnknownLoc();
521  // Shouldn't be a fall through.
522  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
523  assert((Cond.size() == 1 || Cond.size() == 0) &&
524         "SystemZ branch conditions have one component!");
525
526  if (Cond.empty()) {
527    // Unconditional branch?
528    assert(!FBB && "Unconditional branch with multiple successors!");
529    BuildMI(&MBB, dl, get(SystemZ::JMP)).addMBB(TBB);
530    return 1;
531  }
532
533  // Conditional branch.
534  unsigned Count = 0;
535  SystemZCC::CondCodes CC = (SystemZCC::CondCodes)Cond[0].getImm();
536  BuildMI(&MBB, dl, getBrCond(CC)).addMBB(TBB);
537  ++Count;
538
539  if (FBB) {
540    // Two-way Conditional branch. Insert the second branch.
541    BuildMI(&MBB, dl, get(SystemZ::JMP)).addMBB(FBB);
542    ++Count;
543  }
544  return Count;
545}
546
547const TargetInstrDesc&
548SystemZInstrInfo::getBrCond(SystemZCC::CondCodes CC) const {
549  switch (CC) {
550  default:
551   llvm_unreachable("Unknown condition code!");
552  case SystemZCC::O:   return get(SystemZ::JO);
553  case SystemZCC::H:   return get(SystemZ::JH);
554  case SystemZCC::NLE: return get(SystemZ::JNLE);
555  case SystemZCC::L:   return get(SystemZ::JL);
556  case SystemZCC::NHE: return get(SystemZ::JNHE);
557  case SystemZCC::LH:  return get(SystemZ::JLH);
558  case SystemZCC::NE:  return get(SystemZ::JNE);
559  case SystemZCC::E:   return get(SystemZ::JE);
560  case SystemZCC::NLH: return get(SystemZ::JNLH);
561  case SystemZCC::HE:  return get(SystemZ::JHE);
562  case SystemZCC::NL:  return get(SystemZ::JNL);
563  case SystemZCC::LE:  return get(SystemZ::JLE);
564  case SystemZCC::NH:  return get(SystemZ::JNH);
565  case SystemZCC::NO:  return get(SystemZ::JNO);
566  }
567}
568
569SystemZCC::CondCodes
570SystemZInstrInfo::getCondFromBranchOpc(unsigned Opc) const {
571  switch (Opc) {
572  default:            return SystemZCC::INVALID;
573  case SystemZ::JO:   return SystemZCC::O;
574  case SystemZ::JH:   return SystemZCC::H;
575  case SystemZ::JNLE: return SystemZCC::NLE;
576  case SystemZ::JL:   return SystemZCC::L;
577  case SystemZ::JNHE: return SystemZCC::NHE;
578  case SystemZ::JLH:  return SystemZCC::LH;
579  case SystemZ::JNE:  return SystemZCC::NE;
580  case SystemZ::JE:   return SystemZCC::E;
581  case SystemZ::JNLH: return SystemZCC::NLH;
582  case SystemZ::JHE:  return SystemZCC::HE;
583  case SystemZ::JNL:  return SystemZCC::NL;
584  case SystemZ::JLE:  return SystemZCC::LE;
585  case SystemZ::JNH:  return SystemZCC::NH;
586  case SystemZ::JNO:  return SystemZCC::NO;
587  }
588}
589
590SystemZCC::CondCodes
591SystemZInstrInfo::getOppositeCondition(SystemZCC::CondCodes CC) const {
592  switch (CC) {
593  default:
594    llvm_unreachable("Invalid condition!");
595  case SystemZCC::O:   return SystemZCC::NO;
596  case SystemZCC::H:   return SystemZCC::NH;
597  case SystemZCC::NLE: return SystemZCC::LE;
598  case SystemZCC::L:   return SystemZCC::NL;
599  case SystemZCC::NHE: return SystemZCC::HE;
600  case SystemZCC::LH:  return SystemZCC::NLH;
601  case SystemZCC::NE:  return SystemZCC::E;
602  case SystemZCC::E:   return SystemZCC::NE;
603  case SystemZCC::NLH: return SystemZCC::LH;
604  case SystemZCC::HE:  return SystemZCC::NHE;
605  case SystemZCC::NL:  return SystemZCC::L;
606  case SystemZCC::LE:  return SystemZCC::NLE;
607  case SystemZCC::NH:  return SystemZCC::H;
608  case SystemZCC::NO:  return SystemZCC::O;
609  }
610}
611
612const TargetInstrDesc&
613SystemZInstrInfo::getLongDispOpc(unsigned Opc) const {
614  switch (Opc) {
615  default:
616    llvm_unreachable("Don't have long disp version of this instruction");
617  case SystemZ::MOV32mr:   return get(SystemZ::MOV32mry);
618  case SystemZ::MOV32rm:   return get(SystemZ::MOV32rmy);
619  case SystemZ::MOVSX32rm16: return get(SystemZ::MOVSX32rm16y);
620  case SystemZ::MOV32m8r:  return get(SystemZ::MOV32m8ry);
621  case SystemZ::MOV32m16r: return get(SystemZ::MOV32m16ry);
622  case SystemZ::MOV64m8r:  return get(SystemZ::MOV64m8ry);
623  case SystemZ::MOV64m16r: return get(SystemZ::MOV64m16ry);
624  case SystemZ::MOV64m32r: return get(SystemZ::MOV64m32ry);
625  case SystemZ::MOV8mi:    return get(SystemZ::MOV8miy);
626  case SystemZ::MUL32rm:   return get(SystemZ::MUL32rmy);
627  case SystemZ::CMP32rm:   return get(SystemZ::CMP32rmy);
628  case SystemZ::UCMP32rm:  return get(SystemZ::UCMP32rmy);
629  case SystemZ::FMOV32mr:  return get(SystemZ::FMOV32mry);
630  case SystemZ::FMOV64mr:  return get(SystemZ::FMOV64mry);
631  case SystemZ::FMOV32rm:  return get(SystemZ::FMOV32rmy);
632  case SystemZ::FMOV64rm:  return get(SystemZ::FMOV64rmy);
633  case SystemZ::MOV64Pmr:  return get(SystemZ::MOV64Pmry);
634  case SystemZ::MOV64Prm:  return get(SystemZ::MOV64Prmy);
635  }
636}
637