SystemZInstrInfo.cpp revision ae46db85a946ef49f9febc3eca85b8cfad622ccb 
1//===- SystemZInstrInfo.cpp - SystemZ Instruction Information --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SystemZ implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SystemZ.h"
15#include "SystemZInstrBuilder.h"
16#include "SystemZInstrInfo.h"
17#include "SystemZMachineFunctionInfo.h"
18#include "SystemZTargetMachine.h"
19#include "SystemZGenInstrInfo.inc"
20#include "llvm/Function.h"
21#include "llvm/CodeGen/MachineFrameInfo.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/CodeGen/PseudoSourceValue.h"
25
26using namespace llvm;
27
28SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm)
29  : TargetInstrInfoImpl(SystemZInsts, array_lengthof(SystemZInsts)),
30    RI(tm, *this), TM(tm) {
31  // Fill the spill offsets map
32  static const unsigned SpillOffsTab[][2] = {
33    { SystemZ::R2D,  0x10 },
34    { SystemZ::R3D,  0x18 },
35    { SystemZ::R4D,  0x20 },
36    { SystemZ::R5D,  0x28 },
37    { SystemZ::R6D,  0x30 },
38    { SystemZ::R7D,  0x38 },
39    { SystemZ::R8D,  0x40 },
40    { SystemZ::R9D,  0x48 },
41    { SystemZ::R10D, 0x50 },
42    { SystemZ::R11D, 0x58 },
43    { SystemZ::R12D, 0x60 },
44    { SystemZ::R13D, 0x68 },
45    { SystemZ::R14D, 0x70 },
46    { SystemZ::R15D, 0x78 }
47  };
48
49  RegSpillOffsets.grow(SystemZ::NUM_TARGET_REGS);
50
51  for (unsigned i = 0, e = array_lengthof(SpillOffsTab); i != e; ++i)
52    RegSpillOffsets[SpillOffsTab[i][0]] = SpillOffsTab[i][1];
53}
54
55void SystemZInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
56                                          MachineBasicBlock::iterator MI,
57                                    unsigned SrcReg, bool isKill, int FrameIdx,
58                                    const TargetRegisterClass *RC) const {
59  DebugLoc DL = DebugLoc::getUnknownLoc();
60  if (MI != MBB.end()) DL = MI->getDebugLoc();
61
62  unsigned Opc = 0;
63  if (RC == &SystemZ::GR32RegClass ||
64      RC == &SystemZ::ADDR32RegClass)
65    Opc = SystemZ::MOV32mr;
66  else if (RC == &SystemZ::GR64RegClass ||
67           RC == &SystemZ::ADDR64RegClass) {
68    Opc = SystemZ::MOV64mr;
69  } else if (RC == &SystemZ::FP32RegClass) {
70    Opc = SystemZ::FMOV32mr;
71  } else if (RC == &SystemZ::FP64RegClass) {
72    Opc = SystemZ::FMOV64mr;
73  } else
74    assert(0 && "Unsupported regclass to store");
75
76  addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
77    .addReg(SrcReg, getKillRegState(isKill));
78}
79
80void SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
81                                           MachineBasicBlock::iterator MI,
82                                           unsigned DestReg, int FrameIdx,
83                                           const TargetRegisterClass *RC) const{
84  DebugLoc DL = DebugLoc::getUnknownLoc();
85  if (MI != MBB.end()) DL = MI->getDebugLoc();
86
87  unsigned Opc = 0;
88  if (RC == &SystemZ::GR32RegClass ||
89      RC == &SystemZ::ADDR32RegClass)
90    Opc = SystemZ::MOV32rm;
91  else if (RC == &SystemZ::GR64RegClass ||
92           RC == &SystemZ::ADDR64RegClass) {
93    Opc = SystemZ::MOV64rm;
94  } else if (RC == &SystemZ::FP32RegClass) {
95    Opc = SystemZ::FMOV32rm;
96  } else if (RC == &SystemZ::FP64RegClass) {
97    Opc = SystemZ::FMOV64rm;
98  } else
99    assert(0 && "Unsupported regclass to store");
100
101  addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
102}
103
104bool SystemZInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
105                                    MachineBasicBlock::iterator I,
106                                    unsigned DestReg, unsigned SrcReg,
107                                    const TargetRegisterClass *DestRC,
108                                    const TargetRegisterClass *SrcRC) const {
109  DebugLoc DL = DebugLoc::getUnknownLoc();
110  if (I != MBB.end()) DL = I->getDebugLoc();
111
112  // Determine if DstRC and SrcRC have a common superclass.
113  const TargetRegisterClass *CommonRC = DestRC;
114  if (DestRC == SrcRC)
115    /* Same regclass for source and dest */;
116  else if (CommonRC->hasSuperClass(SrcRC))
117    CommonRC = SrcRC;
118  else if (!CommonRC->hasSubClass(SrcRC))
119    CommonRC = 0;
120
121  if (CommonRC) {
122    if (CommonRC == &SystemZ::GR64RegClass ||
123        CommonRC == &SystemZ::ADDR64RegClass) {
124      BuildMI(MBB, I, DL, get(SystemZ::MOV64rr), DestReg).addReg(SrcReg);
125    } else if (CommonRC == &SystemZ::GR32RegClass ||
126               CommonRC == &SystemZ::ADDR32RegClass) {
127      BuildMI(MBB, I, DL, get(SystemZ::MOV32rr), DestReg).addReg(SrcReg);
128    } else if (CommonRC == &SystemZ::GR64PRegClass) {
129      BuildMI(MBB, I, DL, get(SystemZ::MOV64rrP), DestReg).addReg(SrcReg);
130    } else if (CommonRC == &SystemZ::GR128RegClass) {
131      BuildMI(MBB, I, DL, get(SystemZ::MOV128rr), DestReg).addReg(SrcReg);
132    } else if (CommonRC == &SystemZ::FP32RegClass) {
133      BuildMI(MBB, I, DL, get(SystemZ::FMOV32rr), DestReg).addReg(SrcReg);
134    } else if (CommonRC == &SystemZ::FP64RegClass) {
135      BuildMI(MBB, I, DL, get(SystemZ::FMOV64rr), DestReg).addReg(SrcReg);
136    } else {
137      return false;
138    }
139
140    return true;
141  }
142
143  if ((SrcRC == &SystemZ::GR64RegClass &&
144       DestRC == &SystemZ::ADDR64RegClass) ||
145      (DestRC == &SystemZ::GR64RegClass &&
146       SrcRC == &SystemZ::ADDR64RegClass)) {
147    BuildMI(MBB, I, DL, get(SystemZ::MOV64rr), DestReg).addReg(SrcReg);
148    return true;
149  } else if ((SrcRC == &SystemZ::GR32RegClass &&
150              DestRC == &SystemZ::ADDR32RegClass) ||
151             (DestRC == &SystemZ::GR32RegClass &&
152              SrcRC == &SystemZ::ADDR32RegClass)) {
153    BuildMI(MBB, I, DL, get(SystemZ::MOV32rr), DestReg).addReg(SrcReg);
154    return true;
155  }
156
157  return false;
158}
159
160bool
161SystemZInstrInfo::isMoveInstr(const MachineInstr& MI,
162                              unsigned &SrcReg, unsigned &DstReg,
163                              unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
164  switch (MI.getOpcode()) {
165  default:
166    return false;
167  case SystemZ::MOV32rr:
168  case SystemZ::MOV64rr:
169  case SystemZ::MOV64rrP:
170  case SystemZ::MOV128rr:
171  case SystemZ::FMOV32rr:
172  case SystemZ::FMOV64rr:
173    assert(MI.getNumOperands() >= 2 &&
174           MI.getOperand(0).isReg() &&
175           MI.getOperand(1).isReg() &&
176           "invalid register-register move instruction");
177    SrcReg = MI.getOperand(1).getReg();
178    DstReg = MI.getOperand(0).getReg();
179    SrcSubIdx = MI.getOperand(1).getSubReg();
180    DstSubIdx = MI.getOperand(0).getSubReg();
181    return true;
182  }
183}
184
185bool
186SystemZInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
187                                           MachineBasicBlock::iterator MI,
188                                const std::vector<CalleeSavedInfo> &CSI) const {
189  if (CSI.empty())
190    return false;
191
192  DebugLoc DL = DebugLoc::getUnknownLoc();
193  if (MI != MBB.end()) DL = MI->getDebugLoc();
194
195  MachineFunction &MF = *MBB.getParent();
196  SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>();
197  unsigned CalleeFrameSize = 0;
198
199  // Scan the callee-saved and find the bounds of register spill area.
200  unsigned LowReg = 0, HighReg = 0, StartOffset = -1U, EndOffset = 0;
201  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
202    unsigned Reg = CSI[i].getReg();
203    const TargetRegisterClass *RegClass = CSI[i].getRegClass();
204    if (RegClass != &SystemZ::FP64RegClass) {
205      unsigned Offset = RegSpillOffsets[Reg];
206      CalleeFrameSize += 8;
207      if (StartOffset > Offset) {
208        LowReg = Reg; StartOffset = Offset;
209      }
210      if (EndOffset < Offset) {
211        HighReg = Reg; EndOffset = RegSpillOffsets[Reg];
212      }
213    }
214  }
215
216  // Save information for epilogue inserter.
217  MFI->setCalleeSavedFrameSize(CalleeFrameSize);
218  MFI->setLowReg(LowReg); MFI->setHighReg(HighReg);
219
220  // Save GPRs
221  if (StartOffset) {
222    // Build a store instruction. Use STORE MULTIPLE instruction if there are many
223    // registers to store, otherwise - just STORE.
224    MachineInstrBuilder MIB =
225      BuildMI(MBB, MI, DL, get((LowReg == HighReg ?
226                                SystemZ::MOV64mr : SystemZ::MOV64mrm)));
227
228    // Add store operands.
229    MIB.addReg(SystemZ::R15D).addImm(StartOffset);
230    if (LowReg == HighReg)
231      MIB.addReg(0);
232    MIB.addReg(LowReg, RegState::Kill);
233    if (LowReg != HighReg)
234      MIB.addReg(HighReg, RegState::Kill);
235
236    // Do a second scan adding regs as being killed by instruction
237    for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
238      unsigned Reg = CSI[i].getReg();
239      // Add the callee-saved register as live-in. It's killed at the spill.
240      MBB.addLiveIn(Reg);
241      if (Reg != LowReg && Reg != HighReg)
242        MIB.addReg(Reg, RegState::ImplicitKill);
243    }
244  }
245
246  // Save FPRs
247  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
248    unsigned Reg = CSI[i].getReg();
249    const TargetRegisterClass *RegClass = CSI[i].getRegClass();
250    if (RegClass == &SystemZ::FP64RegClass) {
251      MBB.addLiveIn(Reg);
252      storeRegToStackSlot(MBB, MI, Reg, true, CSI[i].getFrameIdx(), RegClass);
253    }
254  }
255
256  return true;
257}
258
259bool
260SystemZInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
261                                             MachineBasicBlock::iterator MI,
262                                const std::vector<CalleeSavedInfo> &CSI) const {
263  if (CSI.empty())
264    return false;
265
266  DebugLoc DL = DebugLoc::getUnknownLoc();
267  if (MI != MBB.end()) DL = MI->getDebugLoc();
268
269  MachineFunction &MF = *MBB.getParent();
270  const TargetRegisterInfo *RegInfo= MF.getTarget().getRegisterInfo();
271  SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>();
272
273  // Restore FP registers
274  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
275    unsigned Reg = CSI[i].getReg();
276    const TargetRegisterClass *RegClass = CSI[i].getRegClass();
277    if (RegClass == &SystemZ::FP64RegClass)
278      loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass);
279  }
280
281  // Restore GP registers
282  unsigned LowReg = MFI->getLowReg(), HighReg = MFI->getHighReg();
283  unsigned StartOffset = RegSpillOffsets[LowReg];
284
285  if (StartOffset) {
286    // Build a load instruction. Use LOAD MULTIPLE instruction if there are many
287    // registers to load, otherwise - just LOAD.
288    MachineInstrBuilder MIB =
289      BuildMI(MBB, MI, DL, get((LowReg == HighReg ?
290                                SystemZ::MOV64rm : SystemZ::MOV64rmm)));
291    // Add store operands.
292    MIB.addReg(LowReg, RegState::Define);
293    if (LowReg != HighReg)
294      MIB.addReg(HighReg, RegState::Define);
295
296    MIB.addReg((RegInfo->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D));
297    MIB.addImm(StartOffset);
298    if (LowReg == HighReg)
299      MIB.addReg(0);
300
301    // Do a second scan adding regs as being defined by instruction
302    for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
303      unsigned Reg = CSI[i].getReg();
304      if (Reg != LowReg && Reg != HighReg)
305        MIB.addReg(Reg, RegState::ImplicitDefine);
306    }
307  }
308
309  return true;
310}
311
312bool SystemZInstrInfo::
313ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
314  assert(Cond.size() == 1 && "Invalid Xbranch condition!");
315
316  SystemZCC::CondCodes CC = static_cast<SystemZCC::CondCodes>(Cond[0].getImm());
317  Cond[0].setImm(getOppositeCondition(CC));
318  return false;
319}
320
321bool SystemZInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB)const{
322  if (MBB.empty()) return false;
323
324  switch (MBB.back().getOpcode()) {
325  case SystemZ::RET:   // Return.
326  case SystemZ::JMP:   // Uncond branch.
327  case SystemZ::JMPr:  // Indirect branch.
328    return true;
329  default: return false;
330  }
331}
332
333bool SystemZInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
334  const TargetInstrDesc &TID = MI->getDesc();
335  if (!TID.isTerminator()) return false;
336
337  // Conditional branch is a special case.
338  if (TID.isBranch() && !TID.isBarrier())
339    return true;
340  if (!TID.isPredicable())
341    return true;
342  return !isPredicated(MI);
343}
344
345bool SystemZInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
346                                     MachineBasicBlock *&TBB,
347                                     MachineBasicBlock *&FBB,
348                                     SmallVectorImpl<MachineOperand> &Cond,
349                                     bool AllowModify) const {
350  // Start from the bottom of the block and work up, examining the
351  // terminator instructions.
352  MachineBasicBlock::iterator I = MBB.end();
353  while (I != MBB.begin()) {
354    --I;
355    // Working from the bottom, when we see a non-terminator
356    // instruction, we're done.
357    if (!isUnpredicatedTerminator(I))
358      break;
359
360    // A terminator that isn't a branch can't easily be handled
361    // by this analysis.
362    if (!I->getDesc().isBranch())
363      return true;
364
365    // Handle unconditional branches.
366    if (I->getOpcode() == SystemZ::JMP) {
367      if (!AllowModify) {
368        TBB = I->getOperand(0).getMBB();
369        continue;
370      }
371
372      // If the block has any instructions after a JMP, delete them.
373      while (next(I) != MBB.end())
374        next(I)->eraseFromParent();
375      Cond.clear();
376      FBB = 0;
377
378      // Delete the JMP if it's equivalent to a fall-through.
379      if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
380        TBB = 0;
381        I->eraseFromParent();
382        I = MBB.end();
383        continue;
384      }
385
386      // TBB is used to indicate the unconditinal destination.
387      TBB = I->getOperand(0).getMBB();
388      continue;
389    }
390
391    // Handle conditional branches.
392    SystemZCC::CondCodes BranchCode = getCondFromBranchOpc(I->getOpcode());
393    if (BranchCode == SystemZCC::INVALID)
394      return true;  // Can't handle indirect branch.
395
396    // Working from the bottom, handle the first conditional branch.
397    if (Cond.empty()) {
398      FBB = TBB;
399      TBB = I->getOperand(0).getMBB();
400      Cond.push_back(MachineOperand::CreateImm(BranchCode));
401      continue;
402    }
403
404    // Handle subsequent conditional branches. Only handle the case where all
405    // conditional branches branch to the same destination.
406    assert(Cond.size() == 1);
407    assert(TBB);
408
409    // Only handle the case where all conditional branches branch to
410    // the same destination.
411    if (TBB != I->getOperand(0).getMBB())
412      return true;
413
414    SystemZCC::CondCodes OldBranchCode = (SystemZCC::CondCodes)Cond[0].getImm();
415    // If the conditions are the same, we can leave them alone.
416    if (OldBranchCode == BranchCode)
417      continue;
418
419    return true;
420  }
421
422  return false;
423}
424
425unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
426  MachineBasicBlock::iterator I = MBB.end();
427  unsigned Count = 0;
428
429  while (I != MBB.begin()) {
430    --I;
431    if (I->getOpcode() != SystemZ::JMP &&
432        getCondFromBranchOpc(I->getOpcode()) == SystemZCC::INVALID)
433      break;
434    // Remove the branch.
435    I->eraseFromParent();
436    I = MBB.end();
437    ++Count;
438  }
439
440  return Count;
441}
442
443unsigned
444SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
445                               MachineBasicBlock *FBB,
446                            const SmallVectorImpl<MachineOperand> &Cond) const {
447  // FIXME: this should probably have a DebugLoc operand
448  DebugLoc dl = DebugLoc::getUnknownLoc();
449  // Shouldn't be a fall through.
450  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
451  assert((Cond.size() == 1 || Cond.size() == 0) &&
452         "SystemZ branch conditions have one component!");
453
454  if (Cond.empty()) {
455    // Unconditional branch?
456    assert(!FBB && "Unconditional branch with multiple successors!");
457    BuildMI(&MBB, dl, get(SystemZ::JMP)).addMBB(TBB);
458    return 1;
459  }
460
461  // Conditional branch.
462  unsigned Count = 0;
463  SystemZCC::CondCodes CC = (SystemZCC::CondCodes)Cond[0].getImm();
464  BuildMI(&MBB, dl, getBrCond(CC)).addMBB(TBB);
465  ++Count;
466
467  if (FBB) {
468    // Two-way Conditional branch. Insert the second branch.
469    BuildMI(&MBB, dl, get(SystemZ::JMP)).addMBB(FBB);
470    ++Count;
471  }
472  return Count;
473}
474
475const TargetInstrDesc&
476SystemZInstrInfo::getBrCond(SystemZCC::CondCodes CC) const {
477  switch (CC) {
478  default:
479    assert(0 && "Unknown condition code!");
480  case SystemZCC::O:   return get(SystemZ::JO);
481  case SystemZCC::H:   return get(SystemZ::JH);
482  case SystemZCC::NLE: return get(SystemZ::JNLE);
483  case SystemZCC::L:   return get(SystemZ::JL);
484  case SystemZCC::NHE: return get(SystemZ::JNHE);
485  case SystemZCC::LH:  return get(SystemZ::JLH);
486  case SystemZCC::NE:  return get(SystemZ::JNE);
487  case SystemZCC::E:   return get(SystemZ::JE);
488  case SystemZCC::NLH: return get(SystemZ::JNLH);
489  case SystemZCC::HE:  return get(SystemZ::JHE);
490  case SystemZCC::NL:  return get(SystemZ::JNL);
491  case SystemZCC::LE:  return get(SystemZ::JLE);
492  case SystemZCC::NH:  return get(SystemZ::JNH);
493  case SystemZCC::NO:  return get(SystemZ::JNO);
494  }
495}
496
497SystemZCC::CondCodes
498SystemZInstrInfo::getCondFromBranchOpc(unsigned Opc) const {
499  switch (Opc) {
500  default:            return SystemZCC::INVALID;
501  case SystemZ::JO:   return SystemZCC::O;
502  case SystemZ::JH:   return SystemZCC::H;
503  case SystemZ::JNLE: return SystemZCC::NLE;
504  case SystemZ::JL:   return SystemZCC::L;
505  case SystemZ::JNHE: return SystemZCC::NHE;
506  case SystemZ::JLH:  return SystemZCC::LH;
507  case SystemZ::JNE:  return SystemZCC::NE;
508  case SystemZ::JE:   return SystemZCC::E;
509  case SystemZ::JNLH: return SystemZCC::NLH;
510  case SystemZ::JHE:  return SystemZCC::HE;
511  case SystemZ::JNL:  return SystemZCC::NL;
512  case SystemZ::JLE:  return SystemZCC::LE;
513  case SystemZ::JNH:  return SystemZCC::NH;
514  case SystemZ::JNO:  return SystemZCC::NO;
515  }
516}
517
518SystemZCC::CondCodes
519SystemZInstrInfo::getOppositeCondition(SystemZCC::CondCodes CC) const {
520  switch (CC) {
521  default:
522   assert(0 && "Invalid condition!");
523  case SystemZCC::O:   return SystemZCC::NO;
524  case SystemZCC::H:   return SystemZCC::NH;
525  case SystemZCC::NLE: return SystemZCC::LE;
526  case SystemZCC::L:   return SystemZCC::NL;
527  case SystemZCC::NHE: return SystemZCC::HE;
528  case SystemZCC::LH:  return SystemZCC::NLH;
529  case SystemZCC::NE:  return SystemZCC::E;
530  case SystemZCC::E:   return SystemZCC::NE;
531  case SystemZCC::NLH: return SystemZCC::LH;
532  case SystemZCC::HE:  return SystemZCC::NHE;
533  case SystemZCC::NL:  return SystemZCC::L;
534  case SystemZCC::LE:  return SystemZCC::NLE;
535  case SystemZCC::NH:  return SystemZCC::H;
536  case SystemZCC::NO:  return SystemZCC::O;
537  }
538}
539
540const TargetInstrDesc&
541SystemZInstrInfo::getLongDispOpc(unsigned Opc) const {
542  switch (Opc) {
543  case SystemZ::MOV32mr:   return get(SystemZ::MOV32mry);
544  case SystemZ::MOV32rm:   return get(SystemZ::MOV32rmy);
545  case SystemZ::MOVSX32rm16: return get(SystemZ::MOVSX32rm16y);
546  case SystemZ::MOV32m8r:  return get(SystemZ::MOV32m8ry);
547  case SystemZ::MOV32m16r: return get(SystemZ::MOV32m16ry);
548  case SystemZ::MOV64m8r:  return get(SystemZ::MOV64m8ry);
549  case SystemZ::MOV64m16r: return get(SystemZ::MOV64m16ry);
550  case SystemZ::MOV64m32r: return get(SystemZ::MOV64m32ry);
551  case SystemZ::MOV8mi:    return get(SystemZ::MOV8miy);
552  case SystemZ::MUL32rm:   return get(SystemZ::MUL32rmy);
553  case SystemZ::CMP32rm:   return get(SystemZ::CMP32rmy);
554  case SystemZ::UCMP32rm:  return get(SystemZ::UCMP32rmy);
555  case SystemZ::FMOV32mr:  return get(SystemZ::FMOV32mry);
556  case SystemZ::FMOV64mr:  return get(SystemZ::FMOV64mry);
557  case SystemZ::FMOV32rm:  return get(SystemZ::FMOV32rmy);
558  case SystemZ::FMOV64rm:  return get(SystemZ::FMOV64rmy);
559  default: return get(Opc);
560  }
561}
562
563