SystemZInstrInfo.cpp revision ba249e41f3ffa9e947b9173e3965385ec6324ffb 
1//===- SystemZInstrInfo.cpp - SystemZ Instruction Information --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SystemZ implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SystemZ.h"
15#include "SystemZInstrInfo.h"
16#include "SystemZMachineFunctionInfo.h"
17#include "SystemZTargetMachine.h"
18#include "SystemZGenInstrInfo.inc"
19#include "llvm/Function.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/CodeGen/PseudoSourceValue.h"
24
25using namespace llvm;
26
27SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm)
28  : TargetInstrInfoImpl(SystemZInsts, array_lengthof(SystemZInsts)),
29    RI(tm, *this), TM(tm) {}
30
31void SystemZInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
32                                          MachineBasicBlock::iterator MI,
33                                    unsigned SrcReg, bool isKill, int FrameIdx,
34                                    const TargetRegisterClass *RC) const {
35  assert(0 && "Cannot store this register to stack slot!");
36}
37
38void SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
39                                           MachineBasicBlock::iterator MI,
40                                           unsigned DestReg, int FrameIdx,
41                                           const TargetRegisterClass *RC) const{
42  assert(0 && "Cannot store this register to stack slot!");
43}
44
45bool SystemZInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
46                                    MachineBasicBlock::iterator I,
47                                    unsigned DestReg, unsigned SrcReg,
48                                    const TargetRegisterClass *DestRC,
49                                    const TargetRegisterClass *SrcRC) const {
50  DebugLoc DL = DebugLoc::getUnknownLoc();
51  if (I != MBB.end()) DL = I->getDebugLoc();
52
53  // Determine if DstRC and SrcRC have a common superclass.
54  const TargetRegisterClass *CommonRC = DestRC;
55  if (DestRC == SrcRC)
56    /* Same regclass for source and dest */;
57  else if (CommonRC->hasSuperClass(SrcRC))
58    CommonRC = SrcRC;
59  else if (!CommonRC->hasSubClass(SrcRC))
60    CommonRC = 0;
61
62  if (CommonRC) {
63    unsigned Opc;
64    if (CommonRC == &SystemZ::GR64RegClass ||
65        CommonRC == &SystemZ::ADDR64RegClass) {
66      Opc = SystemZ::MOV64rr;
67    } else if (CommonRC == &SystemZ::GR32RegClass ||
68               CommonRC == &SystemZ::ADDR32RegClass) {
69      Opc = SystemZ::MOV32rr;
70    } else {
71      return false;
72    }
73
74    BuildMI(MBB, I, DL, get(Opc), DestReg).addReg(SrcReg);
75    return true;
76  }
77
78  if ((SrcRC == &SystemZ::GR64RegClass &&
79       DestRC == &SystemZ::ADDR64RegClass) ||
80      (DestRC == &SystemZ::GR64RegClass &&
81       SrcRC == &SystemZ::ADDR64RegClass)) {
82    BuildMI(MBB, I, DL, get(SystemZ::MOV64rr), DestReg).addReg(SrcReg);
83    return true;
84  } else if ((SrcRC == &SystemZ::GR32RegClass &&
85              DestRC == &SystemZ::ADDR32RegClass) ||
86             (DestRC == &SystemZ::GR32RegClass &&
87              SrcRC == &SystemZ::ADDR32RegClass)) {
88    BuildMI(MBB, I, DL, get(SystemZ::MOV32rr), DestReg).addReg(SrcReg);
89    return true;
90  }
91
92  return false;
93}
94
95bool
96SystemZInstrInfo::isMoveInstr(const MachineInstr& MI,
97                              unsigned &SrcReg, unsigned &DstReg,
98                              unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
99  SrcSubIdx = DstSubIdx = 0; // No sub-registers yet.
100
101  switch (MI.getOpcode()) {
102  default:
103    return false;
104  case SystemZ::MOV32rr:
105  case SystemZ::MOV64rr:
106    assert(MI.getNumOperands() >= 2 &&
107           MI.getOperand(0).isReg() &&
108           MI.getOperand(1).isReg() &&
109           "invalid register-register move instruction");
110    SrcReg = MI.getOperand(1).getReg();
111    DstReg = MI.getOperand(0).getReg();
112    return true;
113  }
114}
115
116bool
117SystemZInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
118                                           MachineBasicBlock::iterator MI,
119                                const std::vector<CalleeSavedInfo> &CSI) const {
120  if (CSI.empty())
121    return false;
122
123  MachineFunction &MF = *MBB.getParent();
124  SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>();
125  MFI->setCalleeSavedFrameSize(CSI.size() * 8);
126
127  return true;
128}
129
130bool
131SystemZInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
132                                             MachineBasicBlock::iterator MI,
133                                const std::vector<CalleeSavedInfo> &CSI) const {
134  return true;
135}
136
137unsigned
138SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
139                              MachineBasicBlock *FBB,
140                            const SmallVectorImpl<MachineOperand> &Cond) const {
141  assert(0 && "Implement branches!");
142
143  return 0;
144}
145