SystemZInstrInfo.h revision 0416e3c599c22dc656a1115ac983116ad0b2d9da 
1//===-- SystemZInstrInfo.h - SystemZ instruction information ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SystemZ implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_TARGET_SYSTEMZINSTRINFO_H
15#define LLVM_TARGET_SYSTEMZINSTRINFO_H
16
17#include "SystemZ.h"
18#include "SystemZRegisterInfo.h"
19#include "llvm/Target/TargetInstrInfo.h"
20
21#define GET_INSTRINFO_HEADER
22#include "SystemZGenInstrInfo.inc"
23
24namespace llvm {
25
26class SystemZTargetMachine;
27
28namespace SystemZII {
29  enum {
30    // See comments in SystemZInstrFormats.td.
31    SimpleBDXLoad  = (1 << 0),
32    SimpleBDXStore = (1 << 1),
33    Has20BitOffset = (1 << 2),
34    HasIndex       = (1 << 3),
35    Is128Bit       = (1 << 4),
36    AccessSizeMask = (31 << 5),
37    AccessSizeShift = 5
38  };
39  static inline unsigned getAccessSize(unsigned int Flags) {
40    return (Flags & AccessSizeMask) >> AccessSizeShift;
41  }
42
43  // SystemZ MachineOperand target flags.
44  enum {
45    // Masks out the bits for the access model.
46    MO_SYMBOL_MODIFIER = (1 << 0),
47
48    // @GOT (aka @GOTENT)
49    MO_GOT = (1 << 0)
50  };
51  // Classifies a branch.
52  enum BranchType {
53    // An instruction that branches on the current value of CC.
54    BranchNormal,
55
56    // An instruction that peforms a 32-bit signed comparison and branches
57    // on the result.
58    BranchC,
59
60    // An instruction that peforms a 64-bit signed comparison and branches
61    // on the result.
62    BranchCG
63  };
64  // Information about a branch instruction.
65  struct Branch {
66    // The type of the branch.
67    BranchType Type;
68
69    // CCMASK_<N> is set if the branch should be taken when CC == N.
70    unsigned CCMask;
71
72    // The target of the branch.
73    const MachineOperand *Target;
74
75    Branch(BranchType type, unsigned ccMask, const MachineOperand *target)
76      : Type(type), CCMask(ccMask), Target(target) {}
77  };
78}
79
80class SystemZInstrInfo : public SystemZGenInstrInfo {
81  const SystemZRegisterInfo RI;
82  SystemZTargetMachine &TM;
83
84  void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
85  void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const;
86
87public:
88  explicit SystemZInstrInfo(SystemZTargetMachine &TM);
89
90  // Override TargetInstrInfo.
91  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
92                                       int &FrameIndex) const LLVM_OVERRIDE;
93  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
94                                      int &FrameIndex) const LLVM_OVERRIDE;
95  virtual bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex,
96                               int &SrcFrameIndex) const LLVM_OVERRIDE;
97  virtual bool AnalyzeBranch(MachineBasicBlock &MBB,
98                             MachineBasicBlock *&TBB,
99                             MachineBasicBlock *&FBB,
100                             SmallVectorImpl<MachineOperand> &Cond,
101                             bool AllowModify) const LLVM_OVERRIDE;
102  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const LLVM_OVERRIDE;
103  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
104                                MachineBasicBlock *FBB,
105                                const SmallVectorImpl<MachineOperand> &Cond,
106                                DebugLoc DL) const LLVM_OVERRIDE;
107  virtual bool isPredicable(MachineInstr *MI) const LLVM_OVERRIDE;
108  virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
109                                   unsigned ExtraPredCycles,
110                                   const BranchProbability &Probability) const
111    LLVM_OVERRIDE;
112  virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
113                                   unsigned NumCyclesT,
114                                   unsigned ExtraPredCyclesT,
115                                   MachineBasicBlock &FMBB,
116                                   unsigned NumCyclesF,
117                                   unsigned ExtraPredCyclesF,
118                                   const BranchProbability &Probability) const
119    LLVM_OVERRIDE;
120  virtual bool
121    PredicateInstruction(MachineInstr *MI,
122                         const SmallVectorImpl<MachineOperand> &Pred) const
123    LLVM_OVERRIDE;
124  virtual void copyPhysReg(MachineBasicBlock &MBB,
125                           MachineBasicBlock::iterator MBBI, DebugLoc DL,
126                           unsigned DestReg, unsigned SrcReg,
127                           bool KillSrc) const LLVM_OVERRIDE;
128  virtual void
129    storeRegToStackSlot(MachineBasicBlock &MBB,
130                        MachineBasicBlock::iterator MBBI,
131                        unsigned SrcReg, bool isKill, int FrameIndex,
132                        const TargetRegisterClass *RC,
133                        const TargetRegisterInfo *TRI) const LLVM_OVERRIDE;
134  virtual void
135    loadRegFromStackSlot(MachineBasicBlock &MBB,
136                         MachineBasicBlock::iterator MBBI,
137                         unsigned DestReg, int FrameIdx,
138                         const TargetRegisterClass *RC,
139                         const TargetRegisterInfo *TRI) const LLVM_OVERRIDE;
140  virtual MachineInstr *
141    convertToThreeAddress(MachineFunction::iterator &MFI,
142                          MachineBasicBlock::iterator &MBBI,
143                          LiveVariables *LV) const;
144  virtual MachineInstr *
145    foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
146                          const SmallVectorImpl<unsigned> &Ops,
147                          int FrameIndex) const;
148  virtual MachineInstr *
149    foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI,
150                          const SmallVectorImpl<unsigned> &Ops,
151                          MachineInstr* LoadMI) const;
152  virtual bool
153    expandPostRAPseudo(MachineBasicBlock::iterator MBBI) const LLVM_OVERRIDE;
154  virtual bool
155    ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
156    LLVM_OVERRIDE;
157
158  // Return the SystemZRegisterInfo, which this class owns.
159  const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
160
161  // Return the size in bytes of MI.
162  uint64_t getInstSizeInBytes(const MachineInstr *MI) const;
163
164  // Return true if MI is a conditional or unconditional branch.
165  // When returning true, set Cond to the mask of condition-code
166  // values on which the instruction will branch, and set Target
167  // to the operand that contains the branch target.  This target
168  // can be a register or a basic block.
169  SystemZII::Branch getBranchInfo(const MachineInstr *MI) const;
170
171  // Get the load and store opcodes for a given register class.
172  void getLoadStoreOpcodes(const TargetRegisterClass *RC,
173                           unsigned &LoadOpcode, unsigned &StoreOpcode) const;
174
175  // Opcode is the opcode of an instruction that has an address operand,
176  // and the caller wants to perform that instruction's operation on an
177  // address that has displacement Offset.  Return the opcode of a suitable
178  // instruction (which might be Opcode itself) or 0 if no such instruction
179  // exists.
180  unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const;
181
182  // Return true if ROTATE AND ... SELECTED BITS can be used to select bits
183  // Mask of the R2 operand, given that only the low BitSize bits of Mask are
184  // significant.  Set Start and End to the I3 and I4 operands if so.
185  bool isRxSBGMask(uint64_t Mask, unsigned BitSize,
186                   unsigned &Start, unsigned &End) const;
187
188  // If Opcode is a COMPARE opcode for which an associated COMPARE AND
189  // BRANCH exists, return the opcode for the latter, otherwise return 0.
190  // MI, if nonnull, is the compare instruction.
191  unsigned getCompareAndBranch(unsigned Opcode,
192                               const MachineInstr *MI = 0) const;
193
194  // Emit code before MBBI in MI to move immediate value Value into
195  // physical register Reg.
196  void loadImmediate(MachineBasicBlock &MBB,
197                     MachineBasicBlock::iterator MBBI,
198                     unsigned Reg, uint64_t Value) const;
199};
200} // end namespace llvm
201
202#endif
203