SystemZInstrInfo.h revision 06c3c9a9e1cc313d911e939e3e994feaf43cc3a7 
1//===-- SystemZInstrInfo.h - SystemZ instruction information ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SystemZ implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_TARGET_SYSTEMZINSTRINFO_H
15#define LLVM_TARGET_SYSTEMZINSTRINFO_H
16
17#include "SystemZ.h"
18#include "SystemZRegisterInfo.h"
19#include "llvm/Target/TargetInstrInfo.h"
20
21#define GET_INSTRINFO_HEADER
22#include "SystemZGenInstrInfo.inc"
23
24namespace llvm {
25
26class SystemZTargetMachine;
27
28namespace SystemZII {
29  enum {
30    // See comments in SystemZInstrFormats.td.
31    SimpleBDXLoad  = (1 << 0),
32    SimpleBDXStore = (1 << 1),
33    Has20BitOffset = (1 << 2),
34    HasIndex       = (1 << 3),
35    Is128Bit       = (1 << 4)
36  };
37  // SystemZ MachineOperand target flags.
38  enum {
39    // Masks out the bits for the access model.
40    MO_SYMBOL_MODIFIER = (1 << 0),
41
42    // @GOT (aka @GOTENT)
43    MO_GOT = (1 << 0)
44  };
45  // Information about a branch instruction.
46  struct Branch {
47    // CCMASK_<N> is set if the branch should be taken when CC == N.
48    unsigned CCMask;
49
50    // The target of the branch.
51    const MachineOperand *Target;
52
53    Branch(unsigned ccMask, const MachineOperand *target)
54      : CCMask(ccMask), Target(target) {}
55  };
56}
57
58class SystemZInstrInfo : public SystemZGenInstrInfo {
59  const SystemZRegisterInfo RI;
60
61  void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
62  void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const;
63
64public:
65  explicit SystemZInstrInfo(SystemZTargetMachine &TM);
66
67  // Override TargetInstrInfo.
68  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
69                                       int &FrameIndex) const LLVM_OVERRIDE;
70  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
71                                      int &FrameIndex) const LLVM_OVERRIDE;
72  virtual bool AnalyzeBranch(MachineBasicBlock &MBB,
73                             MachineBasicBlock *&TBB,
74                             MachineBasicBlock *&FBB,
75                             SmallVectorImpl<MachineOperand> &Cond,
76                             bool AllowModify) const LLVM_OVERRIDE;
77  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const LLVM_OVERRIDE;
78  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
79                                MachineBasicBlock *FBB,
80                                const SmallVectorImpl<MachineOperand> &Cond,
81                                DebugLoc DL) const LLVM_OVERRIDE;
82  virtual void copyPhysReg(MachineBasicBlock &MBB,
83                           MachineBasicBlock::iterator MBBI, DebugLoc DL,
84                           unsigned DestReg, unsigned SrcReg,
85                           bool KillSrc) const LLVM_OVERRIDE;
86  virtual void
87    storeRegToStackSlot(MachineBasicBlock &MBB,
88                        MachineBasicBlock::iterator MBBI,
89                        unsigned SrcReg, bool isKill, int FrameIndex,
90                        const TargetRegisterClass *RC,
91                        const TargetRegisterInfo *TRI) const LLVM_OVERRIDE;
92  virtual void
93    loadRegFromStackSlot(MachineBasicBlock &MBB,
94                         MachineBasicBlock::iterator MBBI,
95                         unsigned DestReg, int FrameIdx,
96                         const TargetRegisterClass *RC,
97                         const TargetRegisterInfo *TRI) const LLVM_OVERRIDE;
98  virtual bool
99    expandPostRAPseudo(MachineBasicBlock::iterator MBBI) const LLVM_OVERRIDE;
100  virtual bool
101    ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
102    LLVM_OVERRIDE;
103
104  // Return the SystemZRegisterInfo, which this class owns.
105  const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
106
107  // Return the size in bytes of MI.
108  uint64_t getInstSizeInBytes(const MachineInstr *MI) const;
109
110  // Return true if MI is a conditional or unconditional branch.
111  // When returning true, set Cond to the mask of condition-code
112  // values on which the instruction will branch, and set Target
113  // to the operand that contains the branch target.  This target
114  // can be a register or a basic block.
115  SystemZII::Branch getBranchInfo(const MachineInstr *MI) const;
116
117  // Get the load and store opcodes for a given register class.
118  void getLoadStoreOpcodes(const TargetRegisterClass *RC,
119                           unsigned &LoadOpcode, unsigned &StoreOpcode) const;
120
121  // Opcode is the opcode of an instruction that has an address operand,
122  // and the caller wants to perform that instruction's operation on an
123  // address that has displacement Offset.  Return the opcode of a suitable
124  // instruction (which might be Opcode itself) or 0 if no such instruction
125  // exists.
126  unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const;
127
128  // Emit code before MBBI in MI to move immediate value Value into
129  // physical register Reg.
130  void loadImmediate(MachineBasicBlock &MBB,
131                     MachineBasicBlock::iterator MBBI,
132                     unsigned Reg, uint64_t Value) const;
133};
134} // end namespace llvm
135
136#endif
137