SystemZInstrInfo.h revision 78e6e009223a38739797629ca2d217acf86dda93 
1//===- SystemZInstrInfo.h - SystemZ Instruction Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SystemZ implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_TARGET_SYSTEMZINSTRINFO_H
15#define LLVM_TARGET_SYSTEMZINSTRINFO_H
16
17#include "SystemZ.h"
18#include "SystemZRegisterInfo.h"
19#include "llvm/ADT/IndexedMap.h"
20#include "llvm/Target/TargetInstrInfo.h"
21
22namespace llvm {
23
24class SystemZTargetMachine;
25
26/// SystemZII - This namespace holds all of the target specific flags that
27/// instruction info tracks.
28///
29namespace SystemZII {
30  enum {
31    //===------------------------------------------------------------------===//
32    // SystemZ Specific MachineOperand flags.
33
34    MO_NO_FLAG = 0,
35
36    /// MO_GOTENT - On a symbol operand this indicates that the immediate is
37    /// the offset to the location of the symbol name from the base of the GOT.
38    ///
39    ///    SYMBOL_LABEL @GOTENT
40    MO_GOTENT = 1,
41
42    /// MO_PLT - On a symbol operand this indicates that the immediate is
43    /// offset to the PLT entry of symbol name from the current code location.
44    ///
45    ///    SYMBOL_LABEL @PLT
46    MO_PLT = 2
47  };
48}
49
50class SystemZInstrInfo : public TargetInstrInfoImpl {
51  const SystemZRegisterInfo RI;
52  SystemZTargetMachine &TM;
53  IndexedMap<unsigned> RegSpillOffsets;
54public:
55  explicit SystemZInstrInfo(SystemZTargetMachine &TM);
56
57  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
58  /// such, whenever a client has an instance of instruction info, it should
59  /// always be able to get register info as well (through this method).
60  ///
61  virtual const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
62
63  virtual void copyPhysReg(MachineBasicBlock &MBB,
64                           MachineBasicBlock::iterator I, DebugLoc DL,
65                           unsigned DestReg, unsigned SrcReg,
66                           bool KillSrc) const;
67
68  unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
69  unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;
70
71  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
72                                   MachineBasicBlock::iterator MI,
73                                   unsigned SrcReg, bool isKill,
74                                   int FrameIndex,
75                                   const TargetRegisterClass *RC,
76                                   const TargetRegisterInfo *TRI) const;
77  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
78                                    MachineBasicBlock::iterator MI,
79                                    unsigned DestReg, int FrameIdx,
80                                    const TargetRegisterClass *RC,
81                                    const TargetRegisterInfo *TRI) const;
82
83  virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
84                                         MachineBasicBlock::iterator MI,
85                                        const std::vector<CalleeSavedInfo> &CSI,
86                                         const TargetRegisterInfo *TRI) const;
87  virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
88                                           MachineBasicBlock::iterator MI,
89                                        const std::vector<CalleeSavedInfo> &CSI,
90                                           const TargetRegisterInfo *TRI) const;
91
92  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
93  virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
94  virtual bool AnalyzeBranch(MachineBasicBlock &MBB,
95                             MachineBasicBlock *&TBB,
96                             MachineBasicBlock *&FBB,
97                             SmallVectorImpl<MachineOperand> &Cond,
98                             bool AllowModify) const;
99  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
100                                MachineBasicBlock *FBB,
101                                const SmallVectorImpl<MachineOperand> &Cond,
102                                DebugLoc DL) const;
103  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
104
105  SystemZCC::CondCodes getOppositeCondition(SystemZCC::CondCodes CC) const;
106  SystemZCC::CondCodes getCondFromBranchOpc(unsigned Opc) const;
107  const TargetInstrDesc& getBrCond(SystemZCC::CondCodes CC) const;
108  const TargetInstrDesc& getLongDispOpc(unsigned Opc) const;
109
110  const TargetInstrDesc& getMemoryInstr(unsigned Opc, int64_t Offset = 0) const {
111    if (Offset < 0 || Offset >= 4096)
112      return getLongDispOpc(Opc);
113    else
114      return get(Opc);
115  }
116};
117
118}
119
120#endif
121