SystemZInstrInfo.h revision 9b05c709c65ba05645853ca49bc2a1ea8b554f37 
1//===-- SystemZInstrInfo.h - SystemZ instruction information ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SystemZ implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_TARGET_SYSTEMZINSTRINFO_H
15#define LLVM_TARGET_SYSTEMZINSTRINFO_H
16
17#include "SystemZ.h"
18#include "SystemZRegisterInfo.h"
19#include "llvm/Target/TargetInstrInfo.h"
20
21#define GET_INSTRINFO_HEADER
22#include "SystemZGenInstrInfo.inc"
23
24namespace llvm {
25
26class SystemZTargetMachine;
27
28namespace SystemZII {
29  enum {
30    // See comments in SystemZInstrFormats.td.
31    SimpleBDXLoad   = (1 << 0),
32    SimpleBDXStore  = (1 << 1),
33    Has20BitOffset  = (1 << 2),
34    HasIndex        = (1 << 3),
35    Is128Bit        = (1 << 4),
36    AccessSizeMask  = (31 << 5),
37    AccessSizeShift = 5,
38    CCValuesMask    = (15 << 10),
39    CCValuesShift   = 10,
40    CCHasZero       = (1 << 14),
41    CCHasOrder      = (1 << 15),
42    CCMaskFirst     = (1 << 16),
43    CCMaskLast      = (1 << 17),
44    IsLogical       = (1 << 18)
45  };
46  static inline unsigned getAccessSize(unsigned int Flags) {
47    return (Flags & AccessSizeMask) >> AccessSizeShift;
48  }
49  static inline unsigned getCCValues(unsigned int Flags) {
50    return (Flags & CCValuesMask) >> CCValuesShift;
51  }
52
53  // SystemZ MachineOperand target flags.
54  enum {
55    // Masks out the bits for the access model.
56    MO_SYMBOL_MODIFIER = (1 << 0),
57
58    // @GOT (aka @GOTENT)
59    MO_GOT = (1 << 0)
60  };
61  // Classifies a branch.
62  enum BranchType {
63    // An instruction that branches on the current value of CC.
64    BranchNormal,
65
66    // An instruction that peforms a 32-bit signed comparison and branches
67    // on the result.
68    BranchC,
69
70    // An instruction that peforms a 64-bit signed comparison and branches
71    // on the result.
72    BranchCG
73  };
74  // Information about a branch instruction.
75  struct Branch {
76    // The type of the branch.
77    BranchType Type;
78
79    // CCMASK_<N> is set if CC might be equal to N.
80    unsigned CCValid;
81
82    // CCMASK_<N> is set if the branch should be taken when CC == N.
83    unsigned CCMask;
84
85    // The target of the branch.
86    const MachineOperand *Target;
87
88    Branch(BranchType type, unsigned ccValid, unsigned ccMask,
89           const MachineOperand *target)
90      : Type(type), CCValid(ccValid), CCMask(ccMask), Target(target) {}
91  };
92}
93
94class SystemZInstrInfo : public SystemZGenInstrInfo {
95  const SystemZRegisterInfo RI;
96  SystemZTargetMachine &TM;
97
98  void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
99  void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const;
100
101public:
102  explicit SystemZInstrInfo(SystemZTargetMachine &TM);
103
104  // Override TargetInstrInfo.
105  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
106                                       int &FrameIndex) const LLVM_OVERRIDE;
107  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
108                                      int &FrameIndex) const LLVM_OVERRIDE;
109  virtual bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex,
110                               int &SrcFrameIndex) const LLVM_OVERRIDE;
111  virtual bool AnalyzeBranch(MachineBasicBlock &MBB,
112                             MachineBasicBlock *&TBB,
113                             MachineBasicBlock *&FBB,
114                             SmallVectorImpl<MachineOperand> &Cond,
115                             bool AllowModify) const LLVM_OVERRIDE;
116  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const LLVM_OVERRIDE;
117  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
118                                MachineBasicBlock *FBB,
119                                const SmallVectorImpl<MachineOperand> &Cond,
120                                DebugLoc DL) const LLVM_OVERRIDE;
121  virtual bool isPredicable(MachineInstr *MI) const LLVM_OVERRIDE;
122  virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
123                                   unsigned ExtraPredCycles,
124                                   const BranchProbability &Probability) const
125    LLVM_OVERRIDE;
126  virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
127                                   unsigned NumCyclesT,
128                                   unsigned ExtraPredCyclesT,
129                                   MachineBasicBlock &FMBB,
130                                   unsigned NumCyclesF,
131                                   unsigned ExtraPredCyclesF,
132                                   const BranchProbability &Probability) const
133    LLVM_OVERRIDE;
134  virtual bool
135    PredicateInstruction(MachineInstr *MI,
136                         const SmallVectorImpl<MachineOperand> &Pred) const
137    LLVM_OVERRIDE;
138  virtual void copyPhysReg(MachineBasicBlock &MBB,
139                           MachineBasicBlock::iterator MBBI, DebugLoc DL,
140                           unsigned DestReg, unsigned SrcReg,
141                           bool KillSrc) const LLVM_OVERRIDE;
142  virtual void
143    storeRegToStackSlot(MachineBasicBlock &MBB,
144                        MachineBasicBlock::iterator MBBI,
145                        unsigned SrcReg, bool isKill, int FrameIndex,
146                        const TargetRegisterClass *RC,
147                        const TargetRegisterInfo *TRI) const LLVM_OVERRIDE;
148  virtual void
149    loadRegFromStackSlot(MachineBasicBlock &MBB,
150                         MachineBasicBlock::iterator MBBI,
151                         unsigned DestReg, int FrameIdx,
152                         const TargetRegisterClass *RC,
153                         const TargetRegisterInfo *TRI) const LLVM_OVERRIDE;
154  virtual MachineInstr *
155    convertToThreeAddress(MachineFunction::iterator &MFI,
156                          MachineBasicBlock::iterator &MBBI,
157                          LiveVariables *LV) const;
158  virtual MachineInstr *
159    foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
160                          const SmallVectorImpl<unsigned> &Ops,
161                          int FrameIndex) const;
162  virtual MachineInstr *
163    foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI,
164                          const SmallVectorImpl<unsigned> &Ops,
165                          MachineInstr* LoadMI) const;
166  virtual bool
167    expandPostRAPseudo(MachineBasicBlock::iterator MBBI) const LLVM_OVERRIDE;
168  virtual bool
169    ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
170    LLVM_OVERRIDE;
171
172  // Return the SystemZRegisterInfo, which this class owns.
173  const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
174
175  // Return the size in bytes of MI.
176  uint64_t getInstSizeInBytes(const MachineInstr *MI) const;
177
178  // Return true if MI is a conditional or unconditional branch.
179  // When returning true, set Cond to the mask of condition-code
180  // values on which the instruction will branch, and set Target
181  // to the operand that contains the branch target.  This target
182  // can be a register or a basic block.
183  SystemZII::Branch getBranchInfo(const MachineInstr *MI) const;
184
185  // Get the load and store opcodes for a given register class.
186  void getLoadStoreOpcodes(const TargetRegisterClass *RC,
187                           unsigned &LoadOpcode, unsigned &StoreOpcode) const;
188
189  // Opcode is the opcode of an instruction that has an address operand,
190  // and the caller wants to perform that instruction's operation on an
191  // address that has displacement Offset.  Return the opcode of a suitable
192  // instruction (which might be Opcode itself) or 0 if no such instruction
193  // exists.
194  unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const;
195
196  // If Opcode is a load instruction that has a LOAD AND TEST form,
197  // return the opcode for the testing form, otherwise return 0.
198  unsigned getLoadAndTest(unsigned Opcode) const;
199
200  // Return true if ROTATE AND ... SELECTED BITS can be used to select bits
201  // Mask of the R2 operand, given that only the low BitSize bits of Mask are
202  // significant.  Set Start and End to the I3 and I4 operands if so.
203  bool isRxSBGMask(uint64_t Mask, unsigned BitSize,
204                   unsigned &Start, unsigned &End) const;
205
206  // If Opcode is a COMPARE opcode for which an associated COMPARE AND
207  // BRANCH exists, return the opcode for the latter, otherwise return 0.
208  // MI, if nonnull, is the compare instruction.
209  unsigned getCompareAndBranch(unsigned Opcode,
210                               const MachineInstr *MI = 0) const;
211
212  // Emit code before MBBI in MI to move immediate value Value into
213  // physical register Reg.
214  void loadImmediate(MachineBasicBlock &MBB,
215                     MachineBasicBlock::iterator MBBI,
216                     unsigned Reg, uint64_t Value) const;
217};
218} // end namespace llvm
219
220#endif
221