1//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// Stack allocation
12//===----------------------------------------------------------------------===//
13
14def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
15                              [(callseq_start timm:$amt)]>;
16def ADJCALLSTACKUP   : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
17                              [(callseq_end timm:$amt1, timm:$amt2)]>;
18
19let neverHasSideEffects = 1 in {
20  // Takes as input the value of the stack pointer after a dynamic allocation
21  // has been made.  Sets the output to the address of the dynamically-
22  // allocated area itself, skipping the outgoing arguments.
23  //
24  // This expands to an LA or LAY instruction.  We restrict the offset
25  // to the range of LA and keep the LAY range in reserve for when
26  // the size of the outgoing arguments is added.
27  def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src),
28                           [(set GR64:$dst, dynalloc12only:$src)]>;
29}
30
31//===----------------------------------------------------------------------===//
32// Control flow instructions
33//===----------------------------------------------------------------------===//
34
35// A return instruction (br %r14).
36let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
37  def Return : Alias<2, (outs), (ins), [(z_retflag)]>;
38
39// Unconditional branches.  R1 is the condition-code mask (all 1s).
40let isBranch = 1, isTerminator = 1, isBarrier = 1, R1 = 15 in {
41  let isIndirectBranch = 1 in
42    def BR : InstRR<0x07, (outs), (ins ADDR64:$R2),
43                    "br\t$R2", [(brind ADDR64:$R2)]>;
44
45  // An assembler extended mnemonic for BRC.
46  def J : InstRI<0xA74, (outs), (ins brtarget16:$I2), "j\t$I2",
47                 [(br bb:$I2)]>;
48
49  // An assembler extended mnemonic for BRCL.  (The extension is "G"
50  // rather than "L" because "JL" is "Jump if Less".)
51  def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2), "jg\t$I2", []>;
52}
53
54// Conditional branches.  It's easier for LLVM to handle these branches
55// in their raw BRC/BRCL form, with the 4-bit condition-code mask being
56// the first operand.  It seems friendlier to use mnemonic forms like
57// JE and JLH when writing out the assembly though.
58let isBranch = 1, isTerminator = 1, Uses = [CC] in {
59  let isCodeGenOnly = 1, CCMaskFirst = 1 in {
60    def BRC : InstRI<0xA74, (outs), (ins cond4:$valid, cond4:$R1,
61                                         brtarget16:$I2), "j$R1\t$I2",
62                     [(z_br_ccmask cond4:$valid, cond4:$R1, bb:$I2)]>;
63    def BRCL : InstRIL<0xC04, (outs), (ins cond4:$valid, cond4:$R1,
64                                           brtarget32:$I2), "jg$R1\t$I2", []>;
65  }
66  def AsmBRC : InstRI<0xA74, (outs), (ins imm32zx4:$R1, brtarget16:$I2),
67                      "brc\t$R1, $I2", []>;
68  def AsmBRCL : InstRIL<0xC04, (outs), (ins imm32zx4:$R1, brtarget32:$I2),
69                        "brcl\t$R1, $I2", []>;
70  def AsmBCR : InstRR<0x07, (outs), (ins imm32zx4:$R1, GR64:$R2),
71                      "bcr\t$R1, $R2", []>;
72}
73
74// Fused compare-and-branch instructions.  As for normal branches,
75// we handle these instructions internally in their raw CRJ-like form,
76// but use assembly macros like CRJE when writing them out.
77//
78// These instructions do not use or clobber the condition codes.
79// We nevertheless pretend that they clobber CC, so that we can lower
80// them to separate comparisons and BRCLs if the branch ends up being
81// out of range.
82multiclass CompareBranches<Operand ccmask, string pos1, string pos2> {
83  let isBranch = 1, isTerminator = 1, Defs = [CC] in {
84    def RJ  : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
85                                            brtarget16:$RI4),
86                       "crj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
87    def GRJ : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
88                                            brtarget16:$RI4),
89                       "cgrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
90    def IJ  : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2, ccmask:$M3,
91                                            brtarget16:$RI4),
92                       "cij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
93    def GIJ : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2, ccmask:$M3,
94                                            brtarget16:$RI4),
95                       "cgij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
96    def LRJ  : InstRIEb<0xEC77, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
97                                             brtarget16:$RI4),
98                        "clrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
99    def LGRJ : InstRIEb<0xEC65, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
100                                             brtarget16:$RI4),
101                        "clgrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
102    def LIJ  : InstRIEc<0xEC7F, (outs), (ins GR32:$R1, imm32zx8:$I2, ccmask:$M3,
103                                             brtarget16:$RI4),
104                        "clij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
105    def LGIJ : InstRIEc<0xEC7D, (outs), (ins GR64:$R1, imm64zx8:$I2, ccmask:$M3,
106                                             brtarget16:$RI4),
107                        "clgij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
108  }
109}
110let isCodeGenOnly = 1 in
111  defm C : CompareBranches<cond4, "$M3", "">;
112defm AsmC : CompareBranches<imm32zx4, "", "$M3, ">;
113
114// Define AsmParser mnemonics for each general condition-code mask
115// (integer or floating-point)
116multiclass CondExtendedMnemonic<bits<4> ccmask, string name> {
117  let R1 = ccmask in {
118    def J : InstRI<0xA74, (outs), (ins brtarget16:$I2),
119                   "j"##name##"\t$I2", []>;
120    def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2),
121                     "jg"##name##"\t$I2", []>;
122    def BR : InstRR<0x07, (outs), (ins ADDR64:$R2), "b"##name##"r\t$R2", []>;
123  }
124  def LOCR  : FixedCondUnaryRRF<"locr"##name,  0xB9F2, GR32, GR32, ccmask>;
125  def LOCGR : FixedCondUnaryRRF<"locgr"##name, 0xB9E2, GR64, GR64, ccmask>;
126  def LOC   : FixedCondUnaryRSY<"loc"##name,   0xEBF2, GR32, ccmask, 4>;
127  def LOCG  : FixedCondUnaryRSY<"locg"##name,  0xEBE2, GR64, ccmask, 8>;
128  def STOC  : FixedCondStoreRSY<"stoc"##name,  0xEBF3, GR32, ccmask, 4>;
129  def STOCG : FixedCondStoreRSY<"stocg"##name, 0xEBE3, GR64, ccmask, 8>;
130}
131defm AsmO   : CondExtendedMnemonic<1,  "o">;
132defm AsmH   : CondExtendedMnemonic<2,  "h">;
133defm AsmNLE : CondExtendedMnemonic<3,  "nle">;
134defm AsmL   : CondExtendedMnemonic<4,  "l">;
135defm AsmNHE : CondExtendedMnemonic<5,  "nhe">;
136defm AsmLH  : CondExtendedMnemonic<6,  "lh">;
137defm AsmNE  : CondExtendedMnemonic<7,  "ne">;
138defm AsmE   : CondExtendedMnemonic<8,  "e">;
139defm AsmNLH : CondExtendedMnemonic<9,  "nlh">;
140defm AsmHE  : CondExtendedMnemonic<10, "he">;
141defm AsmNL  : CondExtendedMnemonic<11, "nl">;
142defm AsmLE  : CondExtendedMnemonic<12, "le">;
143defm AsmNH  : CondExtendedMnemonic<13, "nh">;
144defm AsmNO  : CondExtendedMnemonic<14, "no">;
145
146// Define AsmParser mnemonics for each integer condition-code mask.
147// This is like the list above, except that condition 3 is not possible
148// and that the low bit of the mask is therefore always 0.  This means
149// that each condition has two names.  Conditions "o" and "no" are not used.
150//
151// We don't make one of the two names an alias of the other because
152// we need the custom parsing routines to select the correct register class.
153multiclass IntCondExtendedMnemonicA<bits<4> ccmask, string name> {
154  let M3 = ccmask in {
155    def CR  : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2,
156                                            brtarget16:$RI4),
157                       "crj"##name##"\t$R1, $R2, $RI4", []>;
158    def CGR : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2,
159                                            brtarget16:$RI4),
160                       "cgrj"##name##"\t$R1, $R2, $RI4", []>;
161    def CI  : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2,
162                                            brtarget16:$RI4),
163                       "cij"##name##"\t$R1, $I2, $RI4", []>;
164    def CGI : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2,
165                                            brtarget16:$RI4),
166                       "cgij"##name##"\t$R1, $I2, $RI4", []>;
167    def CLR  : InstRIEb<0xEC77, (outs), (ins GR32:$R1, GR32:$R2,
168                                            brtarget16:$RI4),
169                        "clrj"##name##"\t$R1, $R2, $RI4", []>;
170    def CLGR : InstRIEb<0xEC65, (outs), (ins GR64:$R1, GR64:$R2,
171                                             brtarget16:$RI4),
172                        "clgrj"##name##"\t$R1, $R2, $RI4", []>;
173    def CLI  : InstRIEc<0xEC7F, (outs), (ins GR32:$R1, imm32zx8:$I2,
174                                             brtarget16:$RI4),
175                        "clij"##name##"\t$R1, $I2, $RI4", []>;
176    def CLGI : InstRIEc<0xEC7D, (outs), (ins GR64:$R1, imm64zx8:$I2,
177                                             brtarget16:$RI4),
178                        "clgij"##name##"\t$R1, $I2, $RI4", []>;
179  }
180}
181multiclass IntCondExtendedMnemonic<bits<4> ccmask, string name1, string name2>
182  : IntCondExtendedMnemonicA<ccmask, name1> {
183  let isAsmParserOnly = 1 in
184    defm Alt : IntCondExtendedMnemonicA<ccmask, name2>;
185}
186defm AsmJH   : IntCondExtendedMnemonic<2,  "h",  "nle">;
187defm AsmJL   : IntCondExtendedMnemonic<4,  "l",  "nhe">;
188defm AsmJLH  : IntCondExtendedMnemonic<6,  "lh", "ne">;
189defm AsmJE   : IntCondExtendedMnemonic<8,  "e",  "nlh">;
190defm AsmJHE  : IntCondExtendedMnemonic<10, "he", "nl">;
191defm AsmJLE  : IntCondExtendedMnemonic<12, "le", "nh">;
192
193// Decrement a register and branch if it is nonzero.  These don't clobber CC,
194// but we might need to split long branches into sequences that do.
195let Defs = [CC] in {
196  def BRCT  : BranchUnaryRI<"brct",  0xA76, GR32>;
197  def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>;
198}
199
200//===----------------------------------------------------------------------===//
201// Select instructions
202//===----------------------------------------------------------------------===//
203
204def Select32Mux : SelectWrapper<GRX32>, Requires<[FeatureHighWord]>;
205def Select32    : SelectWrapper<GR32>;
206def Select64    : SelectWrapper<GR64>;
207
208// We don't define 32-bit Mux stores because the low-only STOC should
209// always be used if possible.
210defm CondStore8Mux  : CondStores<GRX32, nonvolatile_truncstorei8,
211                                 nonvolatile_anyextloadi8, bdxaddr20only>,
212                      Requires<[FeatureHighWord]>;
213defm CondStore16Mux : CondStores<GRX32, nonvolatile_truncstorei16,
214                                 nonvolatile_anyextloadi16, bdxaddr20only>,
215                      Requires<[FeatureHighWord]>;
216defm CondStore8     : CondStores<GR32, nonvolatile_truncstorei8,
217                                 nonvolatile_anyextloadi8, bdxaddr20only>;
218defm CondStore16    : CondStores<GR32, nonvolatile_truncstorei16,
219                                 nonvolatile_anyextloadi16, bdxaddr20only>;
220defm CondStore32    : CondStores<GR32, nonvolatile_store,
221                                 nonvolatile_load, bdxaddr20only>;
222
223defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8,
224                    nonvolatile_anyextloadi8, bdxaddr20only>;
225defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16,
226                    nonvolatile_anyextloadi16, bdxaddr20only>;
227defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32,
228                    nonvolatile_anyextloadi32, bdxaddr20only>;
229defm CondStore64 : CondStores<GR64, nonvolatile_store,
230                              nonvolatile_load, bdxaddr20only>;
231
232//===----------------------------------------------------------------------===//
233// Call instructions
234//===----------------------------------------------------------------------===//
235
236let isCall = 1, Defs = [R14D, CC] in {
237  def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops),
238                        [(z_call pcrel32:$I2)]>;
239  def CallBASR  : Alias<2, (outs), (ins ADDR64:$R2, variable_ops),
240                        [(z_call ADDR64:$R2)]>;
241}
242
243// Sibling calls.  Indirect sibling calls must be via R1, since R2 upwards
244// are argument registers and since branching to R0 is a no-op.
245let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
246  def CallJG : Alias<6, (outs), (ins pcrel32:$I2),
247                     [(z_sibcall pcrel32:$I2)]>;
248  let Uses = [R1D] in
249    def CallBR : Alias<2, (outs), (ins), [(z_sibcall R1D)]>;
250}
251
252// Define the general form of the call instructions for the asm parser.
253// These instructions don't hard-code %r14 as the return address register.
254def BRAS  : InstRI<0xA75, (outs), (ins GR64:$R1, brtarget16:$I2),
255                   "bras\t$R1, $I2", []>;
256def BRASL : InstRIL<0xC05, (outs), (ins GR64:$R1, brtarget32:$I2),
257                    "brasl\t$R1, $I2", []>;
258def BASR  : InstRR<0x0D, (outs), (ins GR64:$R1, ADDR64:$R2),
259                   "basr\t$R1, $R2", []>;
260
261//===----------------------------------------------------------------------===//
262// Move instructions
263//===----------------------------------------------------------------------===//
264
265// Register moves.
266let neverHasSideEffects = 1 in {
267  // Expands to LR, RISBHG or RISBLG, depending on the choice of registers.
268  def LRMux : UnaryRRPseudo<"l", null_frag, GRX32, GRX32>,
269              Requires<[FeatureHighWord]>;
270  def LR  : UnaryRR <"l",  0x18,   null_frag, GR32, GR32>;
271  def LGR : UnaryRRE<"lg", 0xB904, null_frag, GR64, GR64>;
272}
273let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
274  def LTR  : UnaryRR <"lt",  0x12,   null_frag, GR32, GR32>;
275  def LTGR : UnaryRRE<"ltg", 0xB902, null_frag, GR64, GR64>;
276}
277
278// Move on condition.
279let isCodeGenOnly = 1, Uses = [CC] in {
280  def LOCR  : CondUnaryRRF<"loc",  0xB9F2, GR32, GR32>;
281  def LOCGR : CondUnaryRRF<"locg", 0xB9E2, GR64, GR64>;
282}
283let Uses = [CC] in {
284  def AsmLOCR  : AsmCondUnaryRRF<"loc",  0xB9F2, GR32, GR32>;
285  def AsmLOCGR : AsmCondUnaryRRF<"locg", 0xB9E2, GR64, GR64>;
286}
287
288// Immediate moves.
289let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
290    isReMaterializable = 1 in {
291  // 16-bit sign-extended immediates.  LHIMux expands to LHI or IIHF,
292  // deopending on the choice of register.
293  def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>,
294               Requires<[FeatureHighWord]>;
295  def LHI  : UnaryRI<"lhi",  0xA78, bitconvert, GR32, imm32sx16>;
296  def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>;
297
298  // Other 16-bit immediates.
299  def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>;
300  def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>;
301  def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>;
302  def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>;
303
304  // 32-bit immediates.
305  def LGFI  : UnaryRIL<"lgfi",  0xC01, bitconvert, GR64, imm64sx32>;
306  def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>;
307  def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>;
308}
309
310// Register loads.
311let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
312  // Expands to L, LY or LFH, depending on the choice of register.
313  def LMux : UnaryRXYPseudo<"l", load, GRX32, 4>,
314             Requires<[FeatureHighWord]>;
315  defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>;
316  def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>,
317            Requires<[FeatureHighWord]>;
318  def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>;
319
320  // These instructions are split after register allocation, so we don't
321  // want a custom inserter.
322  let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
323    def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src),
324                      [(set GR128:$dst, (load bdxaddr20only128:$src))]>;
325  }
326}
327let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
328  def LT  : UnaryRXY<"lt",  0xE312, load, GR32, 4>;
329  def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>;
330}
331
332let canFoldAsLoad = 1 in {
333  def LRL  : UnaryRILPC<"lrl",  0xC4D, aligned_load, GR32>;
334  def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>;
335}
336
337// Load on condition.
338let isCodeGenOnly = 1, Uses = [CC] in {
339  def LOC  : CondUnaryRSY<"loc",  0xEBF2, nonvolatile_load, GR32, 4>;
340  def LOCG : CondUnaryRSY<"locg", 0xEBE2, nonvolatile_load, GR64, 8>;
341}
342let Uses = [CC] in {
343  def AsmLOC  : AsmCondUnaryRSY<"loc",  0xEBF2, GR32, 4>;
344  def AsmLOCG : AsmCondUnaryRSY<"locg", 0xEBE2, GR64, 8>;
345}
346
347// Register stores.
348let SimpleBDXStore = 1 in {
349  // Expands to ST, STY or STFH, depending on the choice of register.
350  def STMux : StoreRXYPseudo<store, GRX32, 4>,
351              Requires<[FeatureHighWord]>;
352  defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>;
353  def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>,
354             Requires<[FeatureHighWord]>;
355  def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>;
356
357  // These instructions are split after register allocation, so we don't
358  // want a custom inserter.
359  let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
360    def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst),
361                       [(store GR128:$src, bdxaddr20only128:$dst)]>;
362  }
363}
364def STRL  : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>;
365def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>;
366
367// Store on condition.
368let isCodeGenOnly = 1, Uses = [CC] in {
369  def STOC  : CondStoreRSY<"stoc",  0xEBF3, GR32, 4>;
370  def STOCG : CondStoreRSY<"stocg", 0xEBE3, GR64, 8>;
371}
372let Uses = [CC] in {
373  def AsmSTOC  : AsmCondStoreRSY<"stoc",  0xEBF3, GR32, 4>;
374  def AsmSTOCG : AsmCondStoreRSY<"stocg", 0xEBE3, GR64, 8>;
375}
376
377// 8-bit immediate stores to 8-bit fields.
378defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>;
379
380// 16-bit immediate stores to 16-, 32- or 64-bit fields.
381def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>;
382def MVHI  : StoreSIL<"mvhi",  0xE54C, store,         imm32sx16>;
383def MVGHI : StoreSIL<"mvghi", 0xE548, store,         imm64sx16>;
384
385// Memory-to-memory moves.
386let mayLoad = 1, mayStore = 1 in
387  defm MVC : MemorySS<"mvc", 0xD2, z_mvc, z_mvc_loop>;
388
389// String moves.
390let mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L] in
391  defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>;
392
393//===----------------------------------------------------------------------===//
394// Sign extensions
395//===----------------------------------------------------------------------===//
396//
397// Note that putting these before zero extensions mean that we will prefer
398// them for anyextload*.  There's not really much to choose between the two
399// either way, but signed-extending loads have a short LH and a long LHY,
400// while zero-extending loads have only the long LLH.
401//
402//===----------------------------------------------------------------------===//
403
404// 32-bit extensions from registers.
405let neverHasSideEffects = 1 in {
406  def LBR : UnaryRRE<"lb", 0xB926, sext8,  GR32, GR32>;
407  def LHR : UnaryRRE<"lh", 0xB927, sext16, GR32, GR32>;
408}
409
410// 64-bit extensions from registers.
411let neverHasSideEffects = 1 in {
412  def LGBR : UnaryRRE<"lgb", 0xB906, sext8,  GR64, GR64>;
413  def LGHR : UnaryRRE<"lgh", 0xB907, sext16, GR64, GR64>;
414  def LGFR : UnaryRRE<"lgf", 0xB914, sext32, GR64, GR32>;
415}
416let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
417  def LTGFR : UnaryRRE<"ltgf", 0xB912, null_frag, GR64, GR64>;
418
419// Match 32-to-64-bit sign extensions in which the source is already
420// in a 64-bit register.
421def : Pat<(sext_inreg GR64:$src, i32),
422          (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>;
423
424// 32-bit extensions from 8-bit memory.  LBMux expands to LB or LBH,
425// depending on the choice of register.
426def LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>,
427            Requires<[FeatureHighWord]>;
428def LB  : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>;
429def LBH : UnaryRXY<"lbh", 0xE3C0, asextloadi8, GRH32, 1>,
430          Requires<[FeatureHighWord]>;
431
432// 32-bit extensions from 16-bit memory.  LHMux expands to LH or LHH,
433// depending on the choice of register.
434def LHMux : UnaryRXYPseudo<"lh", asextloadi16, GRX32, 2>,
435            Requires<[FeatureHighWord]>;
436defm LH   : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>;
437def  LHH  : UnaryRXY<"lhh", 0xE3C4, asextloadi16, GRH32, 2>,
438            Requires<[FeatureHighWord]>;
439def  LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>;
440
441// 64-bit extensions from memory.
442def LGB   : UnaryRXY<"lgb", 0xE377, asextloadi8,  GR64, 1>;
443def LGH   : UnaryRXY<"lgh", 0xE315, asextloadi16, GR64, 2>;
444def LGF   : UnaryRXY<"lgf", 0xE314, asextloadi32, GR64, 4>;
445def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_asextloadi16, GR64>;
446def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_asextloadi32, GR64>;
447let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
448  def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>;
449
450//===----------------------------------------------------------------------===//
451// Zero extensions
452//===----------------------------------------------------------------------===//
453
454// 32-bit extensions from registers.
455let neverHasSideEffects = 1 in {
456  // Expands to LLCR or RISB[LH]G, depending on the choice of registers.
457  def LLCRMux : UnaryRRPseudo<"llc", zext8, GRX32, GRX32>,
458                Requires<[FeatureHighWord]>;
459  def LLCR    : UnaryRRE<"llc", 0xB994, zext8,  GR32, GR32>;
460  // Expands to LLHR or RISB[LH]G, depending on the choice of registers.
461  def LLHRMux : UnaryRRPseudo<"llh", zext16, GRX32, GRX32>,
462                Requires<[FeatureHighWord]>;
463  def LLHR    : UnaryRRE<"llh", 0xB995, zext16, GR32, GR32>;
464}
465
466// 64-bit extensions from registers.
467let neverHasSideEffects = 1 in {
468  def LLGCR : UnaryRRE<"llgc", 0xB984, zext8,  GR64, GR64>;
469  def LLGHR : UnaryRRE<"llgh", 0xB985, zext16, GR64, GR64>;
470  def LLGFR : UnaryRRE<"llgf", 0xB916, zext32, GR64, GR32>;
471}
472
473// Match 32-to-64-bit zero extensions in which the source is already
474// in a 64-bit register.
475def : Pat<(and GR64:$src, 0xffffffff),
476          (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>;
477
478// 32-bit extensions from 8-bit memory.  LLCMux expands to LLC or LLCH,
479// depending on the choice of register.
480def LLCMux : UnaryRXYPseudo<"llc", azextloadi8, GRX32, 1>,
481             Requires<[FeatureHighWord]>;
482def LLC  : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>;
483def LLCH : UnaryRXY<"llch", 0xE3C2, azextloadi8, GR32, 1>,
484           Requires<[FeatureHighWord]>;
485
486// 32-bit extensions from 16-bit memory.  LLHMux expands to LLH or LLHH,
487// depending on the choice of register.
488def LLHMux : UnaryRXYPseudo<"llh", azextloadi16, GRX32, 2>,
489             Requires<[FeatureHighWord]>;
490def LLH   : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>;
491def LLHH  : UnaryRXY<"llhh", 0xE3C6, azextloadi16, GR32, 2>,
492            Requires<[FeatureHighWord]>;
493def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>;
494
495// 64-bit extensions from memory.
496def LLGC   : UnaryRXY<"llgc", 0xE390, azextloadi8,  GR64, 1>;
497def LLGH   : UnaryRXY<"llgh", 0xE391, azextloadi16, GR64, 2>;
498def LLGF   : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>;
499def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>;
500def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>;
501
502//===----------------------------------------------------------------------===//
503// Truncations
504//===----------------------------------------------------------------------===//
505
506// Truncations of 64-bit registers to 32-bit registers.
507def : Pat<(i32 (trunc GR64:$src)),
508          (EXTRACT_SUBREG GR64:$src, subreg_l32)>;
509
510// Truncations of 32-bit registers to 8-bit memory.  STCMux expands to
511// STC, STCY or STCH, depending on the choice of register.
512def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>,
513             Requires<[FeatureHighWord]>;
514defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>;
515def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>,
516           Requires<[FeatureHighWord]>;
517
518// Truncations of 32-bit registers to 16-bit memory.  STHMux expands to
519// STH, STHY or STHH, depending on the choice of register.
520def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>,
521             Requires<[FeatureHighWord]>;
522defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>;
523def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>,
524           Requires<[FeatureHighWord]>;
525def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>;
526
527// Truncations of 64-bit registers to memory.
528defm : StoreGR64Pair<STC, STCY, truncstorei8>;
529defm : StoreGR64Pair<STH, STHY, truncstorei16>;
530def  : StoreGR64PC<STHRL, aligned_truncstorei16>;
531defm : StoreGR64Pair<ST, STY, truncstorei32>;
532def  : StoreGR64PC<STRL, aligned_truncstorei32>;
533
534//===----------------------------------------------------------------------===//
535// Multi-register moves
536//===----------------------------------------------------------------------===//
537
538// Multi-register loads.
539def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>;
540
541// Multi-register stores.
542def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>;
543
544//===----------------------------------------------------------------------===//
545// Byte swaps
546//===----------------------------------------------------------------------===//
547
548// Byte-swapping register moves.
549let neverHasSideEffects = 1 in {
550  def LRVR  : UnaryRRE<"lrv",  0xB91F, bswap, GR32, GR32>;
551  def LRVGR : UnaryRRE<"lrvg", 0xB90F, bswap, GR64, GR64>;
552}
553
554// Byte-swapping loads.  Unlike normal loads, these instructions are
555// allowed to access storage more than once.
556def LRV  : UnaryRXY<"lrv",  0xE31E, loadu<bswap, nonvolatile_load>, GR32, 4>;
557def LRVG : UnaryRXY<"lrvg", 0xE30F, loadu<bswap, nonvolatile_load>, GR64, 8>;
558
559// Likewise byte-swapping stores.
560def STRV  : StoreRXY<"strv", 0xE33E, storeu<bswap, nonvolatile_store>, GR32, 4>;
561def STRVG : StoreRXY<"strvg", 0xE32F, storeu<bswap, nonvolatile_store>,
562                     GR64, 8>;
563
564//===----------------------------------------------------------------------===//
565// Load address instructions
566//===----------------------------------------------------------------------===//
567
568// Load BDX-style addresses.
569let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isReMaterializable = 1,
570    DispKey = "la" in {
571  let DispSize = "12" in
572    def LA : InstRX<0x41, (outs GR64:$R1), (ins laaddr12pair:$XBD2),
573                    "la\t$R1, $XBD2",
574                    [(set GR64:$R1, laaddr12pair:$XBD2)]>;
575  let DispSize = "20" in
576    def LAY : InstRXY<0xE371, (outs GR64:$R1), (ins laaddr20pair:$XBD2),
577                      "lay\t$R1, $XBD2",
578                      [(set GR64:$R1, laaddr20pair:$XBD2)]>;
579}
580
581// Load a PC-relative address.  There's no version of this instruction
582// with a 16-bit offset, so there's no relaxation.
583let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
584    isReMaterializable = 1 in {
585  def LARL : InstRIL<0xC00, (outs GR64:$R1), (ins pcrel32:$I2),
586                     "larl\t$R1, $I2",
587                     [(set GR64:$R1, pcrel32:$I2)]>;
588}
589
590//===----------------------------------------------------------------------===//
591// Absolute and Negation
592//===----------------------------------------------------------------------===//
593
594let Defs = [CC] in {
595  let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
596    def LPR  : UnaryRR <"lp",  0x10,   z_iabs, GR32, GR32>;
597    def LPGR : UnaryRRE<"lpg", 0xB900, z_iabs, GR64, GR64>;
598  }
599  let CCValues = 0xE, CompareZeroCCMask = 0xE in
600    def LPGFR : UnaryRRE<"lpgf", 0xB910, null_frag, GR64, GR32>;
601}
602def : Pat<(z_iabs32 GR32:$src), (LPR  GR32:$src)>;
603def : Pat<(z_iabs64 GR64:$src), (LPGR GR64:$src)>;
604defm : SXU<z_iabs,   LPGFR>;
605defm : SXU<z_iabs64, LPGFR>;
606
607let Defs = [CC] in {
608  let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
609    def LNR  : UnaryRR <"ln",  0x11,   z_inegabs, GR32, GR32>;
610    def LNGR : UnaryRRE<"lng", 0xB901, z_inegabs, GR64, GR64>;
611  }
612  let CCValues = 0xE, CompareZeroCCMask = 0xE in
613    def LNGFR : UnaryRRE<"lngf", 0xB911, null_frag, GR64, GR32>;
614}
615def : Pat<(z_inegabs32 GR32:$src), (LNR  GR32:$src)>;
616def : Pat<(z_inegabs64 GR64:$src), (LNGR GR64:$src)>;
617defm : SXU<z_inegabs,   LNGFR>;
618defm : SXU<z_inegabs64, LNGFR>;
619
620let Defs = [CC] in {
621  let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
622    def LCR  : UnaryRR <"lc",  0x13,   ineg, GR32, GR32>;
623    def LCGR : UnaryRRE<"lcg", 0xB903, ineg, GR64, GR64>;
624  }
625  let CCValues = 0xE, CompareZeroCCMask = 0xE in
626    def LCGFR : UnaryRRE<"lcgf", 0xB913, null_frag, GR64, GR32>;
627}
628defm : SXU<ineg, LCGFR>;
629
630//===----------------------------------------------------------------------===//
631// Insertion
632//===----------------------------------------------------------------------===//
633
634let isCodeGenOnly = 1 in
635  defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, azextloadi8, 1>;
636defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>;
637
638defm : InsertMem<"inserti8", IC32,  GR32, azextloadi8, bdxaddr12pair>;
639defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>;
640
641defm : InsertMem<"inserti8", IC,  GR64, azextloadi8, bdxaddr12pair>;
642defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>;
643
644// Insertions of a 16-bit immediate, leaving other bits unaffected.
645// We don't have or_as_insert equivalents of these operations because
646// OI is available instead.
647//
648// IIxMux expands to II[LH]x, depending on the choice of register.
649def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>,
650             Requires<[FeatureHighWord]>;
651def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>,
652             Requires<[FeatureHighWord]>;
653def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>;
654def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>;
655def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>;
656def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>;
657def IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>;
658def IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>;
659def IIHL64 : BinaryAliasRI<inserthl, GR64, imm64hl16>;
660def IIHH64 : BinaryAliasRI<inserthh, GR64, imm64hh16>;
661
662// ...likewise for 32-bit immediates.  For GR32s this is a general
663// full-width move.  (We use IILF rather than something like LLILF
664// for 32-bit moves because IILF leaves the upper 32 bits of the
665// GR64 unchanged.)
666let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in {
667  def IIFMux : UnaryRIPseudo<bitconvert, GRX32, uimm32>,
668               Requires<[FeatureHighWord]>;
669  def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>;
670  def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>;
671}
672def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>;
673def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>;
674
675// An alternative model of inserthf, with the first operand being
676// a zero-extended value.
677def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm),
678          (IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32),
679                  imm64hf32:$imm)>;
680
681//===----------------------------------------------------------------------===//
682// Addition
683//===----------------------------------------------------------------------===//
684
685// Plain addition.
686let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in {
687  // Addition of a register.
688  let isCommutable = 1 in {
689    defm AR : BinaryRRAndK<"a", 0x1A, 0xB9F8, add, GR32, GR32>;
690    defm AGR : BinaryRREAndK<"ag", 0xB908, 0xB9E8, add, GR64, GR64>;
691  }
692  def AGFR : BinaryRRE<"agf", 0xB918, null_frag, GR64, GR32>;
693
694  // Addition of signed 16-bit immediates.
695  defm AHIMux : BinaryRIAndKPseudo<"ahimux", add, GRX32, imm32sx16>;
696  defm AHI  : BinaryRIAndK<"ahi",  0xA7A, 0xECD8, add, GR32, imm32sx16>;
697  defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, add, GR64, imm64sx16>;
698
699  // Addition of signed 32-bit immediates.
700  def AFIMux : BinaryRIPseudo<add, GRX32, simm32>,
701               Requires<[FeatureHighWord]>;
702  def AFI  : BinaryRIL<"afi",  0xC29, add, GR32, simm32>;
703  def AIH  : BinaryRIL<"aih",  0xCC8, add, GRH32, simm32>,
704             Requires<[FeatureHighWord]>;
705  def AGFI : BinaryRIL<"agfi", 0xC28, add, GR64, imm64sx32>;
706
707  // Addition of memory.
708  defm AH  : BinaryRXPair<"ah", 0x4A, 0xE37A, add, GR32, asextloadi16, 2>;
709  defm A   : BinaryRXPair<"a",  0x5A, 0xE35A, add, GR32, load, 4>;
710  def  AGF : BinaryRXY<"agf", 0xE318, add, GR64, asextloadi32, 4>;
711  def  AG  : BinaryRXY<"ag",  0xE308, add, GR64, load, 8>;
712
713  // Addition to memory.
714  def ASI  : BinarySIY<"asi",  0xEB6A, add, imm32sx8>;
715  def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>;
716}
717defm : SXB<add, GR64, AGFR>;
718
719// Addition producing a carry.
720let Defs = [CC] in {
721  // Addition of a register.
722  let isCommutable = 1 in {
723    defm ALR : BinaryRRAndK<"al", 0x1E, 0xB9FA, addc, GR32, GR32>;
724    defm ALGR : BinaryRREAndK<"alg", 0xB90A, 0xB9EA, addc, GR64, GR64>;
725  }
726  def ALGFR : BinaryRRE<"algf", 0xB91A, null_frag, GR64, GR32>;
727
728  // Addition of signed 16-bit immediates.
729  def ALHSIK  : BinaryRIE<"alhsik",  0xECDA, addc, GR32, imm32sx16>,
730                Requires<[FeatureDistinctOps]>;
731  def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, addc, GR64, imm64sx16>,
732                Requires<[FeatureDistinctOps]>;
733
734  // Addition of unsigned 32-bit immediates.
735  def ALFI  : BinaryRIL<"alfi",  0xC2B, addc, GR32, uimm32>;
736  def ALGFI : BinaryRIL<"algfi", 0xC2A, addc, GR64, imm64zx32>;
737
738  // Addition of memory.
739  defm AL   : BinaryRXPair<"al", 0x5E, 0xE35E, addc, GR32, load, 4>;
740  def  ALGF : BinaryRXY<"algf", 0xE31A, addc, GR64, azextloadi32, 4>;
741  def  ALG  : BinaryRXY<"alg",  0xE30A, addc, GR64, load, 8>;
742}
743defm : ZXB<addc, GR64, ALGFR>;
744
745// Addition producing and using a carry.
746let Defs = [CC], Uses = [CC] in {
747  // Addition of a register.
748  def ALCR  : BinaryRRE<"alc",  0xB998, adde, GR32, GR32>;
749  def ALCGR : BinaryRRE<"alcg", 0xB988, adde, GR64, GR64>;
750
751  // Addition of memory.
752  def ALC  : BinaryRXY<"alc",  0xE398, adde, GR32, load, 4>;
753  def ALCG : BinaryRXY<"alcg", 0xE388, adde, GR64, load, 8>;
754}
755
756//===----------------------------------------------------------------------===//
757// Subtraction
758//===----------------------------------------------------------------------===//
759
760// Plain subtraction.  Although immediate forms exist, we use the
761// add-immediate instruction instead.
762let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in {
763  // Subtraction of a register.
764  defm SR : BinaryRRAndK<"s", 0x1B, 0xB9F9, sub, GR32, GR32>;
765  def SGFR : BinaryRRE<"sgf", 0xB919, null_frag, GR64, GR32>;
766  defm SGR : BinaryRREAndK<"sg", 0xB909, 0xB9E9, sub, GR64, GR64>;
767
768  // Subtraction of memory.
769  defm SH  : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, asextloadi16, 2>;
770  defm S   : BinaryRXPair<"s", 0x5B, 0xE35B, sub, GR32, load, 4>;
771  def  SGF : BinaryRXY<"sgf", 0xE319, sub, GR64, asextloadi32, 4>;
772  def  SG  : BinaryRXY<"sg",  0xE309, sub, GR64, load, 8>;
773}
774defm : SXB<sub, GR64, SGFR>;
775
776// Subtraction producing a carry.
777let Defs = [CC] in {
778  // Subtraction of a register.
779  defm SLR : BinaryRRAndK<"sl", 0x1F, 0xB9FB, subc, GR32, GR32>;
780  def SLGFR : BinaryRRE<"slgf", 0xB91B, null_frag, GR64, GR32>;
781  defm SLGR : BinaryRREAndK<"slg", 0xB90B, 0xB9EB, subc, GR64, GR64>;
782
783  // Subtraction of unsigned 32-bit immediates.  These don't match
784  // subc because we prefer addc for constants.
785  def SLFI  : BinaryRIL<"slfi",  0xC25, null_frag, GR32, uimm32>;
786  def SLGFI : BinaryRIL<"slgfi", 0xC24, null_frag, GR64, imm64zx32>;
787
788  // Subtraction of memory.
789  defm SL   : BinaryRXPair<"sl", 0x5F, 0xE35F, subc, GR32, load, 4>;
790  def  SLGF : BinaryRXY<"slgf", 0xE31B, subc, GR64, azextloadi32, 4>;
791  def  SLG  : BinaryRXY<"slg",  0xE30B, subc, GR64, load, 8>;
792}
793defm : ZXB<subc, GR64, SLGFR>;
794
795// Subtraction producing and using a carry.
796let Defs = [CC], Uses = [CC] in {
797  // Subtraction of a register.
798  def SLBR  : BinaryRRE<"slb",  0xB999, sube, GR32, GR32>;
799  def SLGBR : BinaryRRE<"slbg", 0xB989, sube, GR64, GR64>;
800
801  // Subtraction of memory.
802  def SLB  : BinaryRXY<"slb",  0xE399, sube, GR32, load, 4>;
803  def SLBG : BinaryRXY<"slbg", 0xE389, sube, GR64, load, 8>;
804}
805
806//===----------------------------------------------------------------------===//
807// AND
808//===----------------------------------------------------------------------===//
809
810let Defs = [CC] in {
811  // ANDs of a register.
812  let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
813    defm NR : BinaryRRAndK<"n", 0x14, 0xB9F4, and, GR32, GR32>;
814    defm NGR : BinaryRREAndK<"ng", 0xB980, 0xB9E4, and, GR64, GR64>;
815  }
816
817  let isConvertibleToThreeAddress = 1 in {
818    // ANDs of a 16-bit immediate, leaving other bits unaffected.
819    // The CC result only reflects the 16-bit field, not the full register.
820    //
821    // NIxMux expands to NI[LH]x, depending on the choice of register.
822    def NILMux : BinaryRIPseudo<and, GRX32, imm32ll16c>,
823                 Requires<[FeatureHighWord]>;
824    def NIHMux : BinaryRIPseudo<and, GRX32, imm32lh16c>,
825                 Requires<[FeatureHighWord]>;
826    def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>;
827    def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>;
828    def NIHL : BinaryRI<"nihl", 0xA55, and, GRH32, imm32ll16c>;
829    def NIHH : BinaryRI<"nihh", 0xA54, and, GRH32, imm32lh16c>;
830    def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>;
831    def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>;
832    def NIHL64 : BinaryAliasRI<and, GR64, imm64hl16c>;
833    def NIHH64 : BinaryAliasRI<and, GR64, imm64hh16c>;
834
835    // ANDs of a 32-bit immediate, leaving other bits unaffected.
836    // The CC result only reflects the 32-bit field, which means we can
837    // use it as a zero indicator for i32 operations but not otherwise.
838    let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
839      // Expands to NILF or NIHF, depending on the choice of register.
840      def NIFMux : BinaryRIPseudo<and, GRX32, uimm32>,
841                   Requires<[FeatureHighWord]>;
842      def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>;
843      def NIHF : BinaryRIL<"nihf", 0xC0A, and, GRH32, uimm32>;
844    }
845    def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>;
846    def NIHF64 : BinaryAliasRIL<and, GR64, imm64hf32c>;
847  }
848
849  // ANDs of memory.
850  let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
851    defm N  : BinaryRXPair<"n", 0x54, 0xE354, and, GR32, load, 4>;
852    def  NG : BinaryRXY<"ng", 0xE380, and, GR64, load, 8>; 
853  }
854
855  // AND to memory
856  defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, imm32zx8>;
857
858  // Block AND.
859  let mayLoad = 1, mayStore = 1 in
860    defm NC : MemorySS<"nc", 0xD4, z_nc, z_nc_loop>;
861}
862defm : RMWIByte<and, bdaddr12pair, NI>;
863defm : RMWIByte<and, bdaddr20pair, NIY>;
864
865//===----------------------------------------------------------------------===//
866// OR
867//===----------------------------------------------------------------------===//
868
869let Defs = [CC] in {
870  // ORs of a register.
871  let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
872    defm OR : BinaryRRAndK<"o", 0x16, 0xB9F6, or, GR32, GR32>;
873    defm OGR : BinaryRREAndK<"og", 0xB981, 0xB9E6, or, GR64, GR64>;
874  }
875
876  // ORs of a 16-bit immediate, leaving other bits unaffected.
877  // The CC result only reflects the 16-bit field, not the full register.
878  //
879  // OIxMux expands to OI[LH]x, depending on the choice of register.
880  def OILMux : BinaryRIPseudo<or, GRX32, imm32ll16>,
881               Requires<[FeatureHighWord]>;
882  def OIHMux : BinaryRIPseudo<or, GRX32, imm32lh16>,
883               Requires<[FeatureHighWord]>;
884  def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>;
885  def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>;
886  def OIHL : BinaryRI<"oihl", 0xA59, or, GRH32, imm32ll16>;
887  def OIHH : BinaryRI<"oihh", 0xA58, or, GRH32, imm32lh16>;
888  def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>;
889  def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>;
890  def OIHL64 : BinaryAliasRI<or, GR64, imm64hl16>;
891  def OIHH64 : BinaryAliasRI<or, GR64, imm64hh16>;
892
893  // ORs of a 32-bit immediate, leaving other bits unaffected.
894  // The CC result only reflects the 32-bit field, which means we can
895  // use it as a zero indicator for i32 operations but not otherwise.
896  let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
897    // Expands to OILF or OIHF, depending on the choice of register.
898    def OIFMux : BinaryRIPseudo<or, GRX32, uimm32>,
899                 Requires<[FeatureHighWord]>;
900    def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>;
901    def OIHF : BinaryRIL<"oihf", 0xC0C, or, GRH32, uimm32>;
902  }
903  def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>;
904  def OIHF64 : BinaryAliasRIL<or, GR64, imm64hf32>;
905
906  // ORs of memory.
907  let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
908    defm O  : BinaryRXPair<"o", 0x56, 0xE356, or, GR32, load, 4>;
909    def  OG : BinaryRXY<"og", 0xE381, or, GR64, load, 8>;
910  }
911
912  // OR to memory
913  defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, imm32zx8>;
914
915  // Block OR.
916  let mayLoad = 1, mayStore = 1 in
917    defm OC : MemorySS<"oc", 0xD6, z_oc, z_oc_loop>;
918}
919defm : RMWIByte<or, bdaddr12pair, OI>;
920defm : RMWIByte<or, bdaddr20pair, OIY>;
921
922//===----------------------------------------------------------------------===//
923// XOR
924//===----------------------------------------------------------------------===//
925
926let Defs = [CC] in {
927  // XORs of a register.
928  let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
929    defm XR : BinaryRRAndK<"x", 0x17, 0xB9F7, xor, GR32, GR32>;
930    defm XGR : BinaryRREAndK<"xg", 0xB982, 0xB9E7, xor, GR64, GR64>;
931  }
932
933  // XORs of a 32-bit immediate, leaving other bits unaffected.
934  // The CC result only reflects the 32-bit field, which means we can
935  // use it as a zero indicator for i32 operations but not otherwise.
936  let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
937    // Expands to XILF or XIHF, depending on the choice of register.
938    def XIFMux : BinaryRIPseudo<xor, GRX32, uimm32>,
939                 Requires<[FeatureHighWord]>;
940    def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>;
941    def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>;
942  }
943  def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>;
944  def XIHF64 : BinaryAliasRIL<xor, GR64, imm64hf32>;
945
946  // XORs of memory.
947  let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
948    defm X  : BinaryRXPair<"x",0x57, 0xE357, xor, GR32, load, 4>;
949    def  XG : BinaryRXY<"xg", 0xE382, xor, GR64, load, 8>;
950  }
951
952  // XOR to memory
953  defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, imm32zx8>;
954
955  // Block XOR.
956  let mayLoad = 1, mayStore = 1 in
957    defm XC : MemorySS<"xc", 0xD7, z_xc, z_xc_loop>;
958}
959defm : RMWIByte<xor, bdaddr12pair, XI>;
960defm : RMWIByte<xor, bdaddr20pair, XIY>;
961
962//===----------------------------------------------------------------------===//
963// Multiplication
964//===----------------------------------------------------------------------===//
965
966// Multiplication of a register.
967let isCommutable = 1 in {
968  def MSR  : BinaryRRE<"ms",  0xB252, mul, GR32, GR32>;
969  def MSGR : BinaryRRE<"msg", 0xB90C, mul, GR64, GR64>;
970}
971def MSGFR : BinaryRRE<"msgf", 0xB91C, null_frag, GR64, GR32>;
972defm : SXB<mul, GR64, MSGFR>;
973
974// Multiplication of a signed 16-bit immediate.
975def MHI  : BinaryRI<"mhi",  0xA7C, mul, GR32, imm32sx16>;
976def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>;
977
978// Multiplication of a signed 32-bit immediate.
979def MSFI  : BinaryRIL<"msfi",  0xC21, mul, GR32, simm32>;
980def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>;
981
982// Multiplication of memory.
983defm MH   : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, asextloadi16, 2>;
984defm MS   : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>;
985def  MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>;
986def  MSG  : BinaryRXY<"msg",  0xE30C, mul, GR64, load, 8>;
987
988// Multiplication of a register, producing two results.
989def MLGR : BinaryRRE<"mlg", 0xB986, z_umul_lohi64, GR128, GR64>;
990
991// Multiplication of memory, producing two results.
992def MLG : BinaryRXY<"mlg", 0xE386, z_umul_lohi64, GR128, load, 8>;
993
994//===----------------------------------------------------------------------===//
995// Division and remainder
996//===----------------------------------------------------------------------===//
997
998// Division and remainder, from registers.
999def DSGFR : BinaryRRE<"dsgf", 0xB91D, z_sdivrem32, GR128, GR32>;
1000def DSGR  : BinaryRRE<"dsg",  0xB90D, z_sdivrem64, GR128, GR64>;
1001def DLR   : BinaryRRE<"dl",   0xB997, z_udivrem32, GR128, GR32>;
1002def DLGR  : BinaryRRE<"dlg",  0xB987, z_udivrem64, GR128, GR64>;
1003
1004// Division and remainder, from memory.
1005def DSGF : BinaryRXY<"dsgf", 0xE31D, z_sdivrem32, GR128, load, 4>;
1006def DSG  : BinaryRXY<"dsg",  0xE30D, z_sdivrem64, GR128, load, 8>;
1007def DL   : BinaryRXY<"dl",   0xE397, z_udivrem32, GR128, load, 4>;
1008def DLG  : BinaryRXY<"dlg",  0xE387, z_udivrem64, GR128, load, 8>;
1009
1010//===----------------------------------------------------------------------===//
1011// Shifts
1012//===----------------------------------------------------------------------===//
1013
1014// Shift left.
1015let neverHasSideEffects = 1 in {
1016  defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shl, GR32>;
1017  def SLLG : BinaryRSY<"sllg", 0xEB0D, shl, GR64>;
1018}
1019
1020// Logical shift right.
1021let neverHasSideEffects = 1 in {
1022  defm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, srl, GR32>;
1023  def SRLG : BinaryRSY<"srlg", 0xEB0C, srl, GR64>;
1024}
1025
1026// Arithmetic shift right.
1027let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
1028  defm SRA : BinaryRSAndK<"sra", 0x8A, 0xEBDC, sra, GR32>;
1029  def SRAG : BinaryRSY<"srag", 0xEB0A, sra, GR64>;
1030}
1031
1032// Rotate left.
1033let neverHasSideEffects = 1 in {
1034  def RLL  : BinaryRSY<"rll",  0xEB1D, rotl, GR32>;
1035  def RLLG : BinaryRSY<"rllg", 0xEB1C, rotl, GR64>;
1036}
1037
1038// Rotate second operand left and inserted selected bits into first operand.
1039// These can act like 32-bit operands provided that the constant start and
1040// end bits (operands 2 and 3) are in the range [32, 64).
1041let Defs = [CC] in {
1042  let isCodeGenOnly = 1 in
1043    def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>;
1044  let CCValues = 0xE, CompareZeroCCMask = 0xE in
1045    def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>;
1046}
1047
1048// Forms of RISBG that only affect one word of the destination register.
1049// They do not set CC.
1050let Predicates = [FeatureHighWord] in {
1051  def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>;
1052  def RISBLL  : RotateSelectAliasRIEf<GR32,  GR32>;
1053  def RISBLH  : RotateSelectAliasRIEf<GR32,  GRH32>;
1054  def RISBHL  : RotateSelectAliasRIEf<GRH32, GR32>;
1055  def RISBHH  : RotateSelectAliasRIEf<GRH32, GRH32>;
1056  def RISBLG  : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>;
1057  def RISBHG  : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>;
1058}
1059
1060// Rotate second operand left and perform a logical operation with selected
1061// bits of the first operand.  The CC result only describes the selected bits,
1062// so isn't useful for a full comparison against zero.
1063let Defs = [CC] in {
1064  def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>;
1065  def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>;
1066  def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>;
1067}
1068
1069//===----------------------------------------------------------------------===//
1070// Comparison
1071//===----------------------------------------------------------------------===//
1072
1073// Signed comparisons.  We put these before the unsigned comparisons because
1074// some of the signed forms have COMPARE AND BRANCH equivalents whereas none
1075// of the unsigned forms do.
1076let Defs = [CC], CCValues = 0xE in {
1077  // Comparison with a register.
1078  def CR   : CompareRR <"c",   0x19,   z_scmp,    GR32, GR32>;
1079  def CGFR : CompareRRE<"cgf", 0xB930, null_frag, GR64, GR32>;
1080  def CGR  : CompareRRE<"cg",  0xB920, z_scmp,    GR64, GR64>;
1081
1082  // Comparison with a signed 16-bit immediate.
1083  def CHI  : CompareRI<"chi",  0xA7E, z_scmp, GR32, imm32sx16>;
1084  def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>;
1085
1086  // Comparison with a signed 32-bit immediate.  CFIMux expands to CFI or CIH,
1087  // depending on the choice of register.
1088  def CFIMux : CompareRIPseudo<z_scmp, GRX32, simm32>,
1089               Requires<[FeatureHighWord]>;
1090  def CFI  : CompareRIL<"cfi",  0xC2D, z_scmp, GR32, simm32>;
1091  def CIH  : CompareRIL<"cih",  0xCCD, z_scmp, GRH32, simm32>,
1092             Requires<[FeatureHighWord]>;
1093  def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>;
1094
1095  // Comparison with memory.
1096  defm CH    : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, asextloadi16, 2>;
1097  def  CMux  : CompareRXYPseudo<z_scmp, GRX32, load, 4>,
1098               Requires<[FeatureHighWord]>;
1099  defm C     : CompareRXPair<"c",  0x59, 0xE359, z_scmp, GR32, load, 4>;
1100  def  CHF   : CompareRXY<"chf", 0xE3CD, z_scmp, GRH32, load, 4>,
1101               Requires<[FeatureHighWord]>;
1102  def  CGH   : CompareRXY<"cgh", 0xE334, z_scmp, GR64, asextloadi16, 2>;
1103  def  CGF   : CompareRXY<"cgf", 0xE330, z_scmp, GR64, asextloadi32, 4>;
1104  def  CG    : CompareRXY<"cg",  0xE320, z_scmp, GR64, load, 8>;
1105  def  CHRL  : CompareRILPC<"chrl",  0xC65, z_scmp, GR32, aligned_asextloadi16>;
1106  def  CRL   : CompareRILPC<"crl",   0xC6D, z_scmp, GR32, aligned_load>;
1107  def  CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_asextloadi16>;
1108  def  CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_asextloadi32>;
1109  def  CGRL  : CompareRILPC<"cgrl",  0xC68, z_scmp, GR64, aligned_load>;
1110
1111  // Comparison between memory and a signed 16-bit immediate.
1112  def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, asextloadi16, imm32sx16>;
1113  def CHSI  : CompareSIL<"chsi",  0xE55C, z_scmp, load, imm32sx16>;
1114  def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, load, imm64sx16>;
1115}
1116defm : SXB<z_scmp, GR64, CGFR>;
1117
1118// Unsigned comparisons.
1119let Defs = [CC], CCValues = 0xE, IsLogical = 1 in {
1120  // Comparison with a register.
1121  def CLR   : CompareRR <"cl",   0x15,   z_ucmp,    GR32, GR32>;
1122  def CLGFR : CompareRRE<"clgf", 0xB931, null_frag, GR64, GR32>;
1123  def CLGR  : CompareRRE<"clg",  0xB921, z_ucmp,    GR64, GR64>;
1124
1125  // Comparison with an unsigned 32-bit immediate.  CLFIMux expands to CLFI
1126  // or CLIH, depending on the choice of register.
1127  def CLFIMux : CompareRIPseudo<z_ucmp, GRX32, uimm32>,
1128                Requires<[FeatureHighWord]>;
1129  def CLFI  : CompareRIL<"clfi",  0xC2F, z_ucmp, GR32, uimm32>;
1130  def CLIH  : CompareRIL<"clih",  0xCCF, z_ucmp, GR32, uimm32>,
1131              Requires<[FeatureHighWord]>;
1132  def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>;
1133
1134  // Comparison with memory.
1135  def  CLMux  : CompareRXYPseudo<z_ucmp, GRX32, load, 4>,
1136                Requires<[FeatureHighWord]>;
1137  defm CL     : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>;
1138  def  CLHF   : CompareRXY<"clhf", 0xE3CF, z_ucmp, GRH32, load, 4>,
1139                Requires<[FeatureHighWord]>;
1140  def  CLGF   : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, azextloadi32, 4>;
1141  def  CLG    : CompareRXY<"clg",  0xE321, z_ucmp, GR64, load, 8>;
1142  def  CLHRL  : CompareRILPC<"clhrl",  0xC67, z_ucmp, GR32,
1143                             aligned_azextloadi16>;
1144  def  CLRL   : CompareRILPC<"clrl",   0xC6F, z_ucmp, GR32,
1145                             aligned_load>;
1146  def  CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64,
1147                             aligned_azextloadi16>;
1148  def  CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64,
1149                             aligned_azextloadi32>;
1150  def  CLGRL  : CompareRILPC<"clgrl",  0xC6A, z_ucmp, GR64,
1151                             aligned_load>;
1152
1153  // Comparison between memory and an unsigned 8-bit immediate.
1154  defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, azextloadi8, imm32zx8>;
1155
1156  // Comparison between memory and an unsigned 16-bit immediate.
1157  def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, azextloadi16, imm32zx16>;
1158  def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>;
1159  def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>;
1160}
1161defm : ZXB<z_ucmp, GR64, CLGFR>;
1162
1163// Memory-to-memory comparison.
1164let mayLoad = 1, Defs = [CC] in
1165  defm CLC : MemorySS<"clc", 0xD5, z_clc, z_clc_loop>;
1166
1167// String comparison.
1168let mayLoad = 1, Defs = [CC], Uses = [R0L] in
1169  defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>;
1170
1171// Test under mask.
1172let Defs = [CC] in {
1173  // TMxMux expands to TM[LH]x, depending on the choice of register.
1174  def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>,
1175               Requires<[FeatureHighWord]>;
1176  def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>,
1177               Requires<[FeatureHighWord]>;
1178  def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>;
1179  def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>;
1180  def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>;
1181  def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>;
1182
1183  def TMLL64 : CompareAliasRI<z_tm_reg, GR64, imm64ll16>;
1184  def TMLH64 : CompareAliasRI<z_tm_reg, GR64, imm64lh16>;
1185  def TMHL64 : CompareAliasRI<z_tm_reg, GR64, imm64hl16>;
1186  def TMHH64 : CompareAliasRI<z_tm_reg, GR64, imm64hh16>;
1187
1188  defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>;
1189}
1190
1191//===----------------------------------------------------------------------===//
1192// Prefetch
1193//===----------------------------------------------------------------------===//
1194
1195def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>;
1196def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>;
1197
1198//===----------------------------------------------------------------------===//
1199// Atomic operations
1200//===----------------------------------------------------------------------===//
1201
1202def Serialize : Alias<2, (outs), (ins), [(z_serialize)]>;
1203
1204let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in {
1205  def LAA   : LoadAndOpRSY<"laa",   0xEBF8, atomic_load_add_32, GR32>;
1206  def LAAG  : LoadAndOpRSY<"laag",  0xEBE8, atomic_load_add_64, GR64>;
1207  def LAAL  : LoadAndOpRSY<"laal",  0xEBFA, null_frag, GR32>;
1208  def LAALG : LoadAndOpRSY<"laalg", 0xEBEA, null_frag, GR64>;
1209  def LAN   : LoadAndOpRSY<"lan",   0xEBF4, atomic_load_and_32, GR32>;
1210  def LANG  : LoadAndOpRSY<"lang",  0xEBE4, atomic_load_and_64, GR64>;
1211  def LAO   : LoadAndOpRSY<"lao",   0xEBF6, atomic_load_or_32, GR32>;
1212  def LAOG  : LoadAndOpRSY<"laog",  0xEBE6, atomic_load_or_64, GR64>;
1213  def LAX   : LoadAndOpRSY<"lax",   0xEBF7, atomic_load_xor_32, GR32>;
1214  def LAXG  : LoadAndOpRSY<"laxg",  0xEBE7, atomic_load_xor_64, GR64>;
1215}
1216
1217def ATOMIC_SWAPW   : AtomicLoadWBinaryReg<z_atomic_swapw>;
1218def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>;
1219def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>;
1220
1221def ATOMIC_LOADW_AR  : AtomicLoadWBinaryReg<z_atomic_loadw_add>;
1222def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>;
1223let Predicates = [FeatureNoInterlockedAccess1] in {
1224  def ATOMIC_LOAD_AR   : AtomicLoadBinaryReg32<atomic_load_add_32>;
1225  def ATOMIC_LOAD_AHI  : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>;
1226  def ATOMIC_LOAD_AFI  : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>;
1227  def ATOMIC_LOAD_AGR  : AtomicLoadBinaryReg64<atomic_load_add_64>;
1228  def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>;
1229  def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>;
1230}
1231
1232def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>;
1233def ATOMIC_LOAD_SR  : AtomicLoadBinaryReg32<atomic_load_sub_32>;
1234def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>;
1235
1236def ATOMIC_LOADW_NR   : AtomicLoadWBinaryReg<z_atomic_loadw_and>;
1237def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>;
1238let Predicates = [FeatureNoInterlockedAccess1] in {
1239  def ATOMIC_LOAD_NR     : AtomicLoadBinaryReg32<atomic_load_and_32>;
1240  def ATOMIC_LOAD_NILL   : AtomicLoadBinaryImm32<atomic_load_and_32,
1241                                                 imm32ll16c>;
1242  def ATOMIC_LOAD_NILH   : AtomicLoadBinaryImm32<atomic_load_and_32,
1243                                                 imm32lh16c>;
1244  def ATOMIC_LOAD_NILF   : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>;
1245  def ATOMIC_LOAD_NGR    : AtomicLoadBinaryReg64<atomic_load_and_64>;
1246  def ATOMIC_LOAD_NILL64 : AtomicLoadBinaryImm64<atomic_load_and_64,
1247                                                 imm64ll16c>;
1248  def ATOMIC_LOAD_NILH64 : AtomicLoadBinaryImm64<atomic_load_and_64,
1249                                                 imm64lh16c>;
1250  def ATOMIC_LOAD_NIHL64 : AtomicLoadBinaryImm64<atomic_load_and_64,
1251                                                 imm64hl16c>;
1252  def ATOMIC_LOAD_NIHH64 : AtomicLoadBinaryImm64<atomic_load_and_64,
1253                                                 imm64hh16c>;
1254  def ATOMIC_LOAD_NILF64 : AtomicLoadBinaryImm64<atomic_load_and_64,
1255                                                 imm64lf32c>;
1256  def ATOMIC_LOAD_NIHF64 : AtomicLoadBinaryImm64<atomic_load_and_64,
1257                                                 imm64hf32c>;
1258}
1259
1260def ATOMIC_LOADW_OR     : AtomicLoadWBinaryReg<z_atomic_loadw_or>;
1261def ATOMIC_LOADW_OILH   : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>;
1262let Predicates = [FeatureNoInterlockedAccess1] in {
1263  def ATOMIC_LOAD_OR     : AtomicLoadBinaryReg32<atomic_load_or_32>;
1264  def ATOMIC_LOAD_OILL   : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>;
1265  def ATOMIC_LOAD_OILH   : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>;
1266  def ATOMIC_LOAD_OILF   : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>;
1267  def ATOMIC_LOAD_OGR    : AtomicLoadBinaryReg64<atomic_load_or_64>;
1268  def ATOMIC_LOAD_OILL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>;
1269  def ATOMIC_LOAD_OILH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>;
1270  def ATOMIC_LOAD_OIHL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>;
1271  def ATOMIC_LOAD_OIHH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>;
1272  def ATOMIC_LOAD_OILF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>;
1273  def ATOMIC_LOAD_OIHF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>;
1274}
1275
1276def ATOMIC_LOADW_XR     : AtomicLoadWBinaryReg<z_atomic_loadw_xor>;
1277def ATOMIC_LOADW_XILF   : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>;
1278let Predicates = [FeatureNoInterlockedAccess1] in {
1279  def ATOMIC_LOAD_XR     : AtomicLoadBinaryReg32<atomic_load_xor_32>;
1280  def ATOMIC_LOAD_XILF   : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>;
1281  def ATOMIC_LOAD_XGR    : AtomicLoadBinaryReg64<atomic_load_xor_64>;
1282  def ATOMIC_LOAD_XILF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>;
1283  def ATOMIC_LOAD_XIHF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>;
1284}
1285
1286def ATOMIC_LOADW_NRi    : AtomicLoadWBinaryReg<z_atomic_loadw_nand>;
1287def ATOMIC_LOADW_NILHi  : AtomicLoadWBinaryImm<z_atomic_loadw_nand,
1288                                               imm32lh16c>;
1289def ATOMIC_LOAD_NRi     : AtomicLoadBinaryReg32<atomic_load_nand_32>;
1290def ATOMIC_LOAD_NILLi   : AtomicLoadBinaryImm32<atomic_load_nand_32,
1291                                                imm32ll16c>;
1292def ATOMIC_LOAD_NILHi   : AtomicLoadBinaryImm32<atomic_load_nand_32,
1293                                                imm32lh16c>;
1294def ATOMIC_LOAD_NILFi   : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>;
1295def ATOMIC_LOAD_NGRi    : AtomicLoadBinaryReg64<atomic_load_nand_64>;
1296def ATOMIC_LOAD_NILL64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1297                                                imm64ll16c>;
1298def ATOMIC_LOAD_NILH64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1299                                                imm64lh16c>;
1300def ATOMIC_LOAD_NIHL64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1301                                                imm64hl16c>;
1302def ATOMIC_LOAD_NIHH64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1303                                                imm64hh16c>;
1304def ATOMIC_LOAD_NILF64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1305                                                imm64lf32c>;
1306def ATOMIC_LOAD_NIHF64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1307                                                imm64hf32c>;
1308
1309def ATOMIC_LOADW_MIN    : AtomicLoadWBinaryReg<z_atomic_loadw_min>;
1310def ATOMIC_LOAD_MIN_32  : AtomicLoadBinaryReg32<atomic_load_min_32>;
1311def ATOMIC_LOAD_MIN_64  : AtomicLoadBinaryReg64<atomic_load_min_64>;
1312
1313def ATOMIC_LOADW_MAX    : AtomicLoadWBinaryReg<z_atomic_loadw_max>;
1314def ATOMIC_LOAD_MAX_32  : AtomicLoadBinaryReg32<atomic_load_max_32>;
1315def ATOMIC_LOAD_MAX_64  : AtomicLoadBinaryReg64<atomic_load_max_64>;
1316
1317def ATOMIC_LOADW_UMIN   : AtomicLoadWBinaryReg<z_atomic_loadw_umin>;
1318def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>;
1319def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>;
1320
1321def ATOMIC_LOADW_UMAX   : AtomicLoadWBinaryReg<z_atomic_loadw_umax>;
1322def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>;
1323def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>;
1324
1325def ATOMIC_CMP_SWAPW
1326  : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
1327                                  ADDR32:$bitshift, ADDR32:$negbitshift,
1328                                  uimm32:$bitsize),
1329           [(set GR32:$dst,
1330                 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
1331                                     ADDR32:$bitshift, ADDR32:$negbitshift,
1332                                     uimm32:$bitsize))]> {
1333  let Defs = [CC];
1334  let mayLoad = 1;
1335  let mayStore = 1;
1336  let usesCustomInserter = 1;
1337}
1338
1339let Defs = [CC] in {
1340  defm CS  : CmpSwapRSPair<"cs", 0xBA, 0xEB14, atomic_cmp_swap_32, GR32>;
1341  def  CSG : CmpSwapRSY<"csg", 0xEB30, atomic_cmp_swap_64, GR64>;
1342}
1343
1344//===----------------------------------------------------------------------===//
1345// Miscellaneous Instructions.
1346//===----------------------------------------------------------------------===//
1347
1348// Extract CC into bits 29 and 28 of a register.
1349let Uses = [CC] in
1350  def IPM : InherentRRE<"ipm", 0xB222, GR32, (z_ipm)>;
1351
1352// Read a 32-bit access register into a GR32.  As with all GR32 operations,
1353// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful
1354// when a 64-bit address is stored in a pair of access registers.
1355def EAR : InstRRE<0xB24F, (outs GR32:$R1), (ins access_reg:$R2),
1356                  "ear\t$R1, $R2",
1357                  [(set GR32:$R1, (z_extract_access access_reg:$R2))]>;
1358
1359// Find leftmost one, AKA count leading zeros.  The instruction actually
1360// returns a pair of GR64s, the first giving the number of leading zeros
1361// and the second giving a copy of the source with the leftmost one bit
1362// cleared.  We only use the first result here.
1363let Defs = [CC] in {
1364  def FLOGR : UnaryRRE<"flog", 0xB983, null_frag, GR128, GR64>;
1365}
1366def : Pat<(ctlz GR64:$src),
1367          (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>;
1368
1369// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext.
1370def : Pat<(i64 (anyext GR32:$src)),
1371          (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>;
1372
1373// Extend GR32s and GR64s to GR128s.
1374let usesCustomInserter = 1 in {
1375  def AEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
1376  def ZEXT128_32 : Pseudo<(outs GR128:$dst), (ins GR32:$src), []>;
1377  def ZEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
1378}
1379
1380// Search a block of memory for a character.
1381let mayLoad = 1, Defs = [CC], Uses = [R0L] in
1382  defm SRST : StringRRE<"srst", 0xb25e, z_search_string>;
1383
1384//===----------------------------------------------------------------------===//
1385// Peepholes.
1386//===----------------------------------------------------------------------===//
1387
1388// Use AL* for GR64 additions of unsigned 32-bit values.
1389defm : ZXB<add, GR64, ALGFR>;
1390def  : Pat<(add GR64:$src1, imm64zx32:$src2),
1391           (ALGFI GR64:$src1, imm64zx32:$src2)>;
1392def  : Pat<(add GR64:$src1, (azextloadi32 bdxaddr20only:$addr)),
1393           (ALGF GR64:$src1, bdxaddr20only:$addr)>;
1394
1395// Use SL* for GR64 subtractions of unsigned 32-bit values.
1396defm : ZXB<sub, GR64, SLGFR>;
1397def  : Pat<(add GR64:$src1, imm64zx32n:$src2),
1398           (SLGFI GR64:$src1, imm64zx32n:$src2)>;
1399def  : Pat<(sub GR64:$src1, (azextloadi32 bdxaddr20only:$addr)),
1400           (SLGF GR64:$src1, bdxaddr20only:$addr)>;
1401
1402// Optimize sign-extended 1/0 selects to -1/0 selects.  This is important
1403// for vector legalization.
1404def : Pat<(sra (shl (i32 (z_select_ccmask 1, 0, imm32zx4:$valid, imm32zx4:$cc)),
1405                         (i32 31)),
1406                    (i32 31)),
1407          (Select32 (LHI -1), (LHI 0), imm32zx4:$valid, imm32zx4:$cc)>;
1408def : Pat<(sra (shl (i64 (anyext (i32 (z_select_ccmask 1, 0, imm32zx4:$valid,
1409                                                       imm32zx4:$cc)))),
1410                    (i32 63)),
1411               (i32 63)),
1412          (Select64 (LGHI -1), (LGHI 0), imm32zx4:$valid, imm32zx4:$cc)>;
1413
1414// Peepholes for turning scalar operations into block operations.
1415defm : BlockLoadStore<anyextloadi8, i32, MVCSequence, NCSequence, OCSequence,
1416                      XCSequence, 1>;
1417defm : BlockLoadStore<anyextloadi16, i32, MVCSequence, NCSequence, OCSequence,
1418                      XCSequence, 2>;
1419defm : BlockLoadStore<load, i32, MVCSequence, NCSequence, OCSequence,
1420                      XCSequence, 4>;
1421defm : BlockLoadStore<anyextloadi8, i64, MVCSequence, NCSequence,
1422                      OCSequence, XCSequence, 1>;
1423defm : BlockLoadStore<anyextloadi16, i64, MVCSequence, NCSequence, OCSequence,
1424                      XCSequence, 2>;
1425defm : BlockLoadStore<anyextloadi32, i64, MVCSequence, NCSequence, OCSequence,
1426                      XCSequence, 4>;
1427defm : BlockLoadStore<load, i64, MVCSequence, NCSequence, OCSequence,
1428                      XCSequence, 8>;
1429