SystemZOperands.td revision 65ddcfa8c1c05aeecd9d4fb062bb121e376aaceb
1//===-- SystemZOperands.td - SystemZ instruction operands ----*- tblgen-*--===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Class definitions 12//===----------------------------------------------------------------------===// 13 14class ImmediateAsmOperand<string name> 15 : AsmOperandClass { 16 let Name = name; 17 let RenderMethod = "addImmOperands"; 18} 19 20// Constructs both a DAG pattern and instruction operand for an immediate 21// of type VT. PRED returns true if a node is acceptable and XFORM returns 22// the operand value associated with the node. ASMOP is the name of the 23// associated asm operand, and also forms the basis of the asm print method. 24class Immediate<ValueType vt, code pred, SDNodeXForm xform, string asmop> 25 : PatLeaf<(vt imm), pred, xform>, Operand<vt> { 26 let PrintMethod = "print"##asmop##"Operand"; 27 let DecoderMethod = "decode"##asmop##"Operand"; 28 let ParserMatchClass = !cast<AsmOperandClass>(asmop); 29} 30 31// Constructs an asm operand for a PC-relative address. SIZE says how 32// many bits there are. 33class PCRelAsmOperand<string size> : ImmediateAsmOperand<"PCRel"##size> { 34 let PredicateMethod = "isImm"; 35 let ParserMethod = "parsePCRel"##size; 36} 37 38// Constructs an operand for a PC-relative address with address type VT. 39// ASMOP is the associated asm operand. 40class PCRelOperand<ValueType vt, AsmOperandClass asmop> : Operand<vt> { 41 let PrintMethod = "printPCRelOperand"; 42 let ParserMatchClass = asmop; 43} 44 45// Constructs both a DAG pattern and instruction operand for a PC-relative 46// address with address size VT. SELF is the name of the operand and 47// ASMOP is the associated asm operand. 48class PCRelAddress<ValueType vt, string self, AsmOperandClass asmop> 49 : ComplexPattern<vt, 1, "selectPCRelAddress", [z_pcrel_wrapper]>, 50 PCRelOperand<vt, asmop> { 51 let MIOperandInfo = (ops !cast<Operand>(self)); 52} 53 54// Constructs an AsmOperandClass for addressing mode FORMAT, treating the 55// registers as having BITSIZE bits and displacements as having DISPSIZE bits. 56// LENGTH is "LenN" for addresses with an N-bit length field, otherwise it 57// is "". 58class AddressAsmOperand<string format, string bitsize, string dispsize, 59 string length = ""> 60 : AsmOperandClass { 61 let Name = format##bitsize##"Disp"##dispsize##length; 62 let ParserMethod = "parse"##format##bitsize; 63 let RenderMethod = "add"##format##"Operands"; 64} 65 66// Constructs both a DAG pattern and instruction operand for an addressing mode. 67// FORMAT, BITSIZE, DISPSIZE and LENGTH are the parameters to an associated 68// AddressAsmOperand. OPERANDS is a list of NUMOPS individual operands 69// (base register, displacement, etc.). SELTYPE is the type of the memory 70// operand for selection purposes; sometimes we want different selection 71// choices for the same underlying addressing mode. SUFFIX is similarly 72// a suffix appended to the displacement for selection purposes; 73// e.g. we want to reject small 20-bit displacements if a 12-bit form 74// also exists, but we want to accept them otherwise. 75class AddressingMode<string seltype, string bitsize, string dispsize, 76 string suffix, string length, int numops, string format, 77 dag operands> 78 : ComplexPattern<!cast<ValueType>("i"##bitsize), numops, 79 "select"##seltype##dispsize##suffix##length, 80 [add, sub, or, frameindex, z_adjdynalloc]>, 81 Operand<!cast<ValueType>("i"##bitsize)> { 82 let PrintMethod = "print"##format##"Operand"; 83 let EncoderMethod = "get"##format##dispsize##length##"Encoding"; 84 let DecoderMethod = 85 "decode"##format##bitsize##"Disp"##dispsize##length##"Operand"; 86 let MIOperandInfo = operands; 87 let ParserMatchClass = 88 !cast<AddressAsmOperand>(format##bitsize##"Disp"##dispsize##length); 89} 90 91// An addressing mode with a base and displacement but no index. 92class BDMode<string type, string bitsize, string dispsize, string suffix> 93 : AddressingMode<type, bitsize, dispsize, suffix, "", 2, "BDAddr", 94 (ops !cast<RegisterOperand>("ADDR"##bitsize), 95 !cast<Immediate>("disp"##dispsize##"imm"##bitsize))>; 96 97// An addressing mode with a base, displacement and index. 98class BDXMode<string type, string bitsize, string dispsize, string suffix> 99 : AddressingMode<type, bitsize, dispsize, suffix, "", 3, "BDXAddr", 100 (ops !cast<RegisterOperand>("ADDR"##bitsize), 101 !cast<Immediate>("disp"##dispsize##"imm"##bitsize), 102 !cast<RegisterOperand>("ADDR"##bitsize))>; 103 104// A BDMode paired with an immediate length operand of LENSIZE bits. 105class BDLMode<string type, string bitsize, string dispsize, string suffix, 106 string lensize> 107 : AddressingMode<type, bitsize, dispsize, suffix, "Len"##lensize, 3, 108 "BDLAddr", 109 (ops !cast<RegisterOperand>("ADDR"##bitsize), 110 !cast<Immediate>("disp"##dispsize##"imm"##bitsize), 111 !cast<Immediate>("imm"##bitsize))>; 112 113//===----------------------------------------------------------------------===// 114// Extracting immediate operands from nodes 115// These all create MVT::i64 nodes to ensure the value is not sign-extended 116// when converted from an SDNode to a MachineOperand later on. 117//===----------------------------------------------------------------------===// 118 119// Bits 0-15 (counting from the lsb). 120def LL16 : SDNodeXForm<imm, [{ 121 uint64_t Value = N->getZExtValue() & 0x000000000000FFFFULL; 122 return CurDAG->getTargetConstant(Value, MVT::i64); 123}]>; 124 125// Bits 16-31 (counting from the lsb). 126def LH16 : SDNodeXForm<imm, [{ 127 uint64_t Value = (N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16; 128 return CurDAG->getTargetConstant(Value, MVT::i64); 129}]>; 130 131// Bits 32-47 (counting from the lsb). 132def HL16 : SDNodeXForm<imm, [{ 133 uint64_t Value = (N->getZExtValue() & 0x0000FFFF00000000ULL) >> 32; 134 return CurDAG->getTargetConstant(Value, MVT::i64); 135}]>; 136 137// Bits 48-63 (counting from the lsb). 138def HH16 : SDNodeXForm<imm, [{ 139 uint64_t Value = (N->getZExtValue() & 0xFFFF000000000000ULL) >> 48; 140 return CurDAG->getTargetConstant(Value, MVT::i64); 141}]>; 142 143// Low 32 bits. 144def LF32 : SDNodeXForm<imm, [{ 145 uint64_t Value = N->getZExtValue() & 0x00000000FFFFFFFFULL; 146 return CurDAG->getTargetConstant(Value, MVT::i64); 147}]>; 148 149// High 32 bits. 150def HF32 : SDNodeXForm<imm, [{ 151 uint64_t Value = N->getZExtValue() >> 32; 152 return CurDAG->getTargetConstant(Value, MVT::i64); 153}]>; 154 155// Truncate an immediate to a 8-bit signed quantity. 156def SIMM8 : SDNodeXForm<imm, [{ 157 return CurDAG->getTargetConstant(int8_t(N->getZExtValue()), MVT::i64); 158}]>; 159 160// Truncate an immediate to a 8-bit unsigned quantity. 161def UIMM8 : SDNodeXForm<imm, [{ 162 return CurDAG->getTargetConstant(uint8_t(N->getZExtValue()), MVT::i64); 163}]>; 164 165// Truncate an immediate to a 16-bit signed quantity. 166def SIMM16 : SDNodeXForm<imm, [{ 167 return CurDAG->getTargetConstant(int16_t(N->getZExtValue()), MVT::i64); 168}]>; 169 170// Truncate an immediate to a 16-bit unsigned quantity. 171def UIMM16 : SDNodeXForm<imm, [{ 172 return CurDAG->getTargetConstant(uint16_t(N->getZExtValue()), MVT::i64); 173}]>; 174 175// Truncate an immediate to a 32-bit signed quantity. 176def SIMM32 : SDNodeXForm<imm, [{ 177 return CurDAG->getTargetConstant(int32_t(N->getZExtValue()), MVT::i64); 178}]>; 179 180// Truncate an immediate to a 32-bit unsigned quantity. 181def UIMM32 : SDNodeXForm<imm, [{ 182 return CurDAG->getTargetConstant(uint32_t(N->getZExtValue()), MVT::i64); 183}]>; 184 185// Negate and then truncate an immediate to a 32-bit unsigned quantity. 186def NEGIMM32 : SDNodeXForm<imm, [{ 187 return CurDAG->getTargetConstant(uint32_t(-N->getZExtValue()), MVT::i64); 188}]>; 189 190//===----------------------------------------------------------------------===// 191// Immediate asm operands. 192//===----------------------------------------------------------------------===// 193 194def U4Imm : ImmediateAsmOperand<"U4Imm">; 195def U6Imm : ImmediateAsmOperand<"U6Imm">; 196def S8Imm : ImmediateAsmOperand<"S8Imm">; 197def U8Imm : ImmediateAsmOperand<"U8Imm">; 198def S16Imm : ImmediateAsmOperand<"S16Imm">; 199def U16Imm : ImmediateAsmOperand<"U16Imm">; 200def S32Imm : ImmediateAsmOperand<"S32Imm">; 201def U32Imm : ImmediateAsmOperand<"U32Imm">; 202 203//===----------------------------------------------------------------------===// 204// 8-bit immediates 205//===----------------------------------------------------------------------===// 206 207def uimm8zx4 : Immediate<i8, [{ 208 return isUInt<4>(N->getZExtValue()); 209}], NOOP_SDNodeXForm, "U4Imm">; 210 211def uimm8zx6 : Immediate<i8, [{ 212 return isUInt<6>(N->getZExtValue()); 213}], NOOP_SDNodeXForm, "U6Imm">; 214 215def simm8 : Immediate<i8, [{}], SIMM8, "S8Imm">; 216def uimm8 : Immediate<i8, [{}], UIMM8, "U8Imm">; 217 218//===----------------------------------------------------------------------===// 219// i32 immediates 220//===----------------------------------------------------------------------===// 221 222// Immediates for 8-bit lengths. 223def imm32len8 : Immediate<i32, [{ 224 return isUInt<8>(N->getZExtValue() - 1); 225}], NOOP_SDNodeXForm, "U32Imm">; 226 227// Immediates for the lower and upper 16 bits of an i32, with the other 228// bits of the i32 being zero. 229def imm32ll16 : Immediate<i32, [{ 230 return SystemZ::isImmLL(N->getZExtValue()); 231}], LL16, "U16Imm">; 232 233def imm32lh16 : Immediate<i32, [{ 234 return SystemZ::isImmLH(N->getZExtValue()); 235}], LH16, "U16Imm">; 236 237// Immediates for the lower and upper 16 bits of an i32, with the other 238// bits of the i32 being one. 239def imm32ll16c : Immediate<i32, [{ 240 return SystemZ::isImmLL(uint32_t(~N->getZExtValue())); 241}], LL16, "U16Imm">; 242 243def imm32lh16c : Immediate<i32, [{ 244 return SystemZ::isImmLH(uint32_t(~N->getZExtValue())); 245}], LH16, "U16Imm">; 246 247// Short immediates 248def imm32sx8 : Immediate<i32, [{ 249 return isInt<8>(N->getSExtValue()); 250}], SIMM8, "S8Imm">; 251 252def imm32zx8 : Immediate<i32, [{ 253 return isUInt<8>(N->getZExtValue()); 254}], UIMM8, "U8Imm">; 255 256def imm32zx8trunc : Immediate<i32, [{}], UIMM8, "U8Imm">; 257 258def imm32sx16 : Immediate<i32, [{ 259 return isInt<16>(N->getSExtValue()); 260}], SIMM16, "S16Imm">; 261 262def imm32zx16 : Immediate<i32, [{ 263 return isUInt<16>(N->getZExtValue()); 264}], UIMM16, "U16Imm">; 265 266def imm32sx16trunc : Immediate<i32, [{}], SIMM16, "S16Imm">; 267 268// Full 32-bit immediates. we need both signed and unsigned versions 269// because the assembler is picky. E.g. AFI requires signed operands 270// while NILF requires unsigned ones. 271def simm32 : Immediate<i32, [{}], SIMM32, "S32Imm">; 272def uimm32 : Immediate<i32, [{}], UIMM32, "U32Imm">; 273 274def imm32 : ImmLeaf<i32, [{}]>; 275 276//===----------------------------------------------------------------------===// 277// 64-bit immediates 278//===----------------------------------------------------------------------===// 279 280// Immediates for 16-bit chunks of an i64, with the other bits of the 281// i32 being zero. 282def imm64ll16 : Immediate<i64, [{ 283 return SystemZ::isImmLL(N->getZExtValue()); 284}], LL16, "U16Imm">; 285 286def imm64lh16 : Immediate<i64, [{ 287 return SystemZ::isImmLH(N->getZExtValue()); 288}], LH16, "U16Imm">; 289 290def imm64hl16 : Immediate<i64, [{ 291 return SystemZ::isImmHL(N->getZExtValue()); 292}], HL16, "U16Imm">; 293 294def imm64hh16 : Immediate<i64, [{ 295 return SystemZ::isImmHH(N->getZExtValue()); 296}], HH16, "U16Imm">; 297 298// Immediates for 16-bit chunks of an i64, with the other bits of the 299// i32 being one. 300def imm64ll16c : Immediate<i64, [{ 301 return SystemZ::isImmLL(uint64_t(~N->getZExtValue())); 302}], LL16, "U16Imm">; 303 304def imm64lh16c : Immediate<i64, [{ 305 return SystemZ::isImmLH(uint64_t(~N->getZExtValue())); 306}], LH16, "U16Imm">; 307 308def imm64hl16c : Immediate<i64, [{ 309 return SystemZ::isImmHL(uint64_t(~N->getZExtValue())); 310}], HL16, "U16Imm">; 311 312def imm64hh16c : Immediate<i64, [{ 313 return SystemZ::isImmHH(uint64_t(~N->getZExtValue())); 314}], HH16, "U16Imm">; 315 316// Immediates for the lower and upper 32 bits of an i64, with the other 317// bits of the i32 being zero. 318def imm64lf32 : Immediate<i64, [{ 319 return SystemZ::isImmLF(N->getZExtValue()); 320}], LF32, "U32Imm">; 321 322def imm64hf32 : Immediate<i64, [{ 323 return SystemZ::isImmHF(N->getZExtValue()); 324}], HF32, "U32Imm">; 325 326// Immediates for the lower and upper 32 bits of an i64, with the other 327// bits of the i32 being one. 328def imm64lf32c : Immediate<i64, [{ 329 return SystemZ::isImmLF(uint64_t(~N->getZExtValue())); 330}], LF32, "U32Imm">; 331 332def imm64hf32c : Immediate<i64, [{ 333 return SystemZ::isImmHF(uint64_t(~N->getZExtValue())); 334}], HF32, "U32Imm">; 335 336// Short immediates. 337def imm64sx8 : Immediate<i64, [{ 338 return isInt<8>(N->getSExtValue()); 339}], SIMM8, "S8Imm">; 340 341def imm64sx16 : Immediate<i64, [{ 342 return isInt<16>(N->getSExtValue()); 343}], SIMM16, "S16Imm">; 344 345def imm64zx16 : Immediate<i64, [{ 346 return isUInt<16>(N->getZExtValue()); 347}], UIMM16, "U16Imm">; 348 349def imm64sx32 : Immediate<i64, [{ 350 return isInt<32>(N->getSExtValue()); 351}], SIMM32, "S32Imm">; 352 353def imm64zx32 : Immediate<i64, [{ 354 return isUInt<32>(N->getZExtValue()); 355}], UIMM32, "U32Imm">; 356 357def imm64zx32n : Immediate<i64, [{ 358 return isUInt<32>(-N->getSExtValue()); 359}], NEGIMM32, "U32Imm">; 360 361def imm64 : ImmLeaf<i64, [{}]>; 362 363//===----------------------------------------------------------------------===// 364// Floating-point immediates 365//===----------------------------------------------------------------------===// 366 367// Floating-point zero. 368def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>; 369 370// Floating point negative zero. 371def fpimmneg0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(-0.0); }]>; 372 373//===----------------------------------------------------------------------===// 374// Symbolic address operands 375//===----------------------------------------------------------------------===// 376 377// PC-relative asm operands. 378def PCRel16 : PCRelAsmOperand<"16">; 379def PCRel32 : PCRelAsmOperand<"32">; 380 381// PC-relative offsets of a basic block. The offset is sign-extended 382// and multiplied by 2. 383def brtarget16 : PCRelOperand<OtherVT, PCRel16> { 384 let EncoderMethod = "getPC16DBLEncoding"; 385 let DecoderMethod = "decodePC16DBLOperand"; 386} 387def brtarget32 : PCRelOperand<OtherVT, PCRel32> { 388 let EncoderMethod = "getPC32DBLEncoding"; 389 let DecoderMethod = "decodePC32DBLOperand"; 390} 391 392// A PC-relative offset of a global value. The offset is sign-extended 393// and multiplied by 2. 394def pcrel32 : PCRelAddress<i64, "pcrel32", PCRel32> { 395 let EncoderMethod = "getPC32DBLEncoding"; 396 let DecoderMethod = "decodePC32DBLOperand"; 397} 398 399// A PC-relative offset of a global value when the value is used as a 400// call target. The offset is sign-extended and multiplied by 2. 401def pcrel16call : PCRelAddress<i64, "pcrel16call", PCRel16> { 402 let PrintMethod = "printCallOperand"; 403 let EncoderMethod = "getPLT16DBLEncoding"; 404 let DecoderMethod = "decodePC16DBLOperand"; 405} 406def pcrel32call : PCRelAddress<i64, "pcrel32call", PCRel32> { 407 let PrintMethod = "printCallOperand"; 408 let EncoderMethod = "getPLT32DBLEncoding"; 409 let DecoderMethod = "decodePC32DBLOperand"; 410} 411 412//===----------------------------------------------------------------------===// 413// Addressing modes 414//===----------------------------------------------------------------------===// 415 416// 12-bit displacement operands. 417def disp12imm32 : Operand<i32>; 418def disp12imm64 : Operand<i64>; 419 420// 20-bit displacement operands. 421def disp20imm32 : Operand<i32>; 422def disp20imm64 : Operand<i64>; 423 424def BDAddr32Disp12 : AddressAsmOperand<"BDAddr", "32", "12">; 425def BDAddr32Disp20 : AddressAsmOperand<"BDAddr", "32", "20">; 426def BDAddr64Disp12 : AddressAsmOperand<"BDAddr", "64", "12">; 427def BDAddr64Disp20 : AddressAsmOperand<"BDAddr", "64", "20">; 428def BDXAddr64Disp12 : AddressAsmOperand<"BDXAddr", "64", "12">; 429def BDXAddr64Disp20 : AddressAsmOperand<"BDXAddr", "64", "20">; 430def BDLAddr64Disp12Len8 : AddressAsmOperand<"BDLAddr", "64", "12", "Len8">; 431 432// DAG patterns and operands for addressing modes. Each mode has 433// the form <type><range><group>[<len>] where: 434// 435// <type> is one of: 436// shift : base + displacement (32-bit) 437// bdaddr : base + displacement 438// mviaddr : like bdaddr, but reject cases with a natural index 439// bdxaddr : base + displacement + index 440// laaddr : like bdxaddr, but used for Load Address operations 441// dynalloc : base + displacement + index + ADJDYNALLOC 442// bdladdr : base + displacement with a length field 443// 444// <range> is one of: 445// 12 : the displacement is an unsigned 12-bit value 446// 20 : the displacement is a signed 20-bit value 447// 448// <group> is one of: 449// pair : used when there is an equivalent instruction with the opposite 450// range value (12 or 20) 451// only : used when there is no equivalent instruction with the opposite 452// range value 453// 454// <len> is one of: 455// 456// <empty> : there is no length field 457// len8 : the length field is 8 bits, with a range of [1, 0x100]. 458def shift12only : BDMode <"BDAddr", "32", "12", "Only">; 459def shift20only : BDMode <"BDAddr", "32", "20", "Only">; 460def bdaddr12only : BDMode <"BDAddr", "64", "12", "Only">; 461def bdaddr12pair : BDMode <"BDAddr", "64", "12", "Pair">; 462def bdaddr20only : BDMode <"BDAddr", "64", "20", "Only">; 463def bdaddr20pair : BDMode <"BDAddr", "64", "20", "Pair">; 464def mviaddr12pair : BDMode <"MVIAddr", "64", "12", "Pair">; 465def mviaddr20pair : BDMode <"MVIAddr", "64", "20", "Pair">; 466def bdxaddr12only : BDXMode<"BDXAddr", "64", "12", "Only">; 467def bdxaddr12pair : BDXMode<"BDXAddr", "64", "12", "Pair">; 468def bdxaddr20only : BDXMode<"BDXAddr", "64", "20", "Only">; 469def bdxaddr20only128 : BDXMode<"BDXAddr", "64", "20", "Only128">; 470def bdxaddr20pair : BDXMode<"BDXAddr", "64", "20", "Pair">; 471def dynalloc12only : BDXMode<"DynAlloc", "64", "12", "Only">; 472def laaddr12pair : BDXMode<"LAAddr", "64", "12", "Pair">; 473def laaddr20pair : BDXMode<"LAAddr", "64", "20", "Pair">; 474def bdladdr12onlylen8 : BDLMode<"BDLAddr", "64", "12", "Only", "8">; 475 476//===----------------------------------------------------------------------===// 477// Miscellaneous 478//===----------------------------------------------------------------------===// 479 480// Access registers. At present we just use them for accessing the thread 481// pointer, so we don't expose them as register to LLVM. 482def AccessReg : AsmOperandClass { 483 let Name = "AccessReg"; 484 let ParserMethod = "parseAccessReg"; 485} 486def access_reg : Immediate<i8, [{ return N->getZExtValue() < 16; }], 487 NOOP_SDNodeXForm, "AccessReg"> { 488 let ParserMatchClass = AccessReg; 489} 490 491// A 4-bit condition-code mask. 492def cond4 : PatLeaf<(i8 imm), [{ return (N->getZExtValue() < 16); }]>, 493 Operand<i8> { 494 let PrintMethod = "printCond4Operand"; 495} 496