SystemZPatterns.td revision cf20e45cc4cb77bcb16363531e600883cd27ff80 
1//===-- SystemZPatterns.td - SystemZ-specific pattern rules ---*- tblgen-*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10// Record that INSN performs a 64-bit version of unary operator OPERATOR
11// in which the operand is sign-extended from 32 to 64 bits.
12multiclass SXU<SDPatternOperator operator, Instruction insn> {
13  def : Pat<(operator (sext (i32 GR32:$src))),
14            (insn GR32:$src)>;
15  def : Pat<(operator (sext_inreg GR64:$src, i32)),
16            (insn (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
17}
18
19// Record that INSN performs a 64-bit version of binary operator OPERATOR
20// in which the first operand has class CLS and which the second operand
21// is sign-extended from a 32-bit register.
22multiclass SXB<SDPatternOperator operator, RegisterOperand cls,
23               Instruction insn> {
24  def : Pat<(operator cls:$src1, (sext GR32:$src2)),
25            (insn cls:$src1, GR32:$src2)>;
26  def : Pat<(operator cls:$src1, (sext_inreg GR64:$src2, i32)),
27            (insn cls:$src1, (EXTRACT_SUBREG GR64:$src2, subreg_32bit))>;
28}
29
30// Like SXB, but for zero extension.
31multiclass ZXB<SDPatternOperator operator, RegisterOperand cls,
32               Instruction insn> {
33  def : Pat<(operator cls:$src1, (zext GR32:$src2)),
34            (insn cls:$src1, GR32:$src2)>;
35  def : Pat<(operator cls:$src1, (and GR64:$src2, 0xffffffff)),
36            (insn cls:$src1, (EXTRACT_SUBREG GR64:$src2, subreg_32bit))>;
37}
38
39// Record that INSN performs a binary read-modify-write operation,
40// with LOAD, OPERATOR and STORE being the read, modify and write
41// respectively.  MODE is the addressing mode and IMM is the type
42// of the second operand.
43class RMWI<SDPatternOperator load, SDPatternOperator operator,
44           SDPatternOperator store, AddressingMode mode,
45           PatFrag imm, Instruction insn>
46  : Pat<(store (operator (load mode:$addr), imm:$src), mode:$addr),
47        (insn mode:$addr, (UIMM8 imm:$src))>;
48
49// Record that INSN performs binary operation OPERATION on a byte
50// memory location.  IMM is the type of the second operand.
51multiclass RMWIByte<SDPatternOperator operator, AddressingMode mode,
52                    Instruction insn> {
53  def : RMWI<anyextloadi8, operator, truncstorei8, mode, imm32, insn>;
54  def : RMWI<anyextloadi8, operator, truncstorei8, mode, imm64, insn>;
55}
56
57// Record that INSN conditionally performs load operation LOAD into a
58// register of class CLS.  The load may trap even if the condition is false.
59multiclass CondLoad<Instruction insn, RegisterOperand cls,
60                    SDPatternOperator load> {
61  def : Pat<(z_select_ccmask (load bdaddr20only:$addr), cls:$new, uimm8zx4:$cc),
62            (insn cls:$new, bdaddr20only:$addr, uimm8zx4:$cc)>,
63        Requires<[FeatureLoadStoreOnCond]>;
64  def : Pat<(z_select_ccmask cls:$new, (load bdaddr20only:$addr), uimm8zx4:$cc),
65            (insn cls:$new, bdaddr20only:$addr, (INVCC uimm8zx4:$cc))>,
66        Requires<[FeatureLoadStoreOnCond]>;
67}
68
69// Record that INSN performs insertion TYPE into a register of class CLS.
70// The inserted operand is loaded using LOAD from an address of mode MODE.
71multiclass InsertMem<string type, Instruction insn, RegisterOperand cls,
72                     SDPatternOperator load, AddressingMode mode> {
73  def : Pat<(!cast<SDPatternOperator>("or_as_"##type)
74              cls:$src1, (load mode:$src2)),
75            (insn cls:$src1, mode:$src2)>;
76  def : Pat<(!cast<SDPatternOperator>("or_as_rev"##type)
77              (load mode:$src2), cls:$src1),
78            (insn cls:$src1, mode:$src2)>;
79}
80
81// Use MVC instruction INSN for a load of type LOAD followed by a store
82// of type STORE.  VT is the type of the intermediate register and LENGTH
83// is the number of bytes to copy (which may be smaller than VT).
84multiclass MVCLoadStore<SDPatternOperator load, SDPatternOperator store,
85                        ValueType vt, Instruction insn, bits<5> length> {
86  def Pat : PatFrag<(ops node:$dest, node:$src),
87                    (store (vt (load node:$src)), node:$dest),
88                    [{ return storeLoadCanUseMVC(N); }]>;
89
90  def : Pat<(!cast<SDPatternOperator>(NAME##"Pat") bdaddr12only:$dest,
91                                                   bdaddr12only:$src),
92            (insn bdaddr12only:$dest, bdaddr12only:$src, length)>;
93}
94