SystemZRegisterInfo.cpp revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f 
1//===-- SystemZRegisterInfo.cpp - SystemZ register information ------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "SystemZRegisterInfo.h"
11#include "SystemZTargetMachine.h"
12#include "llvm/CodeGen/MachineInstrBuilder.h"
13#include "llvm/CodeGen/MachineRegisterInfo.h"
14
15using namespace llvm;
16
17#define GET_REGINFO_TARGET_DESC
18#include "SystemZGenRegisterInfo.inc"
19
20SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm)
21  : SystemZGenRegisterInfo(SystemZ::R14D), TM(tm) {}
22
23const MCPhysReg*
24SystemZRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
25  static const MCPhysReg CalleeSavedRegs[] = {
26    SystemZ::R6D,  SystemZ::R7D,  SystemZ::R8D,  SystemZ::R9D,
27    SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D,
28    SystemZ::R14D, SystemZ::R15D,
29    SystemZ::F8D,  SystemZ::F9D,  SystemZ::F10D, SystemZ::F11D,
30    SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D,
31    0
32  };
33
34  return CalleeSavedRegs;
35}
36
37BitVector
38SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
39  BitVector Reserved(getNumRegs());
40  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
41
42  if (TFI->hasFP(MF)) {
43    // R11D is the frame pointer.  Reserve all aliases.
44    Reserved.set(SystemZ::R11D);
45    Reserved.set(SystemZ::R11L);
46    Reserved.set(SystemZ::R11H);
47    Reserved.set(SystemZ::R10Q);
48  }
49
50  // R15D is the stack pointer.  Reserve all aliases.
51  Reserved.set(SystemZ::R15D);
52  Reserved.set(SystemZ::R15L);
53  Reserved.set(SystemZ::R15H);
54  Reserved.set(SystemZ::R14Q);
55  return Reserved;
56}
57
58void
59SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
60                                         int SPAdj, unsigned FIOperandNum,
61                                         RegScavenger *RS) const {
62  assert(SPAdj == 0 && "Outgoing arguments should be part of the frame");
63
64  MachineBasicBlock &MBB = *MI->getParent();
65  MachineFunction &MF = *MBB.getParent();
66  auto *TII = static_cast<const SystemZInstrInfo*>(TM.getInstrInfo());
67  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
68  DebugLoc DL = MI->getDebugLoc();
69
70  // Decompose the frame index into a base and offset.
71  int FrameIndex = MI->getOperand(FIOperandNum).getIndex();
72  unsigned BasePtr = getFrameRegister(MF);
73  int64_t Offset = (TFI->getFrameIndexOffset(MF, FrameIndex) +
74                    MI->getOperand(FIOperandNum + 1).getImm());
75
76  // Special handling of dbg_value instructions.
77  if (MI->isDebugValue()) {
78    MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, /*isDef*/ false);
79    MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
80    return;
81  }
82
83  // See if the offset is in range, or if an equivalent instruction that
84  // accepts the offset exists.
85  unsigned Opcode = MI->getOpcode();
86  unsigned OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
87  if (OpcodeForOffset)
88    MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
89  else {
90    // Create an anchor point that is in range.  Start at 0xffff so that
91    // can use LLILH to load the immediate.
92    int64_t OldOffset = Offset;
93    int64_t Mask = 0xffff;
94    do {
95      Offset = OldOffset & Mask;
96      OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
97      Mask >>= 1;
98      assert(Mask && "One offset must be OK");
99    } while (!OpcodeForOffset);
100
101    unsigned ScratchReg =
102      MF.getRegInfo().createVirtualRegister(&SystemZ::ADDR64BitRegClass);
103    int64_t HighOffset = OldOffset - Offset;
104
105    if (MI->getDesc().TSFlags & SystemZII::HasIndex
106        && MI->getOperand(FIOperandNum + 2).getReg() == 0) {
107      // Load the offset into the scratch register and use it as an index.
108      // The scratch register then dies here.
109      TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
110      MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
111      MI->getOperand(FIOperandNum + 2).ChangeToRegister(ScratchReg,
112                                                        false, false, true);
113    } else {
114      // Load the anchor address into a scratch register.
115      unsigned LAOpcode = TII->getOpcodeForOffset(SystemZ::LA, HighOffset);
116      if (LAOpcode)
117        BuildMI(MBB, MI, DL, TII->get(LAOpcode),ScratchReg)
118          .addReg(BasePtr).addImm(HighOffset).addReg(0);
119      else {
120        // Load the high offset into the scratch register and use it as
121        // an index.
122        TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
123        BuildMI(MBB, MI, DL, TII->get(SystemZ::AGR),ScratchReg)
124          .addReg(ScratchReg, RegState::Kill).addReg(BasePtr);
125      }
126
127      // Use the scratch register as the base.  It then dies here.
128      MI->getOperand(FIOperandNum).ChangeToRegister(ScratchReg,
129                                                    false, false, true);
130    }
131  }
132  MI->setDesc(TII->get(OpcodeForOffset));
133  MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
134}
135
136unsigned
137SystemZRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
138  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
139  return TFI->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D;
140}
141