SystemZRegisterInfo.td revision 05ce4898710e3dd2dcc5f44f4aec4693ec0a42a6
1//===- SystemZRegisterInfo.td - The PowerPC Register File ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// 11//===----------------------------------------------------------------------===// 12 13class SystemZReg<string n> : Register<n> { 14 let Namespace = "SystemZ"; 15} 16 17class SystemZRegWithSubregs<string n, list<Register> subregs> 18 : RegisterWithSubRegs<n, subregs> { 19 let Namespace = "SystemZ"; 20} 21 22// We identify all our registers with a 4-bit ID, for consistency's sake. 23 24// GPR32 - Lower 32 bits of one of the 16 64-bit general-purpose registers 25class GPR32<bits<4> num, string n> : SystemZReg<n> { 26 field bits<4> Num = num; 27} 28 29// GPR64 - One of the 16 64-bit general-purpose registers 30class GPR64<bits<4> num, string n, list<Register> subregs, 31 list<Register> aliases = []> 32 : SystemZRegWithSubregs<n, subregs> { 33 field bits<4> Num = num; 34 let Aliases = aliases; 35} 36 37// GPR128 - 8 even-odd register pairs 38class GPR128<bits<4> num, string n, list<Register> subregs, 39 list<Register> aliases = []> 40 : SystemZRegWithSubregs<n, subregs> { 41 field bits<4> Num = num; 42 let Aliases = aliases; 43} 44 45// FPRS - Lower 32 bits of one of the 16 64-bit floating-point registers 46class FPRS<bits<4> num, string n> : SystemZReg<n> { 47 field bits<4> Num = num; 48} 49 50// FPRL - One of the 16 64-bit floating-point registers 51class FPRL<bits<4> num, string n, list<Register> subregs> 52 : SystemZRegWithSubregs<n, subregs> { 53 field bits<4> Num = num; 54} 55 56let Namespace = "SystemZ" in { 57def subreg_32bit : SubRegIndex; 58def subreg_odd32 : SubRegIndex; 59def subreg_even : SubRegIndex; 60def subreg_odd : SubRegIndex; 61} 62 63// General-purpose registers 64def R0W : GPR32< 0, "r0">, DwarfRegNum<[0]>; 65def R1W : GPR32< 1, "r1">, DwarfRegNum<[1]>; 66def R2W : GPR32< 2, "r2">, DwarfRegNum<[2]>; 67def R3W : GPR32< 3, "r3">, DwarfRegNum<[3]>; 68def R4W : GPR32< 4, "r4">, DwarfRegNum<[4]>; 69def R5W : GPR32< 5, "r5">, DwarfRegNum<[5]>; 70def R6W : GPR32< 6, "r6">, DwarfRegNum<[6]>; 71def R7W : GPR32< 7, "r7">, DwarfRegNum<[7]>; 72def R8W : GPR32< 8, "r8">, DwarfRegNum<[8]>; 73def R9W : GPR32< 9, "r9">, DwarfRegNum<[9]>; 74def R10W : GPR32<10, "r10">, DwarfRegNum<[10]>; 75def R11W : GPR32<11, "r11">, DwarfRegNum<[11]>; 76def R12W : GPR32<12, "r12">, DwarfRegNum<[12]>; 77def R13W : GPR32<13, "r13">, DwarfRegNum<[13]>; 78def R14W : GPR32<14, "r14">, DwarfRegNum<[14]>; 79def R15W : GPR32<15, "r15">, DwarfRegNum<[15]>; 80 81let SubRegIndices = [subreg_32bit] in { 82def R0D : GPR64< 0, "r0", [R0W]>, DwarfRegNum<[0]>; 83def R1D : GPR64< 1, "r1", [R1W]>, DwarfRegNum<[1]>; 84def R2D : GPR64< 2, "r2", [R2W]>, DwarfRegNum<[2]>; 85def R3D : GPR64< 3, "r3", [R3W]>, DwarfRegNum<[3]>; 86def R4D : GPR64< 4, "r4", [R4W]>, DwarfRegNum<[4]>; 87def R5D : GPR64< 5, "r5", [R5W]>, DwarfRegNum<[5]>; 88def R6D : GPR64< 6, "r6", [R6W]>, DwarfRegNum<[6]>; 89def R7D : GPR64< 7, "r7", [R7W]>, DwarfRegNum<[7]>; 90def R8D : GPR64< 8, "r8", [R8W]>, DwarfRegNum<[8]>; 91def R9D : GPR64< 9, "r9", [R9W]>, DwarfRegNum<[9]>; 92def R10D : GPR64<10, "r10", [R10W]>, DwarfRegNum<[10]>; 93def R11D : GPR64<11, "r11", [R11W]>, DwarfRegNum<[11]>; 94def R12D : GPR64<12, "r12", [R12W]>, DwarfRegNum<[12]>; 95def R13D : GPR64<13, "r13", [R13W]>, DwarfRegNum<[13]>; 96def R14D : GPR64<14, "r14", [R14W]>, DwarfRegNum<[14]>; 97def R15D : GPR64<15, "r15", [R15W]>, DwarfRegNum<[15]>; 98} 99 100// Register pairs 101let SubRegIndices = [subreg_32bit, subreg_odd32] in { 102def R0P : GPR64< 0, "r0", [R0W, R1W], [R0D, R1D]>, DwarfRegNum<[0]>; 103def R2P : GPR64< 2, "r2", [R2W, R3W], [R2D, R3D]>, DwarfRegNum<[2]>; 104def R4P : GPR64< 4, "r4", [R4W, R5W], [R4D, R5D]>, DwarfRegNum<[4]>; 105def R6P : GPR64< 6, "r6", [R6W, R7W], [R6D, R7D]>, DwarfRegNum<[6]>; 106def R8P : GPR64< 8, "r8", [R8W, R9W], [R8D, R9D]>, DwarfRegNum<[8]>; 107def R10P : GPR64<10, "r10", [R10W, R11W], [R10D, R11D]>, DwarfRegNum<[10]>; 108def R12P : GPR64<12, "r12", [R12W, R13W], [R12D, R13D]>, DwarfRegNum<[12]>; 109def R14P : GPR64<14, "r14", [R14W, R15W], [R14D, R15D]>, DwarfRegNum<[14]>; 110} 111 112let SubRegIndices = [subreg_even, subreg_odd], 113 CompositeIndices = [(subreg_odd32 subreg_odd, subreg_32bit)] in { 114def R0Q : GPR128< 0, "r0", [R0D, R1D], [R0P]>, DwarfRegNum<[0]>; 115def R2Q : GPR128< 2, "r2", [R2D, R3D], [R2P]>, DwarfRegNum<[2]>; 116def R4Q : GPR128< 4, "r4", [R4D, R5D], [R4P]>, DwarfRegNum<[4]>; 117def R6Q : GPR128< 6, "r6", [R6D, R7D], [R6P]>, DwarfRegNum<[6]>; 118def R8Q : GPR128< 8, "r8", [R8D, R9D], [R8P]>, DwarfRegNum<[8]>; 119def R10Q : GPR128<10, "r10", [R10D, R11D], [R10P]>, DwarfRegNum<[10]>; 120def R12Q : GPR128<12, "r12", [R12D, R13D], [R12P]>, DwarfRegNum<[12]>; 121def R14Q : GPR128<14, "r14", [R14D, R15D], [R14P]>, DwarfRegNum<[14]>; 122} 123 124// Floating-point registers 125def F0S : FPRS< 0, "f0">, DwarfRegNum<[16]>; 126def F1S : FPRS< 1, "f1">, DwarfRegNum<[17]>; 127def F2S : FPRS< 2, "f2">, DwarfRegNum<[18]>; 128def F3S : FPRS< 3, "f3">, DwarfRegNum<[19]>; 129def F4S : FPRS< 4, "f4">, DwarfRegNum<[20]>; 130def F5S : FPRS< 5, "f5">, DwarfRegNum<[21]>; 131def F6S : FPRS< 6, "f6">, DwarfRegNum<[22]>; 132def F7S : FPRS< 7, "f7">, DwarfRegNum<[23]>; 133def F8S : FPRS< 8, "f8">, DwarfRegNum<[24]>; 134def F9S : FPRS< 9, "f9">, DwarfRegNum<[25]>; 135def F10S : FPRS<10, "f10">, DwarfRegNum<[26]>; 136def F11S : FPRS<11, "f11">, DwarfRegNum<[27]>; 137def F12S : FPRS<12, "f12">, DwarfRegNum<[28]>; 138def F13S : FPRS<13, "f13">, DwarfRegNum<[29]>; 139def F14S : FPRS<14, "f14">, DwarfRegNum<[30]>; 140def F15S : FPRS<15, "f15">, DwarfRegNum<[31]>; 141 142let SubRegIndices = [subreg_32bit] in { 143def F0L : FPRL< 0, "f0", [F0S]>, DwarfRegNum<[16]>; 144def F1L : FPRL< 1, "f1", [F1S]>, DwarfRegNum<[17]>; 145def F2L : FPRL< 2, "f2", [F2S]>, DwarfRegNum<[18]>; 146def F3L : FPRL< 3, "f3", [F3S]>, DwarfRegNum<[19]>; 147def F4L : FPRL< 4, "f4", [F4S]>, DwarfRegNum<[20]>; 148def F5L : FPRL< 5, "f5", [F5S]>, DwarfRegNum<[21]>; 149def F6L : FPRL< 6, "f6", [F6S]>, DwarfRegNum<[22]>; 150def F7L : FPRL< 7, "f7", [F7S]>, DwarfRegNum<[23]>; 151def F8L : FPRL< 8, "f8", [F8S]>, DwarfRegNum<[24]>; 152def F9L : FPRL< 9, "f9", [F9S]>, DwarfRegNum<[25]>; 153def F10L : FPRL<10, "f10", [F10S]>, DwarfRegNum<[26]>; 154def F11L : FPRL<11, "f11", [F11S]>, DwarfRegNum<[27]>; 155def F12L : FPRL<12, "f12", [F12S]>, DwarfRegNum<[28]>; 156def F13L : FPRL<13, "f13", [F13S]>, DwarfRegNum<[29]>; 157def F14L : FPRL<14, "f14", [F14S]>, DwarfRegNum<[30]>; 158def F15L : FPRL<15, "f15", [F15S]>, DwarfRegNum<[31]>; 159} 160 161// Status register 162def PSW : SystemZReg<"psw">; 163 164/// Register classes 165def GR32 : RegisterClass<"SystemZ", [i32], 32, 166 // Volatile registers 167 [R0W, R1W, R2W, R3W, R4W, R5W, R6W, R7W, R8W, R9W, R10W, R12W, R13W, 168 // Frame pointer, sometimes allocable 169 R11W, 170 // Volatile, but not allocable 171 R14W, R15W]> 172{ 173 let MethodProtos = [{ 174 iterator allocation_order_begin(const MachineFunction &MF) const; 175 iterator allocation_order_end(const MachineFunction &MF) const; 176 }]; 177 let MethodBodies = [{ 178 static const unsigned SystemZ_REG32[] = { 179 SystemZ::R1W, SystemZ::R2W, SystemZ::R3W, SystemZ::R4W, 180 SystemZ::R5W, SystemZ::R0W, SystemZ::R12W, SystemZ::R11W, 181 SystemZ::R10W, SystemZ::R9W, SystemZ::R8W, SystemZ::R7W, 182 SystemZ::R6W, SystemZ::R14W, SystemZ::R13W 183 }; 184 static const unsigned SystemZ_REG32_nofp[] = { 185 SystemZ::R1W, SystemZ::R2W, SystemZ::R3W, SystemZ::R4W, 186 SystemZ::R5W, SystemZ::R0W, SystemZ::R12W, /* No R11W */ 187 SystemZ::R10W, SystemZ::R9W, SystemZ::R8W, SystemZ::R7W, 188 SystemZ::R6W, SystemZ::R14W, SystemZ::R13W 189 }; 190 GR32Class::iterator 191 GR32Class::allocation_order_begin(const MachineFunction &MF) const { 192 const TargetMachine &TM = MF.getTarget(); 193 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 194 if (RI->hasFP(MF)) 195 return SystemZ_REG32_nofp; 196 else 197 return SystemZ_REG32; 198 } 199 GR32Class::iterator 200 GR32Class::allocation_order_end(const MachineFunction &MF) const { 201 const TargetMachine &TM = MF.getTarget(); 202 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 203 if (RI->hasFP(MF)) 204 return SystemZ_REG32_nofp + (sizeof(SystemZ_REG32_nofp) / sizeof(unsigned)); 205 else 206 return SystemZ_REG32 + (sizeof(SystemZ_REG32) / sizeof(unsigned)); 207 } 208 }]; 209} 210 211/// Registers used to generate address. Everything except R0. 212def ADDR32 : RegisterClass<"SystemZ", [i32], 32, 213 // Volatile registers 214 [R1W, R2W, R3W, R4W, R5W, R6W, R7W, R8W, R9W, R10W, R12W, R13W, 215 // Frame pointer, sometimes allocable 216 R11W, 217 // Volatile, but not allocable 218 R14W, R15W]> 219{ 220 let MethodProtos = [{ 221 iterator allocation_order_begin(const MachineFunction &MF) const; 222 iterator allocation_order_end(const MachineFunction &MF) const; 223 }]; 224 let MethodBodies = [{ 225 static const unsigned SystemZ_ADDR32[] = { 226 SystemZ::R1W, SystemZ::R2W, SystemZ::R3W, SystemZ::R4W, 227 SystemZ::R5W, /* No R0W */ SystemZ::R12W, SystemZ::R11W, 228 SystemZ::R10W, SystemZ::R9W, SystemZ::R8W, SystemZ::R7W, 229 SystemZ::R6W, SystemZ::R14W, SystemZ::R13W 230 }; 231 static const unsigned SystemZ_ADDR32_nofp[] = { 232 SystemZ::R1W, SystemZ::R2W, SystemZ::R3W, SystemZ::R4W, 233 SystemZ::R5W, /* No R0W */ SystemZ::R12W, /* No R11W */ 234 SystemZ::R10W, SystemZ::R9W, SystemZ::R8W, SystemZ::R7W, 235 SystemZ::R6W, SystemZ::R14W, SystemZ::R13W 236 }; 237 ADDR32Class::iterator 238 ADDR32Class::allocation_order_begin(const MachineFunction &MF) const { 239 const TargetMachine &TM = MF.getTarget(); 240 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 241 if (RI->hasFP(MF)) 242 return SystemZ_ADDR32_nofp; 243 else 244 return SystemZ_ADDR32; 245 } 246 ADDR32Class::iterator 247 ADDR32Class::allocation_order_end(const MachineFunction &MF) const { 248 const TargetMachine &TM = MF.getTarget(); 249 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 250 if (RI->hasFP(MF)) 251 return SystemZ_ADDR32_nofp + (sizeof(SystemZ_ADDR32_nofp) / sizeof(unsigned)); 252 else 253 return SystemZ_ADDR32 + (sizeof(SystemZ_ADDR32) / sizeof(unsigned)); 254 } 255 }]; 256} 257 258def GR64 : RegisterClass<"SystemZ", [i64], 64, 259 // Volatile registers 260 [R0D, R1D, R2D, R3D, R4D, R5D, R6D, R7D, R8D, R9D, R10D, R12D, R13D, 261 // Frame pointer, sometimes allocable 262 R11D, 263 // Volatile, but not allocable 264 R14D, R15D]> 265{ 266 let SubRegClasses = [(GR32 subreg_32bit)]; 267 let MethodProtos = [{ 268 iterator allocation_order_begin(const MachineFunction &MF) const; 269 iterator allocation_order_end(const MachineFunction &MF) const; 270 }]; 271 let MethodBodies = [{ 272 static const unsigned SystemZ_REG64[] = { 273 SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, 274 SystemZ::R5D, SystemZ::R0D, SystemZ::R12D, SystemZ::R11D, 275 SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D, 276 SystemZ::R6D, SystemZ::R14D, SystemZ::R13D 277 }; 278 static const unsigned SystemZ_REG64_nofp[] = { 279 SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, 280 SystemZ::R5D, SystemZ::R0D, SystemZ::R12D, /* No R11D */ 281 SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D, 282 SystemZ::R6D, SystemZ::R14D, SystemZ::R13D 283 }; 284 GR64Class::iterator 285 GR64Class::allocation_order_begin(const MachineFunction &MF) const { 286 const TargetMachine &TM = MF.getTarget(); 287 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 288 if (RI->hasFP(MF)) 289 return SystemZ_REG64_nofp; 290 else 291 return SystemZ_REG64; 292 } 293 GR64Class::iterator 294 GR64Class::allocation_order_end(const MachineFunction &MF) const { 295 const TargetMachine &TM = MF.getTarget(); 296 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 297 if (RI->hasFP(MF)) 298 return SystemZ_REG64_nofp + (sizeof(SystemZ_REG64_nofp) / sizeof(unsigned)); 299 else 300 return SystemZ_REG64 + (sizeof(SystemZ_REG64) / sizeof(unsigned)); 301 } 302 }]; 303} 304 305def ADDR64 : RegisterClass<"SystemZ", [i64], 64, 306 // Volatile registers 307 [R1D, R2D, R3D, R4D, R5D, R6D, R7D, R8D, R9D, R10D, R12D, R13D, 308 // Frame pointer, sometimes allocable 309 R11D, 310 // Volatile, but not allocable 311 R14D, R15D]> 312{ 313 let SubRegClasses = [(ADDR32 subreg_32bit)]; 314 let MethodProtos = [{ 315 iterator allocation_order_begin(const MachineFunction &MF) const; 316 iterator allocation_order_end(const MachineFunction &MF) const; 317 }]; 318 let MethodBodies = [{ 319 static const unsigned SystemZ_ADDR64[] = { 320 SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, 321 SystemZ::R5D, /* No R0D */ SystemZ::R12D, SystemZ::R11D, 322 SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D, 323 SystemZ::R6D, SystemZ::R14D, SystemZ::R13D 324 }; 325 static const unsigned SystemZ_ADDR64_nofp[] = { 326 SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, 327 SystemZ::R5D, /* No R0D */ SystemZ::R12D, /* No R11D */ 328 SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D, 329 SystemZ::R6D, SystemZ::R14D, SystemZ::R13D 330 }; 331 ADDR64Class::iterator 332 ADDR64Class::allocation_order_begin(const MachineFunction &MF) const { 333 const TargetMachine &TM = MF.getTarget(); 334 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 335 if (RI->hasFP(MF)) 336 return SystemZ_ADDR64_nofp; 337 else 338 return SystemZ_ADDR64; 339 } 340 ADDR64Class::iterator 341 ADDR64Class::allocation_order_end(const MachineFunction &MF) const { 342 const TargetMachine &TM = MF.getTarget(); 343 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 344 if (RI->hasFP(MF)) 345 return SystemZ_ADDR64_nofp + (sizeof(SystemZ_ADDR64_nofp) / sizeof(unsigned)); 346 else 347 return SystemZ_ADDR64 + (sizeof(SystemZ_ADDR64) / sizeof(unsigned)); 348 } 349 }]; 350} 351 352// Even-odd register pairs 353def GR64P : RegisterClass<"SystemZ", [v2i32], 64, 354 [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P]> 355{ 356 let SubRegClasses = [(GR32 subreg_32bit, subreg_odd32)]; 357 let MethodProtos = [{ 358 iterator allocation_order_begin(const MachineFunction &MF) const; 359 iterator allocation_order_end(const MachineFunction &MF) const; 360 }]; 361 let MethodBodies = [{ 362 static const unsigned SystemZ_REG64P[] = { 363 SystemZ::R0P, SystemZ::R2P, SystemZ::R4P, SystemZ::R10P, 364 SystemZ::R8P, SystemZ::R6P }; 365 static const unsigned SystemZ_REG64P_nofp[] = { 366 SystemZ::R0P, SystemZ::R2P, SystemZ::R4P, /* NO R10P */ 367 SystemZ::R8P, SystemZ::R6P }; 368 GR64PClass::iterator 369 GR64PClass::allocation_order_begin(const MachineFunction &MF) const { 370 const TargetMachine &TM = MF.getTarget(); 371 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 372 if (RI->hasFP(MF)) 373 return SystemZ_REG64P_nofp; 374 else 375 return SystemZ_REG64P; 376 } 377 GR64PClass::iterator 378 GR64PClass::allocation_order_end(const MachineFunction &MF) const { 379 const TargetMachine &TM = MF.getTarget(); 380 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 381 if (RI->hasFP(MF)) 382 return SystemZ_REG64P_nofp + (sizeof(SystemZ_REG64P_nofp) / sizeof(unsigned)); 383 else 384 return SystemZ_REG64P + (sizeof(SystemZ_REG64P) / sizeof(unsigned)); 385 } 386 }]; 387} 388 389def GR128 : RegisterClass<"SystemZ", [v2i64], 128, 390 [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q]> 391{ 392 let SubRegClasses = [(GR32 subreg_32bit, subreg_odd32), 393 (GR64 subreg_even, subreg_odd)]; 394 let MethodProtos = [{ 395 iterator allocation_order_begin(const MachineFunction &MF) const; 396 iterator allocation_order_end(const MachineFunction &MF) const; 397 }]; 398 let MethodBodies = [{ 399 static const unsigned SystemZ_REG128[] = { 400 SystemZ::R0Q, SystemZ::R2Q, SystemZ::R4Q, SystemZ::R10Q, 401 SystemZ::R8Q, SystemZ::R6Q }; 402 static const unsigned SystemZ_REG128_nofp[] = { 403 SystemZ::R0Q, SystemZ::R2Q, SystemZ::R4Q, /* NO R10Q */ 404 SystemZ::R8Q, SystemZ::R6Q }; 405 GR128Class::iterator 406 GR128Class::allocation_order_begin(const MachineFunction &MF) const { 407 const TargetMachine &TM = MF.getTarget(); 408 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 409 if (RI->hasFP(MF)) 410 return SystemZ_REG128_nofp; 411 else 412 return SystemZ_REG128; 413 } 414 GR128Class::iterator 415 GR128Class::allocation_order_end(const MachineFunction &MF) const { 416 const TargetMachine &TM = MF.getTarget(); 417 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 418 if (RI->hasFP(MF)) 419 return SystemZ_REG128_nofp + (sizeof(SystemZ_REG128_nofp) / sizeof(unsigned)); 420 else 421 return SystemZ_REG128 + (sizeof(SystemZ_REG128) / sizeof(unsigned)); 422 } 423 }]; 424} 425 426def FP32 : RegisterClass<"SystemZ", [f32], 32, 427 [F0S, F1S, F2S, F3S, F4S, F5S, F6S, F7S, 428 F8S, F9S, F10S, F11S, F12S, F13S, F14S, F15S]> { 429 let MethodProtos = [{ 430 iterator allocation_order_begin(const MachineFunction &MF) const; 431 iterator allocation_order_end(const MachineFunction &MF) const; 432 }]; 433 let MethodBodies = [{ 434 static const unsigned SystemZ_REGFP32[] = { 435 SystemZ::F0S, SystemZ::F2S, SystemZ::F4S, SystemZ::F6S, 436 SystemZ::F1S, SystemZ::F3S, SystemZ::F5S, SystemZ::F7S, 437 SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, 438 SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S }; 439 FP32Class::iterator 440 FP32Class::allocation_order_begin(const MachineFunction &MF) const { 441 return SystemZ_REGFP32; 442 } 443 FP32Class::iterator 444 FP32Class::allocation_order_end(const MachineFunction &MF) const { 445 return SystemZ_REGFP32 + (sizeof(SystemZ_REGFP32) / sizeof(unsigned)); 446 } 447 }]; 448} 449 450def FP64 : RegisterClass<"SystemZ", [f64], 64, 451 [F0L, F1L, F2L, F3L, F4L, F5L, F6L, F7L, 452 F8L, F9L, F10L, F11L, F12L, F13L, F14L, F15L]> { 453 let SubRegClasses = [(FP32 subreg_32bit)]; 454 let MethodProtos = [{ 455 iterator allocation_order_begin(const MachineFunction &MF) const; 456 iterator allocation_order_end(const MachineFunction &MF) const; 457 }]; 458 let MethodBodies = [{ 459 static const unsigned SystemZ_REGFP64[] = { 460 SystemZ::F0L, SystemZ::F2L, SystemZ::F4L, SystemZ::F6L, 461 SystemZ::F1L, SystemZ::F3L, SystemZ::F5L, SystemZ::F7L, 462 SystemZ::F8L, SystemZ::F9L, SystemZ::F10L, SystemZ::F11L, 463 SystemZ::F12L, SystemZ::F13L, SystemZ::F14L, SystemZ::F15L }; 464 FP64Class::iterator 465 FP64Class::allocation_order_begin(const MachineFunction &MF) const { 466 return SystemZ_REGFP64; 467 } 468 FP64Class::iterator 469 FP64Class::allocation_order_end(const MachineFunction &MF) const { 470 return SystemZ_REGFP64 + (sizeof(SystemZ_REGFP64) / sizeof(unsigned)); 471 } 472 }]; 473} 474 475// Status flags registers. 476def CCR : RegisterClass<"SystemZ", [i64], 64, [PSW]> { 477 let CopyCost = -1; // Don't allow copying of status registers. 478} 479