SystemZRegisterInfo.td revision 361a78756b35c886aa3d01d3bd40c2adcf56cce2
1//===- SystemZRegisterInfo.td - The PowerPC Register File ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// 11//===----------------------------------------------------------------------===// 12 13class SystemZReg<string n> : Register<n> { 14 let Namespace = "SystemZ"; 15} 16 17class SystemZRegWithSubregs<string n, list<Register> subregs> 18 : RegisterWithSubRegs<n, subregs> { 19 let Namespace = "SystemZ"; 20} 21 22// We identify all our registers with a 4-bit ID, for consistency's sake. 23 24// GPR32 - Lower 32 bits of one of the 16 64-bit general-purpose registers 25class GPR32<bits<4> num, string n> : SystemZReg<n> { 26 field bits<4> Num = num; 27} 28 29// GPR64 - One of the 16 64-bit general-purpose registers 30class GPR64<bits<4> num, string n, list<Register> subregs, 31 list<Register> aliases = []> 32 : SystemZRegWithSubregs<n, subregs> { 33 field bits<4> Num = num; 34 let Aliases = aliases; 35} 36 37// GPR128 - 8 even-odd register pairs 38class GPR128<bits<4> num, string n, list<Register> subregs, 39 list<Register> aliases = []> 40 : SystemZRegWithSubregs<n, subregs> { 41 field bits<4> Num = num; 42 let Aliases = aliases; 43} 44 45// FPRS - Lower 32 bits of one of the 16 64-bit floating-point registers 46class FPRS<bits<4> num, string n> : SystemZReg<n> { 47 field bits<4> Num = num; 48} 49 50// FPRL - One of the 16 64-bit floating-point registers 51class FPRL<bits<4> num, string n, list<Register> subregs> 52 : SystemZRegWithSubregs<n, subregs> { 53 field bits<4> Num = num; 54} 55 56// General-purpose registers 57def R0W : GPR32< 0, "r0">, DwarfRegNum<[0]>; 58def R1W : GPR32< 1, "r1">, DwarfRegNum<[1]>; 59def R2W : GPR32< 2, "r2">, DwarfRegNum<[2]>; 60def R3W : GPR32< 3, "r3">, DwarfRegNum<[3]>; 61def R4W : GPR32< 4, "r4">, DwarfRegNum<[4]>; 62def R5W : GPR32< 5, "r5">, DwarfRegNum<[5]>; 63def R6W : GPR32< 6, "r6">, DwarfRegNum<[6]>; 64def R7W : GPR32< 7, "r7">, DwarfRegNum<[7]>; 65def R8W : GPR32< 8, "r8">, DwarfRegNum<[8]>; 66def R9W : GPR32< 9, "r9">, DwarfRegNum<[9]>; 67def R10W : GPR32<10, "r10">, DwarfRegNum<[10]>; 68def R11W : GPR32<11, "r11">, DwarfRegNum<[11]>; 69def R12W : GPR32<12, "r12">, DwarfRegNum<[12]>; 70def R13W : GPR32<13, "r13">, DwarfRegNum<[13]>; 71def R14W : GPR32<14, "r14">, DwarfRegNum<[14]>; 72def R15W : GPR32<15, "r15">, DwarfRegNum<[15]>; 73 74def R0D : GPR64< 0, "r0", [R0W]>, DwarfRegNum<[0]>; 75def R1D : GPR64< 1, "r1", [R1W]>, DwarfRegNum<[1]>; 76def R2D : GPR64< 2, "r2", [R2W]>, DwarfRegNum<[2]>; 77def R3D : GPR64< 3, "r3", [R3W]>, DwarfRegNum<[3]>; 78def R4D : GPR64< 4, "r4", [R4W]>, DwarfRegNum<[4]>; 79def R5D : GPR64< 5, "r5", [R5W]>, DwarfRegNum<[5]>; 80def R6D : GPR64< 6, "r6", [R6W]>, DwarfRegNum<[6]>; 81def R7D : GPR64< 7, "r7", [R7W]>, DwarfRegNum<[7]>; 82def R8D : GPR64< 8, "r8", [R8W]>, DwarfRegNum<[8]>; 83def R9D : GPR64< 9, "r9", [R9W]>, DwarfRegNum<[9]>; 84def R10D : GPR64<10, "r10", [R10W]>, DwarfRegNum<[10]>; 85def R11D : GPR64<11, "r11", [R11W]>, DwarfRegNum<[11]>; 86def R12D : GPR64<12, "r12", [R12W]>, DwarfRegNum<[12]>; 87def R13D : GPR64<13, "r13", [R13W]>, DwarfRegNum<[13]>; 88def R14D : GPR64<14, "r14", [R14W]>, DwarfRegNum<[14]>; 89def R15D : GPR64<15, "r15", [R15W]>, DwarfRegNum<[15]>; 90 91// Register pairs 92def R0P : GPR64< 0, "r0", [R0W, R1W], [R0D, R1D]>, DwarfRegNum<[0]>; 93def R2P : GPR64< 2, "r2", [R2W, R3W], [R2D, R3D]>, DwarfRegNum<[2]>; 94def R4P : GPR64< 4, "r4", [R4W, R5W], [R4D, R5D]>, DwarfRegNum<[4]>; 95def R6P : GPR64< 6, "r6", [R6W, R7W], [R6D, R7D]>, DwarfRegNum<[6]>; 96def R8P : GPR64< 8, "r8", [R8W, R9W], [R8D, R9D]>, DwarfRegNum<[8]>; 97def R10P : GPR64<10, "r10", [R10W, R11W], [R10D, R11D]>, DwarfRegNum<[10]>; 98def R12P : GPR64<12, "r12", [R12W, R13W], [R12D, R13D]>, DwarfRegNum<[12]>; 99def R14P : GPR64<14, "r14", [R14W, R15W], [R14D, R15D]>, DwarfRegNum<[14]>; 100 101def R0Q : GPR128< 0, "r0", [R0D, R1D], [R0P]>, DwarfRegNum<[0]>; 102def R2Q : GPR128< 2, "r2", [R2D, R3D], [R2P]>, DwarfRegNum<[2]>; 103def R4Q : GPR128< 4, "r4", [R4D, R5D], [R4P]>, DwarfRegNum<[4]>; 104def R6Q : GPR128< 6, "r6", [R6D, R7D], [R6P]>, DwarfRegNum<[6]>; 105def R8Q : GPR128< 8, "r8", [R8D, R9D], [R8P]>, DwarfRegNum<[8]>; 106def R10Q : GPR128<10, "r10", [R10D, R11D], [R10P]>, DwarfRegNum<[10]>; 107def R12Q : GPR128<12, "r12", [R12D, R13D], [R12P]>, DwarfRegNum<[12]>; 108def R14Q : GPR128<14, "r14", [R14D, R15D], [R14P]>, DwarfRegNum<[14]>; 109 110// Floating-point registers 111def F0S : FPRS< 0, "f0">, DwarfRegNum<[16]>; 112def F1S : FPRS< 1, "f1">, DwarfRegNum<[17]>; 113def F2S : FPRS< 2, "f2">, DwarfRegNum<[18]>; 114def F3S : FPRS< 3, "f3">, DwarfRegNum<[19]>; 115def F4S : FPRS< 4, "f4">, DwarfRegNum<[20]>; 116def F5S : FPRS< 5, "f5">, DwarfRegNum<[21]>; 117def F6S : FPRS< 6, "f6">, DwarfRegNum<[22]>; 118def F7S : FPRS< 7, "f7">, DwarfRegNum<[23]>; 119def F8S : FPRS< 8, "f8">, DwarfRegNum<[24]>; 120def F9S : FPRS< 9, "f9">, DwarfRegNum<[25]>; 121def F10S : FPRS<10, "f10">, DwarfRegNum<[26]>; 122def F11S : FPRS<11, "f11">, DwarfRegNum<[27]>; 123def F12S : FPRS<12, "f12">, DwarfRegNum<[28]>; 124def F13S : FPRS<13, "f13">, DwarfRegNum<[29]>; 125def F14S : FPRS<14, "f14">, DwarfRegNum<[30]>; 126def F15S : FPRS<15, "f15">, DwarfRegNum<[31]>; 127 128def F0L : FPRL< 0, "f0", [F0S]>, DwarfRegNum<[16]>; 129def F1L : FPRL< 1, "f1", [F1S]>, DwarfRegNum<[17]>; 130def F2L : FPRL< 2, "f2", [F2S]>, DwarfRegNum<[18]>; 131def F3L : FPRL< 3, "f3", [F3S]>, DwarfRegNum<[19]>; 132def F4L : FPRL< 4, "f4", [F4S]>, DwarfRegNum<[20]>; 133def F5L : FPRL< 5, "f5", [F5S]>, DwarfRegNum<[21]>; 134def F6L : FPRL< 6, "f6", [F6S]>, DwarfRegNum<[22]>; 135def F7L : FPRL< 7, "f7", [F7S]>, DwarfRegNum<[23]>; 136def F8L : FPRL< 8, "f8", [F8S]>, DwarfRegNum<[24]>; 137def F9L : FPRL< 9, "f9", [F9S]>, DwarfRegNum<[25]>; 138def F10L : FPRL<10, "f10", [F10S]>, DwarfRegNum<[26]>; 139def F11L : FPRL<11, "f11", [F11S]>, DwarfRegNum<[27]>; 140def F12L : FPRL<12, "f12", [F12S]>, DwarfRegNum<[28]>; 141def F13L : FPRL<13, "f13", [F13S]>, DwarfRegNum<[29]>; 142def F14L : FPRL<14, "f14", [F14S]>, DwarfRegNum<[30]>; 143def F15L : FPRL<15, "f15", [F15S]>, DwarfRegNum<[31]>; 144 145// Status register 146def PSW : SystemZReg<"psw">; 147 148def subreg_32bit : PatLeaf<(i32 1)>; 149def subreg_even32 : PatLeaf<(i32 1)>; 150def subreg_odd32 : PatLeaf<(i32 2)>; 151def subreg_even : PatLeaf<(i32 3)>; 152def subreg_odd : PatLeaf<(i32 4)>; 153 154def : SubRegSet<1, [R0D, R1D, R2D, R3D, R4D, R5D, R6D, R7D, 155 R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D], 156 [R0W, R1W, R2W, R3W, R4W, R5W, R6W, R7W, 157 R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>; 158 159def : SubRegSet<3, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q], 160 [R0D, R2D, R4D, R6D, R8D, R10D, R12D, R14D]>; 161 162def : SubRegSet<4, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q], 163 [R1D, R3D, R5D, R7D, R9D, R11D, R13D, R15D]>; 164 165def : SubRegSet<1, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P], 166 [R0W, R2W, R4W, R6W, R8W, R10W, R12W, R14W]>; 167 168def : SubRegSet<2, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P], 169 [R1W, R3W, R5W, R7W, R9W, R11W, R13W, R15W]>; 170 171def : SubRegSet<1, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q], 172 [R0W, R2W, R4W, R6W, R8W, R10W, R12W, R14W]>; 173 174def : SubRegSet<2, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q], 175 [R1W, R3W, R5W, R7W, R9W, R11W, R13W, R15W]>; 176 177/// Register classes 178def GR32 : RegisterClass<"SystemZ", [i32], 32, 179 // Volatile registers 180 [R0W, R1W, R2W, R3W, R4W, R5W, R6W, R7W, R8W, R9W, R10W, R12W, R13W, 181 // Frame pointer, sometimes allocable 182 R11W, 183 // Volatile, but not allocable 184 R14W, R15W]> 185{ 186 let MethodProtos = [{ 187 iterator allocation_order_begin(const MachineFunction &MF) const; 188 iterator allocation_order_end(const MachineFunction &MF) const; 189 }]; 190 let MethodBodies = [{ 191 static const unsigned SystemZ_REG32[] = { 192 SystemZ::R1W, SystemZ::R2W, SystemZ::R3W, SystemZ::R4W, 193 SystemZ::R5W, SystemZ::R0W, SystemZ::R12W, SystemZ::R11W, 194 SystemZ::R10W, SystemZ::R9W, SystemZ::R8W, SystemZ::R7W, 195 SystemZ::R6W, SystemZ::R14W, SystemZ::R13W 196 }; 197 static const unsigned SystemZ_REG32_nofp[] = { 198 SystemZ::R1W, SystemZ::R2W, SystemZ::R3W, SystemZ::R4W, 199 SystemZ::R5W, SystemZ::R0W, SystemZ::R12W, /* No R11W */ 200 SystemZ::R10W, SystemZ::R9W, SystemZ::R8W, SystemZ::R7W, 201 SystemZ::R6W, SystemZ::R14W, SystemZ::R13W 202 }; 203 GR32Class::iterator 204 GR32Class::allocation_order_begin(const MachineFunction &MF) const { 205 const TargetMachine &TM = MF.getTarget(); 206 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 207 if (RI->hasFP(MF)) 208 return SystemZ_REG32_nofp; 209 else 210 return SystemZ_REG32; 211 } 212 GR32Class::iterator 213 GR32Class::allocation_order_end(const MachineFunction &MF) const { 214 const TargetMachine &TM = MF.getTarget(); 215 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 216 if (RI->hasFP(MF)) 217 return SystemZ_REG32_nofp + (sizeof(SystemZ_REG32_nofp) / sizeof(unsigned)); 218 else 219 return SystemZ_REG32 + (sizeof(SystemZ_REG32) / sizeof(unsigned)); 220 } 221 }]; 222} 223 224/// Registers used to generate address. Everything except R0. 225def ADDR32 : RegisterClass<"SystemZ", [i32], 32, 226 // Volatile registers 227 [R1W, R2W, R3W, R4W, R5W, R6W, R7W, R8W, R9W, R10W, R12W, R13W, 228 // Frame pointer, sometimes allocable 229 R11W, 230 // Volatile, but not allocable 231 R14W, R15W]> 232{ 233 let MethodProtos = [{ 234 iterator allocation_order_begin(const MachineFunction &MF) const; 235 iterator allocation_order_end(const MachineFunction &MF) const; 236 }]; 237 let MethodBodies = [{ 238 static const unsigned SystemZ_ADDR32[] = { 239 SystemZ::R1W, SystemZ::R2W, SystemZ::R3W, SystemZ::R4W, 240 SystemZ::R5W, /* No R0W */ SystemZ::R12W, SystemZ::R11W, 241 SystemZ::R10W, SystemZ::R9W, SystemZ::R8W, SystemZ::R7W, 242 SystemZ::R6W, SystemZ::R14W, SystemZ::R13W 243 }; 244 static const unsigned SystemZ_ADDR32_nofp[] = { 245 SystemZ::R1W, SystemZ::R2W, SystemZ::R3W, SystemZ::R4W, 246 SystemZ::R5W, /* No R0W */ SystemZ::R12W, /* No R11W */ 247 SystemZ::R10W, SystemZ::R9W, SystemZ::R8W, SystemZ::R7W, 248 SystemZ::R6W, SystemZ::R14W, SystemZ::R13W 249 }; 250 ADDR32Class::iterator 251 ADDR32Class::allocation_order_begin(const MachineFunction &MF) const { 252 const TargetMachine &TM = MF.getTarget(); 253 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 254 if (RI->hasFP(MF)) 255 return SystemZ_ADDR32_nofp; 256 else 257 return SystemZ_ADDR32; 258 } 259 ADDR32Class::iterator 260 ADDR32Class::allocation_order_end(const MachineFunction &MF) const { 261 const TargetMachine &TM = MF.getTarget(); 262 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 263 if (RI->hasFP(MF)) 264 return SystemZ_ADDR32_nofp + (sizeof(SystemZ_ADDR32_nofp) / sizeof(unsigned)); 265 else 266 return SystemZ_ADDR32 + (sizeof(SystemZ_ADDR32) / sizeof(unsigned)); 267 } 268 }]; 269} 270 271def GR64 : RegisterClass<"SystemZ", [i64], 64, 272 // Volatile registers 273 [R0D, R1D, R2D, R3D, R4D, R5D, R6D, R7D, R8D, R9D, R10D, R12D, R13D, 274 // Frame pointer, sometimes allocable 275 R11D, 276 // Volatile, but not allocable 277 R14D, R15D]> 278{ 279 let SubRegClassList = [GR32]; 280 let MethodProtos = [{ 281 iterator allocation_order_begin(const MachineFunction &MF) const; 282 iterator allocation_order_end(const MachineFunction &MF) const; 283 }]; 284 let MethodBodies = [{ 285 static const unsigned SystemZ_REG64[] = { 286 SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, 287 SystemZ::R5D, SystemZ::R0D, SystemZ::R12D, SystemZ::R11D, 288 SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D, 289 SystemZ::R6D, SystemZ::R14D, SystemZ::R13D 290 }; 291 static const unsigned SystemZ_REG64_nofp[] = { 292 SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, 293 SystemZ::R5D, SystemZ::R0D, SystemZ::R12D, /* No R11D */ 294 SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D, 295 SystemZ::R6D, SystemZ::R14D, SystemZ::R13D 296 }; 297 GR64Class::iterator 298 GR64Class::allocation_order_begin(const MachineFunction &MF) const { 299 const TargetMachine &TM = MF.getTarget(); 300 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 301 if (RI->hasFP(MF)) 302 return SystemZ_REG64_nofp; 303 else 304 return SystemZ_REG64; 305 } 306 GR64Class::iterator 307 GR64Class::allocation_order_end(const MachineFunction &MF) const { 308 const TargetMachine &TM = MF.getTarget(); 309 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 310 if (RI->hasFP(MF)) 311 return SystemZ_REG64_nofp + (sizeof(SystemZ_REG64_nofp) / sizeof(unsigned)); 312 else 313 return SystemZ_REG64 + (sizeof(SystemZ_REG64) / sizeof(unsigned)); 314 } 315 }]; 316} 317 318def ADDR64 : RegisterClass<"SystemZ", [i64], 64, 319 // Volatile registers 320 [R1D, R2D, R3D, R4D, R5D, R6D, R7D, R8D, R9D, R10D, R12D, R13D, 321 // Frame pointer, sometimes allocable 322 R11D, 323 // Volatile, but not allocable 324 R14D, R15D]> 325{ 326 let SubRegClassList = [ADDR32]; 327 let MethodProtos = [{ 328 iterator allocation_order_begin(const MachineFunction &MF) const; 329 iterator allocation_order_end(const MachineFunction &MF) const; 330 }]; 331 let MethodBodies = [{ 332 static const unsigned SystemZ_ADDR64[] = { 333 SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, 334 SystemZ::R5D, /* No R0D */ SystemZ::R12D, SystemZ::R11D, 335 SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D, 336 SystemZ::R6D, SystemZ::R14D, SystemZ::R13D 337 }; 338 static const unsigned SystemZ_ADDR64_nofp[] = { 339 SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, 340 SystemZ::R5D, /* No R0D */ SystemZ::R12D, /* No R11D */ 341 SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D, 342 SystemZ::R6D, SystemZ::R14D, SystemZ::R13D 343 }; 344 ADDR64Class::iterator 345 ADDR64Class::allocation_order_begin(const MachineFunction &MF) const { 346 const TargetMachine &TM = MF.getTarget(); 347 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 348 if (RI->hasFP(MF)) 349 return SystemZ_ADDR64_nofp; 350 else 351 return SystemZ_ADDR64; 352 } 353 ADDR64Class::iterator 354 ADDR64Class::allocation_order_end(const MachineFunction &MF) const { 355 const TargetMachine &TM = MF.getTarget(); 356 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 357 if (RI->hasFP(MF)) 358 return SystemZ_ADDR64_nofp + (sizeof(SystemZ_ADDR64_nofp) / sizeof(unsigned)); 359 else 360 return SystemZ_ADDR64 + (sizeof(SystemZ_ADDR64) / sizeof(unsigned)); 361 } 362 }]; 363} 364 365// Even-odd register pairs 366def GR64P : RegisterClass<"SystemZ", [v2i32], 64, 367 [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P]> 368{ 369 let SubRegClassList = [GR32, GR32]; 370 let MethodProtos = [{ 371 iterator allocation_order_begin(const MachineFunction &MF) const; 372 iterator allocation_order_end(const MachineFunction &MF) const; 373 }]; 374 let MethodBodies = [{ 375 static const unsigned SystemZ_REG64P[] = { 376 SystemZ::R0P, SystemZ::R2P, SystemZ::R4P, SystemZ::R10P, 377 SystemZ::R8P, SystemZ::R6P }; 378 static const unsigned SystemZ_REG64P_nofp[] = { 379 SystemZ::R0P, SystemZ::R2P, SystemZ::R4P, /* NO R10P */ 380 SystemZ::R8P, SystemZ::R6P }; 381 GR64PClass::iterator 382 GR64PClass::allocation_order_begin(const MachineFunction &MF) const { 383 const TargetMachine &TM = MF.getTarget(); 384 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 385 if (RI->hasFP(MF)) 386 return SystemZ_REG64P_nofp; 387 else 388 return SystemZ_REG64P; 389 } 390 GR64PClass::iterator 391 GR64PClass::allocation_order_end(const MachineFunction &MF) const { 392 const TargetMachine &TM = MF.getTarget(); 393 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 394 if (RI->hasFP(MF)) 395 return SystemZ_REG64P_nofp + (sizeof(SystemZ_REG64P_nofp) / sizeof(unsigned)); 396 else 397 return SystemZ_REG64P + (sizeof(SystemZ_REG64P) / sizeof(unsigned)); 398 } 399 }]; 400} 401 402def GR128 : RegisterClass<"SystemZ", [v2i64], 128, 403 [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q]> 404{ 405 let SubRegClassList = [GR32, GR32, GR64, GR64]; 406 let MethodProtos = [{ 407 iterator allocation_order_begin(const MachineFunction &MF) const; 408 iterator allocation_order_end(const MachineFunction &MF) const; 409 }]; 410 let MethodBodies = [{ 411 static const unsigned SystemZ_REG128[] = { 412 SystemZ::R0Q, SystemZ::R2Q, SystemZ::R4Q, SystemZ::R10Q, 413 SystemZ::R8Q, SystemZ::R6Q }; 414 static const unsigned SystemZ_REG128_nofp[] = { 415 SystemZ::R0Q, SystemZ::R2Q, SystemZ::R4Q, /* NO R10Q */ 416 SystemZ::R8Q, SystemZ::R6Q }; 417 GR128Class::iterator 418 GR128Class::allocation_order_begin(const MachineFunction &MF) const { 419 const TargetMachine &TM = MF.getTarget(); 420 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 421 if (RI->hasFP(MF)) 422 return SystemZ_REG128_nofp; 423 else 424 return SystemZ_REG128; 425 } 426 GR128Class::iterator 427 GR128Class::allocation_order_end(const MachineFunction &MF) const { 428 const TargetMachine &TM = MF.getTarget(); 429 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 430 if (RI->hasFP(MF)) 431 return SystemZ_REG128_nofp + (sizeof(SystemZ_REG128_nofp) / sizeof(unsigned)); 432 else 433 return SystemZ_REG128 + (sizeof(SystemZ_REG128) / sizeof(unsigned)); 434 } 435 }]; 436} 437 438def FP32 : RegisterClass<"SystemZ", [f32], 32, 439 [F0S, F1S, F2S, F3S, F4S, F5S, F6S, F7S, 440 F8S, F9S, F10S, F11S, F12S, F13S, F14S, F15S]> { 441 let MethodProtos = [{ 442 iterator allocation_order_begin(const MachineFunction &MF) const; 443 iterator allocation_order_end(const MachineFunction &MF) const; 444 }]; 445 let MethodBodies = [{ 446 static const unsigned SystemZ_REGFP32[] = { 447 SystemZ::F0S, SystemZ::F2S, SystemZ::F4S, SystemZ::F6S, 448 SystemZ::F1S, SystemZ::F3S, SystemZ::F5S, SystemZ::F7S, 449 SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, 450 SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S }; 451 FP32Class::iterator 452 FP32Class::allocation_order_begin(const MachineFunction &MF) const { 453 return SystemZ_REGFP32; 454 } 455 FP32Class::iterator 456 FP32Class::allocation_order_end(const MachineFunction &MF) const { 457 return SystemZ_REGFP32 + (sizeof(SystemZ_REGFP32) / sizeof(unsigned)); 458 } 459 }]; 460} 461 462def FP64 : RegisterClass<"SystemZ", [f64], 64, 463 [F0L, F1L, F2L, F3L, F4L, F5L, F6L, F7L, 464 F8L, F9L, F10L, F11L, F12L, F13L, F14L, F15L]> { 465 let SubRegClassList = [FP32]; 466 let MethodProtos = [{ 467 iterator allocation_order_begin(const MachineFunction &MF) const; 468 iterator allocation_order_end(const MachineFunction &MF) const; 469 }]; 470 let MethodBodies = [{ 471 static const unsigned SystemZ_REGFP64[] = { 472 SystemZ::F0L, SystemZ::F2L, SystemZ::F4L, SystemZ::F6L, 473 SystemZ::F1L, SystemZ::F3L, SystemZ::F5L, SystemZ::F7L, 474 SystemZ::F8L, SystemZ::F9L, SystemZ::F10L, SystemZ::F11L, 475 SystemZ::F12L, SystemZ::F13L, SystemZ::F14L, SystemZ::F15L }; 476 FP64Class::iterator 477 FP64Class::allocation_order_begin(const MachineFunction &MF) const { 478 return SystemZ_REGFP64; 479 } 480 FP64Class::iterator 481 FP64Class::allocation_order_end(const MachineFunction &MF) const { 482 return SystemZ_REGFP64 + (sizeof(SystemZ_REGFP64) / sizeof(unsigned)); 483 } 484 }]; 485} 486 487// Status flags registers. 488def CCR : RegisterClass<"SystemZ", [i64], 64, [PSW]> { 489 let CopyCost = -1; // Don't allow copying of status registers. 490} 491