SystemZRegisterInfo.td revision 8bd0db7615269a909b8d588d7659de8277e785d1
1//===- SystemZRegisterInfo.td - The PowerPC Register File ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// 11//===----------------------------------------------------------------------===// 12 13class SystemZReg<string n> : Register<n> { 14 let Namespace = "SystemZ"; 15} 16 17class SystemZRegWithSubregs<string n, list<Register> subregs> 18 : RegisterWithSubRegs<n, subregs> { 19 let Namespace = "SystemZ"; 20} 21 22// We identify all our registers with a 4-bit ID, for consistency's sake. 23 24// GPR32 - Lower 32 bits of one of the 16 64-bit general-purpose registers 25class GPR32<bits<4> num, string n> : SystemZReg<n> { 26 field bits<4> Num = num; 27} 28 29// GPR64 - One of the 16 64-bit general-purpose registers 30class GPR64<bits<4> num, string n, list<Register> subregs, 31 list<Register> aliases = []> 32 : SystemZRegWithSubregs<n, subregs> { 33 field bits<4> Num = num; 34 let Aliases = aliases; 35} 36 37// GPR128 - 8 even-odd register pairs 38class GPR128<bits<4> num, string n, list<Register> subregs, 39 list<Register> aliases = []> 40 : SystemZRegWithSubregs<n, subregs> { 41 field bits<4> Num = num; 42 let Aliases = aliases; 43} 44 45// FPR - One of the 16 64-bit floating-point registers 46class FPR<bits<4> num, string n> : SystemZReg<n> { 47 field bits<4> Num = num; 48} 49 50// General-purpose registers 51def R0W : GPR32< 0, "r0">, DwarfRegNum<[0]>; 52def R1W : GPR32< 1, "r1">, DwarfRegNum<[1]>; 53def R2W : GPR32< 2, "r2">, DwarfRegNum<[2]>; 54def R3W : GPR32< 3, "r3">, DwarfRegNum<[3]>; 55def R4W : GPR32< 4, "r4">, DwarfRegNum<[4]>; 56def R5W : GPR32< 5, "r5">, DwarfRegNum<[5]>; 57def R6W : GPR32< 6, "r6">, DwarfRegNum<[6]>; 58def R7W : GPR32< 7, "r7">, DwarfRegNum<[7]>; 59def R8W : GPR32< 8, "r8">, DwarfRegNum<[8]>; 60def R9W : GPR32< 9, "r9">, DwarfRegNum<[9]>; 61def R10W : GPR32<10, "r10">, DwarfRegNum<[10]>; 62def R11W : GPR32<11, "r11">, DwarfRegNum<[11]>; 63def R12W : GPR32<12, "r12">, DwarfRegNum<[12]>; 64def R13W : GPR32<13, "r13">, DwarfRegNum<[13]>; 65def R14W : GPR32<14, "r14">, DwarfRegNum<[14]>; 66def R15W : GPR32<15, "r15">, DwarfRegNum<[15]>; 67 68def R0D : GPR64< 0, "r0", [R0W]>, DwarfRegNum<[0]>; 69def R1D : GPR64< 1, "r1", [R1W]>, DwarfRegNum<[1]>; 70def R2D : GPR64< 2, "r2", [R2W]>, DwarfRegNum<[2]>; 71def R3D : GPR64< 3, "r3", [R3W]>, DwarfRegNum<[3]>; 72def R4D : GPR64< 4, "r4", [R4W]>, DwarfRegNum<[4]>; 73def R5D : GPR64< 5, "r5", [R5W]>, DwarfRegNum<[5]>; 74def R6D : GPR64< 6, "r6", [R6W]>, DwarfRegNum<[6]>; 75def R7D : GPR64< 7, "r7", [R7W]>, DwarfRegNum<[7]>; 76def R8D : GPR64< 8, "r8", [R8W]>, DwarfRegNum<[8]>; 77def R9D : GPR64< 9, "r9", [R9W]>, DwarfRegNum<[9]>; 78def R10D : GPR64<10, "r10", [R10W]>, DwarfRegNum<[10]>; 79def R11D : GPR64<11, "r11", [R11W]>, DwarfRegNum<[11]>; 80def R12D : GPR64<12, "r12", [R12W]>, DwarfRegNum<[12]>; 81def R13D : GPR64<13, "r13", [R13W]>, DwarfRegNum<[13]>; 82def R14D : GPR64<14, "r14", [R14W]>, DwarfRegNum<[14]>; 83def R15D : GPR64<15, "r15", [R15W]>, DwarfRegNum<[15]>; 84 85// Register pairs 86def R0P : GPR64< 0, "r0", [R0W, R1W], [R0D, R1D]>, DwarfRegNum<[0]>; 87def R2P : GPR64< 2, "r2", [R2W, R3W], [R2D, R3D]>, DwarfRegNum<[2]>; 88def R4P : GPR64< 4, "r4", [R4W, R5W], [R4D, R5D]>, DwarfRegNum<[4]>; 89def R6P : GPR64< 6, "r6", [R6W, R7W], [R6D, R7D]>, DwarfRegNum<[6]>; 90def R8P : GPR64< 8, "r8", [R8W, R9W], [R8D, R9D]>, DwarfRegNum<[8]>; 91def R10P : GPR64<10, "r10", [R10W, R11W], [R10D, R11D]>, DwarfRegNum<[10]>; 92def R12P : GPR64<12, "r12", [R12W, R13W], [R12D, R13D]>, DwarfRegNum<[12]>; 93def R14P : GPR64<14, "r14", [R14W, R15W], [R14D, R15D]>, DwarfRegNum<[14]>; 94 95def R0Q : GPR128< 0, "r0", [R0D, R1D], [R0P]>, DwarfRegNum<[0]>; 96def R2Q : GPR128< 2, "r2", [R2D, R3D], [R2P]>, DwarfRegNum<[2]>; 97def R4Q : GPR128< 4, "r4", [R4D, R5D], [R4P]>, DwarfRegNum<[4]>; 98def R6Q : GPR128< 6, "r6", [R6D, R7D], [R6P]>, DwarfRegNum<[6]>; 99def R8Q : GPR128< 8, "r8", [R8D, R9D], [R8P]>, DwarfRegNum<[8]>; 100def R10Q : GPR128<10, "r10", [R10D, R11D], [R10P]>, DwarfRegNum<[10]>; 101def R12Q : GPR128<12, "r12", [R12D, R13D], [R12P]>, DwarfRegNum<[12]>; 102def R14Q : GPR128<14, "r14", [R14D, R15D], [R14P]>, DwarfRegNum<[14]>; 103 104// Floating-point registers 105def F0 : FPR< 0, "f0">, DwarfRegNum<[16]>; 106def F1 : FPR< 1, "f1">, DwarfRegNum<[17]>; 107def F2 : FPR< 2, "f2">, DwarfRegNum<[18]>; 108def F3 : FPR< 3, "f3">, DwarfRegNum<[19]>; 109def F4 : FPR< 4, "f4">, DwarfRegNum<[20]>; 110def F5 : FPR< 5, "f5">, DwarfRegNum<[21]>; 111def F6 : FPR< 6, "f6">, DwarfRegNum<[22]>; 112def F7 : FPR< 7, "f7">, DwarfRegNum<[23]>; 113def F8 : FPR< 8, "f8">, DwarfRegNum<[24]>; 114def F9 : FPR< 9, "f9">, DwarfRegNum<[25]>; 115def F10 : FPR<10, "f10">, DwarfRegNum<[26]>; 116def F11 : FPR<11, "f11">, DwarfRegNum<[27]>; 117def F12 : FPR<12, "f12">, DwarfRegNum<[28]>; 118def F13 : FPR<13, "f13">, DwarfRegNum<[29]>; 119def F14 : FPR<14, "f14">, DwarfRegNum<[30]>; 120def F15 : FPR<15, "f15">, DwarfRegNum<[31]>; 121 122// Status register 123def PSW : SystemZReg<"psw">; 124 125def subreg_32bit : PatLeaf<(i32 1)>; 126def subreg_even32 : PatLeaf<(i32 1)>; 127def subreg_odd32 : PatLeaf<(i32 2)>; 128def subreg_even : PatLeaf<(i32 3)>; 129def subreg_odd : PatLeaf<(i32 4)>; 130 131def : SubRegSet<1, [R0D, R1D, R2D, R3D, R4D, R5D, R6D, R7D, 132 R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D], 133 [R0W, R1W, R2W, R3W, R4W, R5W, R6W, R7W, 134 R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>; 135 136def : SubRegSet<3, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q], 137 [R0D, R2D, R4D, R6D, R8D, R10D, R12D, R14D]>; 138 139def : SubRegSet<4, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q], 140 [R1D, R3D, R5D, R7D, R9D, R11D, R13D, R15D]>; 141 142def : SubRegSet<1, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P], 143 [R0W, R2W, R4W, R6W, R8W, R10W, R12W, R14W]>; 144 145def : SubRegSet<2, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P], 146 [R1W, R3W, R5W, R7W, R9W, R11W, R13W, R15W]>; 147 148def : SubRegSet<1, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q], 149 [R0W, R2W, R4W, R6W, R8W, R10W, R12W, R14W]>; 150 151def : SubRegSet<2, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q], 152 [R1W, R3W, R5W, R7W, R9W, R11W, R13W, R15W]>; 153 154/// Register classes 155def GR32 : RegisterClass<"SystemZ", [i32], 32, 156 // Volatile registers 157 [R0W, R1W, R2W, R3W, R4W, R5W, R6W, R7W, R8W, R9W, R10W, R12W, R13W, 158 // Frame pointer, sometimes allocable 159 R11W, 160 // Volatile, but not allocable 161 R14W, R15W]> 162{ 163 let MethodProtos = [{ 164 iterator allocation_order_begin(const MachineFunction &MF) const; 165 iterator allocation_order_end(const MachineFunction &MF) const; 166 }]; 167 let MethodBodies = [{ 168 static const unsigned SystemZ_REG32[] = { 169 SystemZ::R1W, SystemZ::R2W, SystemZ::R3W, SystemZ::R4W, 170 SystemZ::R5W, SystemZ::R0W, SystemZ::R12W, SystemZ::R11W, 171 SystemZ::R10W, SystemZ::R9W, SystemZ::R8W, SystemZ::R7W, 172 SystemZ::R6W, SystemZ::R14W, SystemZ::R13W 173 }; 174 static const unsigned SystemZ_REG32_nofp[] = { 175 SystemZ::R1W, SystemZ::R2W, SystemZ::R3W, SystemZ::R4W, 176 SystemZ::R5W, SystemZ::R0W, SystemZ::R12W, /* No R11W */ 177 SystemZ::R10W, SystemZ::R9W, SystemZ::R8W, SystemZ::R7W, 178 SystemZ::R6W, SystemZ::R14W, SystemZ::R13W 179 }; 180 GR32Class::iterator 181 GR32Class::allocation_order_begin(const MachineFunction &MF) const { 182 const TargetMachine &TM = MF.getTarget(); 183 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 184 if (RI->hasFP(MF)) 185 return SystemZ_REG32_nofp; 186 else 187 return SystemZ_REG32; 188 } 189 GR32Class::iterator 190 GR32Class::allocation_order_end(const MachineFunction &MF) const { 191 const TargetMachine &TM = MF.getTarget(); 192 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 193 if (RI->hasFP(MF)) 194 return SystemZ_REG32_nofp + (sizeof(SystemZ_REG32_nofp) / sizeof(unsigned)); 195 else 196 return SystemZ_REG32 + (sizeof(SystemZ_REG32) / sizeof(unsigned)); 197 } 198 }]; 199} 200 201/// Registers used to generate address. Everything except R0. 202def ADDR32 : RegisterClass<"SystemZ", [i32], 32, 203 // Volatile registers 204 [R1W, R2W, R3W, R4W, R5W, R6W, R7W, R8W, R9W, R10W, R12W, R13W, 205 // Frame pointer, sometimes allocable 206 R11W, 207 // Volatile, but not allocable 208 R14W, R15W]> 209{ 210 let MethodProtos = [{ 211 iterator allocation_order_begin(const MachineFunction &MF) const; 212 iterator allocation_order_end(const MachineFunction &MF) const; 213 }]; 214 let MethodBodies = [{ 215 static const unsigned SystemZ_ADDR32[] = { 216 SystemZ::R1W, SystemZ::R2W, SystemZ::R3W, SystemZ::R4W, 217 SystemZ::R5W, /* No R0W */ SystemZ::R12W, SystemZ::R11W, 218 SystemZ::R10W, SystemZ::R9W, SystemZ::R8W, SystemZ::R7W, 219 SystemZ::R6W, SystemZ::R14W, SystemZ::R13W 220 }; 221 static const unsigned SystemZ_ADDR32_nofp[] = { 222 SystemZ::R1W, SystemZ::R2W, SystemZ::R3W, SystemZ::R4W, 223 SystemZ::R5W, /* No R0W */ SystemZ::R12W, /* No R11W */ 224 SystemZ::R10W, SystemZ::R9W, SystemZ::R8W, SystemZ::R7W, 225 SystemZ::R6W, SystemZ::R14W, SystemZ::R13W 226 }; 227 ADDR32Class::iterator 228 ADDR32Class::allocation_order_begin(const MachineFunction &MF) const { 229 const TargetMachine &TM = MF.getTarget(); 230 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 231 if (RI->hasFP(MF)) 232 return SystemZ_ADDR32_nofp; 233 else 234 return SystemZ_ADDR32; 235 } 236 ADDR32Class::iterator 237 ADDR32Class::allocation_order_end(const MachineFunction &MF) const { 238 const TargetMachine &TM = MF.getTarget(); 239 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 240 if (RI->hasFP(MF)) 241 return SystemZ_ADDR32_nofp + (sizeof(SystemZ_ADDR32_nofp) / sizeof(unsigned)); 242 else 243 return SystemZ_ADDR32 + (sizeof(SystemZ_ADDR32) / sizeof(unsigned)); 244 } 245 }]; 246} 247 248def GR64 : RegisterClass<"SystemZ", [i64], 64, 249 // Volatile registers 250 [R0D, R1D, R2D, R3D, R4D, R5D, R6D, R7D, R8D, R9D, R10D, R12D, R13D, 251 // Frame pointer, sometimes allocable 252 R11D, 253 // Volatile, but not allocable 254 R14D, R15D]> 255{ 256 let SubRegClassList = [GR32]; 257 let MethodProtos = [{ 258 iterator allocation_order_begin(const MachineFunction &MF) const; 259 iterator allocation_order_end(const MachineFunction &MF) const; 260 }]; 261 let MethodBodies = [{ 262 static const unsigned SystemZ_REG64[] = { 263 SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, 264 SystemZ::R5D, SystemZ::R0D, SystemZ::R12D, SystemZ::R11D, 265 SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D, 266 SystemZ::R6D, SystemZ::R14D, SystemZ::R13D 267 }; 268 static const unsigned SystemZ_REG64_nofp[] = { 269 SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, 270 SystemZ::R5D, SystemZ::R0D, SystemZ::R12D, /* No R11D */ 271 SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D, 272 SystemZ::R6D, SystemZ::R14D, SystemZ::R13D 273 }; 274 GR64Class::iterator 275 GR64Class::allocation_order_begin(const MachineFunction &MF) const { 276 const TargetMachine &TM = MF.getTarget(); 277 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 278 if (RI->hasFP(MF)) 279 return SystemZ_REG64_nofp; 280 else 281 return SystemZ_REG64; 282 } 283 GR64Class::iterator 284 GR64Class::allocation_order_end(const MachineFunction &MF) const { 285 const TargetMachine &TM = MF.getTarget(); 286 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 287 if (RI->hasFP(MF)) 288 return SystemZ_REG64_nofp + (sizeof(SystemZ_REG64_nofp) / sizeof(unsigned)); 289 else 290 return SystemZ_REG64 + (sizeof(SystemZ_REG64) / sizeof(unsigned)); 291 } 292 }]; 293} 294 295def ADDR64 : RegisterClass<"SystemZ", [i64], 64, 296 // Volatile registers 297 [R1D, R2D, R3D, R4D, R5D, R6D, R7D, R8D, R9D, R10D, R12D, R13D, 298 // Frame pointer, sometimes allocable 299 R11D, 300 // Volatile, but not allocable 301 R14D, R15D]> 302{ 303 let SubRegClassList = [ADDR32]; 304 let MethodProtos = [{ 305 iterator allocation_order_begin(const MachineFunction &MF) const; 306 iterator allocation_order_end(const MachineFunction &MF) const; 307 }]; 308 let MethodBodies = [{ 309 static const unsigned SystemZ_ADDR64[] = { 310 SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, 311 SystemZ::R5D, /* No R0D */ SystemZ::R12D, SystemZ::R11D, 312 SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D, 313 SystemZ::R6D, SystemZ::R14D, SystemZ::R13D 314 }; 315 static const unsigned SystemZ_ADDR64_nofp[] = { 316 SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, 317 SystemZ::R5D, /* No R0D */ SystemZ::R12D, /* No R11D */ 318 SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D, 319 SystemZ::R6D, SystemZ::R14D, SystemZ::R13D 320 }; 321 ADDR64Class::iterator 322 ADDR64Class::allocation_order_begin(const MachineFunction &MF) const { 323 const TargetMachine &TM = MF.getTarget(); 324 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 325 if (RI->hasFP(MF)) 326 return SystemZ_ADDR64_nofp; 327 else 328 return SystemZ_ADDR64; 329 } 330 ADDR64Class::iterator 331 ADDR64Class::allocation_order_end(const MachineFunction &MF) const { 332 const TargetMachine &TM = MF.getTarget(); 333 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 334 if (RI->hasFP(MF)) 335 return SystemZ_ADDR64_nofp + (sizeof(SystemZ_ADDR64_nofp) / sizeof(unsigned)); 336 else 337 return SystemZ_ADDR64 + (sizeof(SystemZ_ADDR64) / sizeof(unsigned)); 338 } 339 }]; 340} 341 342// Even-odd register pairs 343def GR64P : RegisterClass<"SystemZ", [v2i32], 64, 344 [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P]> 345{ 346 let SubRegClassList = [GR32, GR32]; 347 let MethodProtos = [{ 348 iterator allocation_order_begin(const MachineFunction &MF) const; 349 iterator allocation_order_end(const MachineFunction &MF) const; 350 }]; 351 let MethodBodies = [{ 352 static const unsigned SystemZ_REG64P[] = { 353 SystemZ::R0P, SystemZ::R2P, SystemZ::R4P, SystemZ::R10P, 354 SystemZ::R8P, SystemZ::R6P }; 355 static const unsigned SystemZ_REG64P_nofp[] = { 356 SystemZ::R0P, SystemZ::R2P, SystemZ::R4P, /* NO R10P */ 357 SystemZ::R8P, SystemZ::R6P }; 358 GR64PClass::iterator 359 GR64PClass::allocation_order_begin(const MachineFunction &MF) const { 360 const TargetMachine &TM = MF.getTarget(); 361 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 362 if (RI->hasFP(MF)) 363 return SystemZ_REG64P_nofp; 364 else 365 return SystemZ_REG64P; 366 } 367 GR64PClass::iterator 368 GR64PClass::allocation_order_end(const MachineFunction &MF) const { 369 const TargetMachine &TM = MF.getTarget(); 370 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 371 if (RI->hasFP(MF)) 372 return SystemZ_REG64P_nofp + (sizeof(SystemZ_REG64P_nofp) / sizeof(unsigned)); 373 else 374 return SystemZ_REG64P + (sizeof(SystemZ_REG64P) / sizeof(unsigned)); 375 } 376 }]; 377} 378 379def GR128 : RegisterClass<"SystemZ", [i128, v2i64], 128, 380 [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q]> 381{ 382 let SubRegClassList = [GR32, GR32, GR64, GR64]; 383 let MethodProtos = [{ 384 iterator allocation_order_begin(const MachineFunction &MF) const; 385 iterator allocation_order_end(const MachineFunction &MF) const; 386 }]; 387 let MethodBodies = [{ 388 static const unsigned SystemZ_REG128[] = { 389 SystemZ::R0Q, SystemZ::R2Q, SystemZ::R4Q, SystemZ::R10Q, 390 SystemZ::R8Q, SystemZ::R6Q }; 391 static const unsigned SystemZ_REG128_nofp[] = { 392 SystemZ::R0Q, SystemZ::R2Q, SystemZ::R4Q, /* NO R10Q */ 393 SystemZ::R8Q, SystemZ::R6Q }; 394 GR128Class::iterator 395 GR128Class::allocation_order_begin(const MachineFunction &MF) const { 396 const TargetMachine &TM = MF.getTarget(); 397 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 398 if (RI->hasFP(MF)) 399 return SystemZ_REG128_nofp; 400 else 401 return SystemZ_REG128; 402 } 403 GR128Class::iterator 404 GR128Class::allocation_order_end(const MachineFunction &MF) const { 405 const TargetMachine &TM = MF.getTarget(); 406 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 407 if (RI->hasFP(MF)) 408 return SystemZ_REG128_nofp + (sizeof(SystemZ_REG128_nofp) / sizeof(unsigned)); 409 else 410 return SystemZ_REG128 + (sizeof(SystemZ_REG128) / sizeof(unsigned)); 411 } 412 }]; 413} 414 415def FP64 : RegisterClass<"SystemZ", [f64], 64, 416 [F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15]>; 417 418// Status flags registers. 419def CCR : RegisterClass<"SystemZ", [i64], 64, [PSW]> { 420 let CopyCost = -1; // Don't allow copying of status registers. 421} 422