SystemZRegisterInfo.td revision a51752cbea5d57956f177470f463baeeee33f3d7
1//===- SystemZRegisterInfo.td - The PowerPC Register File ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// 11//===----------------------------------------------------------------------===// 12 13class SystemZReg<string n> : Register<n> { 14 let Namespace = "SystemZ"; 15} 16 17class SystemZRegWithSubregs<string n, list<Register> subregs> 18 : RegisterWithSubRegs<n, subregs> { 19 let Namespace = "SystemZ"; 20} 21 22// We identify all our registers with a 4-bit ID, for consistency's sake. 23 24// GPR32 - Lower 32 bits of one of the 16 64-bit general-purpose registers 25class GPR32<bits<4> num, string n> : SystemZReg<n> { 26 field bits<4> Num = num; 27} 28 29// GPR64 - One of the 16 64-bit general-purpose registers 30class GPR64<bits<4> num, string n, list<Register> subregs> 31 : SystemZRegWithSubregs<n, subregs> { 32 field bits<4> Num = num; 33} 34 35// FPR - One of the 16 64-bit floating-point registers 36class FPR<bits<4> num, string n> : SystemZReg<n> { 37 field bits<4> Num = num; 38} 39 40// General-purpose registers 41def R0W : GPR32< 0, "r0">, DwarfRegNum<[0]>; 42def R1W : GPR32< 1, "r1">, DwarfRegNum<[1]>; 43def R2W : GPR32< 2, "r2">, DwarfRegNum<[2]>; 44def R3W : GPR32< 3, "r3">, DwarfRegNum<[3]>; 45def R4W : GPR32< 4, "r4">, DwarfRegNum<[4]>; 46def R5W : GPR32< 5, "r5">, DwarfRegNum<[5]>; 47def R6W : GPR32< 6, "r6">, DwarfRegNum<[6]>; 48def R7W : GPR32< 7, "r7">, DwarfRegNum<[7]>; 49def R8W : GPR32< 8, "r8">, DwarfRegNum<[8]>; 50def R9W : GPR32< 9, "r9">, DwarfRegNum<[9]>; 51def R10W : GPR32<10, "r10">, DwarfRegNum<[10]>; 52def R11W : GPR32<11, "r11">, DwarfRegNum<[11]>; 53def R12W : GPR32<12, "r12">, DwarfRegNum<[12]>; 54def R13W : GPR32<13, "r13">, DwarfRegNum<[13]>; 55def R14W : GPR32<14, "r14">, DwarfRegNum<[14]>; 56def R15W : GPR32<15, "r15">, DwarfRegNum<[15]>; 57 58def R0D : GPR64< 0, "r0", [R0W]>, DwarfRegNum<[0]>; 59def R1D : GPR64< 1, "r1", [R1W]>, DwarfRegNum<[1]>; 60def R2D : GPR64< 2, "r2", [R2W]>, DwarfRegNum<[2]>; 61def R3D : GPR64< 3, "r3", [R3W]>, DwarfRegNum<[3]>; 62def R4D : GPR64< 4, "r4", [R4W]>, DwarfRegNum<[4]>; 63def R5D : GPR64< 5, "r5", [R5W]>, DwarfRegNum<[5]>; 64def R6D : GPR64< 6, "r6", [R6W]>, DwarfRegNum<[6]>; 65def R7D : GPR64< 7, "r7", [R7W]>, DwarfRegNum<[7]>; 66def R8D : GPR64< 8, "r8", [R8W]>, DwarfRegNum<[8]>; 67def R9D : GPR64< 9, "r9", [R9W]>, DwarfRegNum<[9]>; 68def R10D : GPR64<10, "r10", [R10W]>, DwarfRegNum<[10]>; 69def R11D : GPR64<11, "r11", [R11W]>, DwarfRegNum<[11]>; 70def R12D : GPR64<12, "r12", [R12W]>, DwarfRegNum<[12]>; 71def R13D : GPR64<13, "r13", [R13W]>, DwarfRegNum<[13]>; 72def R14D : GPR64<14, "r14", [R14W]>, DwarfRegNum<[14]>; 73def R15D : GPR64<15, "r15", [R15W]>, DwarfRegNum<[15]>; 74 75// Floating-point registers 76def F0 : FPR< 0, "f0">, DwarfRegNum<[16]>; 77def F1 : FPR< 1, "f1">, DwarfRegNum<[17]>; 78def F2 : FPR< 2, "f2">, DwarfRegNum<[18]>; 79def F3 : FPR< 3, "f3">, DwarfRegNum<[19]>; 80def F4 : FPR< 4, "f4">, DwarfRegNum<[20]>; 81def F5 : FPR< 5, "f5">, DwarfRegNum<[21]>; 82def F6 : FPR< 6, "f6">, DwarfRegNum<[22]>; 83def F7 : FPR< 7, "f7">, DwarfRegNum<[23]>; 84def F8 : FPR< 8, "f8">, DwarfRegNum<[24]>; 85def F9 : FPR< 9, "f9">, DwarfRegNum<[25]>; 86def F10 : FPR<10, "f10">, DwarfRegNum<[26]>; 87def F11 : FPR<11, "f11">, DwarfRegNum<[27]>; 88def F12 : FPR<12, "f12">, DwarfRegNum<[28]>; 89def F13 : FPR<13, "f13">, DwarfRegNum<[29]>; 90def F14 : FPR<14, "f14">, DwarfRegNum<[30]>; 91def F15 : FPR<15, "f15">, DwarfRegNum<[31]>; 92 93// Status register 94def PSW : SystemZReg<"psw">; 95 96def : SubRegSet<1, [R0D, R1D, R2D, R3D, R4D, R5D, R6D, R7D, 97 R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D], 98 [R0W, R1W, R2W, R3W, R4W, R5W, R6W, R7W, 99 R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>; 100 101def subreg_32bit : PatLeaf<(i32 1)>; 102 103/// Register classes 104def GR32 : RegisterClass<"SystemZ", [i32], 32, 105 // Volatile registers 106 [R0W, R1W, R2W, R3W, R4W, R5W, R6W, R7W, R8W, R9W, R10W, R12W, R13W, 107 // Frame pointer, sometimes allocable 108 R11W, 109 // Volatile, but not allocable 110 R14W, R15W]> 111{ 112 let MethodProtos = [{ 113 iterator allocation_order_end(const MachineFunction &MF) const; 114 }]; 115 let MethodBodies = [{ 116 GR32Class::iterator 117 GR32Class::allocation_order_end(const MachineFunction &MF) const { 118 const TargetMachine &TM = MF.getTarget(); 119 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 120 // Depending on whether the function uses frame pointer or not, last 2 or 3 121 // registers on the list above are reserved 122 if (RI->hasFP(MF)) 123 return end()-3; 124 else 125 return end()-2; 126 } 127 }]; 128} 129 130def GR64 : RegisterClass<"SystemZ", [i64], 64, 131 // Volatile registers 132 [R0D, R1D, R2D, R3D, R4D, R5D, R6D, R7D, R8D, R9D, R10D, R12D, R13D, 133 // Frame pointer, sometimes allocable 134 R11D, 135 // Volatile, but not allocable 136 R14D, R15D]> 137{ 138 let SubRegClassList = [GR32]; 139 let MethodProtos = [{ 140 iterator allocation_order_end(const MachineFunction &MF) const; 141 }]; 142 let MethodBodies = [{ 143 GR64Class::iterator 144 GR64Class::allocation_order_end(const MachineFunction &MF) const { 145 const TargetMachine &TM = MF.getTarget(); 146 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 147 // Depending on whether the function uses frame pointer or not, last 2 or 3 148 // registers on the list above are reserved 149 if (RI->hasFP(MF)) 150 return end()-3; 151 else 152 return end()-2; 153 } 154 }]; 155} 156 157def FP64 : RegisterClass<"SystemZ", [f64], 64, 158 [F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15]>; 159 160// Status flags registers. 161def CCR : RegisterClass<"SystemZ", [i64], 64, [PSW]> { 162 let CopyCost = -1; // Don't allow copying of status registers. 163} 164