SystemZRegisterInfo.td revision cd81d94322a39503e4a3e87b6ee03d4fcb3465fb
1//==- SystemZRegisterInfo.td - SystemZ register definitions -*- tablegen -*-==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Class definitions. 12//===----------------------------------------------------------------------===// 13 14class SystemZReg<string n> : Register<n> { 15 let Namespace = "SystemZ"; 16} 17 18class SystemZRegWithSubregs<string n, list<Register> subregs> 19 : RegisterWithSubRegs<n, subregs> { 20 let Namespace = "SystemZ"; 21} 22 23let Namespace = "SystemZ" in { 24def subreg_l32 : SubRegIndex<32, 0>; // Also acts as subreg_ll32. 25def subreg_h32 : SubRegIndex<32, 32>; // Also acts as subreg_lh32. 26def subreg_l64 : SubRegIndex<64, 0>; 27def subreg_h64 : SubRegIndex<64, 64>; 28def subreg_hh32 : ComposedSubRegIndex<subreg_h64, subreg_h32>; 29def subreg_hl32 : ComposedSubRegIndex<subreg_h64, subreg_l32>; 30} 31 32// Define a register class that contains values of type TYPE and an 33// associated operand called NAME. SIZE is the size and alignment 34// of the registers and REGLIST is the list of individual registers. 35multiclass SystemZRegClass<string name, ValueType type, int size, dag regList> { 36 def AsmOperand : AsmOperandClass { 37 let Name = name; 38 let ParserMethod = "parse"##name; 39 let RenderMethod = "addRegOperands"; 40 } 41 def Bit : RegisterClass<"SystemZ", [type], size, regList> { 42 let Size = size; 43 } 44 def "" : RegisterOperand<!cast<RegisterClass>(name##"Bit")> { 45 let ParserMatchClass = !cast<AsmOperandClass>(name##"AsmOperand"); 46 } 47} 48 49//===----------------------------------------------------------------------===// 50// General-purpose registers 51//===----------------------------------------------------------------------===// 52 53// Lower 32 bits of one of the 16 64-bit general-purpose registers 54class GPR32<bits<16> num, string n> : SystemZReg<n> { 55 let HWEncoding = num; 56} 57 58// One of the 16 64-bit general-purpose registers. 59class GPR64<bits<16> num, string n, GPR32 low, GPR32 high> 60 : SystemZRegWithSubregs<n, [low, high]> { 61 let HWEncoding = num; 62 let SubRegIndices = [subreg_l32, subreg_h32]; 63} 64 65// 8 even-odd pairs of GPR64s. 66class GPR128<bits<16> num, string n, GPR64 low, GPR64 high> 67 : SystemZRegWithSubregs<n, [low, high]> { 68 let HWEncoding = num; 69 let SubRegIndices = [subreg_l64, subreg_h64]; 70} 71 72// General-purpose registers 73foreach I = 0-15 in { 74 def R#I#L : GPR32<I, "r"#I>; 75 def R#I#H : GPR32<I, "r"#I>; 76 def R#I#D : GPR64<I, "r"#I, !cast<GPR32>("R"#I#"L"), !cast<GPR32>("R"#I#"H")>, 77 DwarfRegNum<[I]>; 78} 79 80foreach I = [0, 2, 4, 6, 8, 10, 12, 14] in { 81 def R#I#Q : GPR128<I, "r"#I, !cast<GPR64>("R"#!add(I, 1)#"D"), 82 !cast<GPR64>("R"#I#"D")>; 83} 84 85/// Allocate the callee-saved R6-R13 backwards. That way they can be saved 86/// together with R14 and R15 in one prolog instruction. 87defm GR32 : SystemZRegClass<"GR32", i32, 32, (add (sequence "R%uL", 0, 5), 88 (sequence "R%uL", 15, 6))>; 89defm GRH32 : SystemZRegClass<"GRH32", i32, 32, (add (sequence "R%uH", 0, 5), 90 (sequence "R%uH", 15, 6))>; 91defm GR64 : SystemZRegClass<"GR64", i64, 64, (add (sequence "R%uD", 0, 5), 92 (sequence "R%uD", 15, 6))>; 93 94// Combine the low and high GR32s into a single class. This can only be 95// used for virtual registers if the high-word facility is available. 96defm GRX32 : SystemZRegClass<"GRX32", i32, 32, 97 (add (sequence "R%uL", 0, 5), 98 (sequence "R%uH", 0, 5), 99 R15L, R15H, R14L, R14H, R13L, R13H, 100 R12L, R12H, R11L, R11H, R10L, R10H, 101 R9L, R9H, R8L, R8H, R7L, R7H, R6L, R6H)>; 102 103// The architecture doesn't really have any i128 support, so model the 104// register pairs as untyped instead. 105defm GR128 : SystemZRegClass<"GR128", untyped, 128, (add R0Q, R2Q, R4Q, 106 R12Q, R10Q, R8Q, R6Q, 107 R14Q)>; 108 109// Base and index registers. Everything except R0, which in an address 110// context evaluates as 0. 111defm ADDR32 : SystemZRegClass<"ADDR32", i32, 32, (sub GR32Bit, R0L)>; 112defm ADDR64 : SystemZRegClass<"ADDR64", i64, 64, (sub GR64Bit, R0D)>; 113 114// Not used directly, but needs to exist for ADDR32 and ADDR64 subregs 115// of a GR128. 116defm ADDR128 : SystemZRegClass<"ADDR128", untyped, 128, (sub GR128Bit, R0Q)>; 117 118//===----------------------------------------------------------------------===// 119// Floating-point registers 120//===----------------------------------------------------------------------===// 121 122// Maps FPR register numbers to their DWARF encoding. 123class DwarfMapping<int id> { int Id = id; } 124 125def F0Dwarf : DwarfMapping<16>; 126def F2Dwarf : DwarfMapping<17>; 127def F4Dwarf : DwarfMapping<18>; 128def F6Dwarf : DwarfMapping<19>; 129 130def F1Dwarf : DwarfMapping<20>; 131def F3Dwarf : DwarfMapping<21>; 132def F5Dwarf : DwarfMapping<22>; 133def F7Dwarf : DwarfMapping<23>; 134 135def F8Dwarf : DwarfMapping<24>; 136def F10Dwarf : DwarfMapping<25>; 137def F12Dwarf : DwarfMapping<26>; 138def F14Dwarf : DwarfMapping<27>; 139 140def F9Dwarf : DwarfMapping<28>; 141def F11Dwarf : DwarfMapping<29>; 142def F13Dwarf : DwarfMapping<30>; 143def F15Dwarf : DwarfMapping<31>; 144 145// Lower 32 bits of one of the 16 64-bit floating-point registers 146class FPR32<bits<16> num, string n> : SystemZReg<n> { 147 let HWEncoding = num; 148} 149 150// One of the 16 64-bit floating-point registers 151class FPR64<bits<16> num, string n, FPR32 low> 152 : SystemZRegWithSubregs<n, [low]> { 153 let HWEncoding = num; 154 let SubRegIndices = [subreg_h32]; 155} 156 157// 8 pairs of FPR64s, with a one-register gap inbetween. 158class FPR128<bits<16> num, string n, FPR64 low, FPR64 high> 159 : SystemZRegWithSubregs<n, [low, high]> { 160 let HWEncoding = num; 161 let SubRegIndices = [subreg_l64, subreg_h64]; 162} 163 164// Floating-point registers 165foreach I = 0-15 in { 166 def F#I#S : FPR32<I, "f"#I>; 167 def F#I#D : FPR64<I, "f"#I, !cast<FPR32>("F"#I#"S")>, 168 DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>; 169} 170 171foreach I = [0, 1, 4, 5, 8, 9, 12, 13] in { 172 def F#I#Q : FPR128<I, "f"#I, !cast<FPR64>("F"#!add(I, 2)#"D"), 173 !cast<FPR64>("F"#I#"D")>; 174} 175 176// There's no store-multiple instruction for FPRs, so we're not fussy 177// about the order in which call-saved registers are allocated. 178defm FP32 : SystemZRegClass<"FP32", f32, 32, (sequence "F%uS", 0, 15)>; 179defm FP64 : SystemZRegClass<"FP64", f64, 64, (sequence "F%uD", 0, 15)>; 180defm FP128 : SystemZRegClass<"FP128", f128, 128, (add F0Q, F1Q, F4Q, F5Q, 181 F8Q, F9Q, F12Q, F13Q)>; 182 183//===----------------------------------------------------------------------===// 184// Other registers 185//===----------------------------------------------------------------------===// 186 187// The 2-bit condition code field of the PSW. Every register named in an 188// inline asm needs a class associated with it. 189def CC : SystemZReg<"cc">; 190def CCRegs : RegisterClass<"SystemZ", [i32], 32, (add CC)>; 191