SystemZShortenInst.cpp revision c2b840cb7c58e59c68aaa589841c41fb272df66d 
1//===-- SystemZShortenInst.cpp - Instruction-shortening pass --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This pass tries to replace instructions with shorter forms.  For example,
11// IILF can be replaced with LLILL or LLILH if the constant fits and if the
12// other 32 bits of the GR64 destination are not live.
13//
14//===----------------------------------------------------------------------===//
15
16#define DEBUG_TYPE "systemz-shorten-inst"
17
18#include "SystemZTargetMachine.h"
19#include "llvm/CodeGen/MachineFunctionPass.h"
20
21using namespace llvm;
22
23namespace {
24  class SystemZShortenInst : public MachineFunctionPass {
25  public:
26    static char ID;
27    SystemZShortenInst(const SystemZTargetMachine &tm);
28
29    virtual const char *getPassName() const {
30      return "SystemZ Instruction Shortening";
31    }
32
33    bool processBlock(MachineBasicBlock *MBB);
34    bool runOnMachineFunction(MachineFunction &F);
35
36  private:
37    bool shortenIIF(MachineInstr &MI, unsigned *GPRMap, unsigned LiveOther,
38                    unsigned LLIxL, unsigned LLIxH);
39
40    const SystemZInstrInfo *TII;
41
42    // LowGPRs[I] has bit N set if LLVM register I includes the low
43    // word of GPR N.  HighGPRs is the same for the high word.
44    unsigned LowGPRs[SystemZ::NUM_TARGET_REGS];
45    unsigned HighGPRs[SystemZ::NUM_TARGET_REGS];
46  };
47
48  char SystemZShortenInst::ID = 0;
49} // end of anonymous namespace
50
51FunctionPass *llvm::createSystemZShortenInstPass(SystemZTargetMachine &TM) {
52  return new SystemZShortenInst(TM);
53}
54
55SystemZShortenInst::SystemZShortenInst(const SystemZTargetMachine &tm)
56  : MachineFunctionPass(ID), TII(0), LowGPRs(), HighGPRs() {
57  // Set up LowGPRs and HighGPRs.
58  for (unsigned I = 0; I < 16; ++I) {
59    LowGPRs[SystemZMC::GR32Regs[I]] |= 1 << I;
60    LowGPRs[SystemZMC::GR64Regs[I]] |= 1 << I;
61    HighGPRs[SystemZMC::GR64Regs[I]] |= 1 << I;
62    if (unsigned GR128 = SystemZMC::GR128Regs[I]) {
63      LowGPRs[GR128] |= 3 << I;
64      HighGPRs[GR128] |= 3 << I;
65    }
66  }
67}
68
69// MI loads one word of a GPR using an IIxF instruction and LLIxL and LLIxH
70// are the halfword immediate loads for the same word.  Try to use one of them
71// instead of IIxF.  If MI loads the high word, GPRMap[X] is the set of high
72// words referenced by LLVM register X while LiveOther is the mask of low
73// words that are currently live, and vice versa.
74bool SystemZShortenInst::shortenIIF(MachineInstr &MI, unsigned *GPRMap,
75                                    unsigned LiveOther, unsigned LLIxL,
76                                    unsigned LLIxH) {
77  unsigned Reg = MI.getOperand(0).getReg();
78  assert(Reg < SystemZ::NUM_TARGET_REGS && "Invalid register number");
79  unsigned GPRs = GPRMap[Reg];
80  assert(GPRs != 0 && "Register must be a GPR");
81  if (GPRs & LiveOther)
82    return false;
83
84  uint64_t Imm = MI.getOperand(1).getImm();
85  if (SystemZ::isImmLL(Imm)) {
86    MI.setDesc(TII->get(LLIxL));
87    MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
88    return true;
89  }
90  if (SystemZ::isImmLH(Imm)) {
91    MI.setDesc(TII->get(LLIxH));
92    MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
93    MI.getOperand(1).setImm(Imm >> 16);
94    return true;
95  }
96  return false;
97}
98
99// Process all instructions in MBB.  Return true if something changed.
100bool SystemZShortenInst::processBlock(MachineBasicBlock *MBB) {
101  bool Changed = false;
102
103  // Work out which words are live on exit from the block.
104  unsigned LiveLow = 0;
105  unsigned LiveHigh = 0;
106  for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
107         SE = MBB->succ_end(); SI != SE; ++SI) {
108    for (MachineBasicBlock::livein_iterator LI = (*SI)->livein_begin(),
109           LE = (*SI)->livein_end(); LI != LE; ++LI) {
110      unsigned Reg = *LI;
111      assert(Reg < SystemZ::NUM_TARGET_REGS && "Invalid register number");
112      LiveLow |= LowGPRs[Reg];
113      LiveHigh |= HighGPRs[Reg];
114    }
115  }
116
117  // Iterate backwards through the block looking for instructions to change.
118  for (MachineBasicBlock::reverse_iterator MBBI = MBB->rbegin(),
119         MBBE = MBB->rend(); MBBI != MBBE; ++MBBI) {
120    MachineInstr &MI = *MBBI;
121    unsigned Opcode = MI.getOpcode();
122    if (Opcode == SystemZ::IILF32)
123      Changed |= shortenIIF(MI, LowGPRs, LiveHigh, SystemZ::LLILL,
124                            SystemZ::LLILH);
125    unsigned UsedLow = 0;
126    unsigned UsedHigh = 0;
127    for (MachineInstr::mop_iterator MOI = MI.operands_begin(),
128           MOE = MI.operands_end(); MOI != MOE; ++MOI) {
129      MachineOperand &MO = *MOI;
130      if (MO.isReg()) {
131        if (unsigned Reg = MO.getReg()) {
132          assert(Reg < SystemZ::NUM_TARGET_REGS && "Invalid register number");
133          if (MO.isDef()) {
134            LiveLow &= ~LowGPRs[Reg];
135            LiveHigh &= ~HighGPRs[Reg];
136          } else if (!MO.isUndef()) {
137            UsedLow |= LowGPRs[Reg];
138            UsedHigh |= HighGPRs[Reg];
139          }
140        }
141      }
142    }
143    LiveLow |= UsedLow;
144    LiveHigh |= UsedHigh;
145  }
146
147  return Changed;
148}
149
150bool SystemZShortenInst::runOnMachineFunction(MachineFunction &F) {
151  TII = static_cast<const SystemZInstrInfo *>(F.getTarget().getInstrInfo());
152
153  bool Changed = false;
154  for (MachineFunction::iterator MFI = F.begin(), MFE = F.end();
155       MFI != MFE; ++MFI)
156    Changed |= processBlock(MFI);
157
158  return Changed;
159}
160