X86IntelInstPrinter.cpp revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338
1ed47a0409b187d5dcd2bddfd054326fc809d00aeChris Lattner//===-- X86IntelInstPrinter.cpp - Intel assembly instruction printing -----===// 2ed47a0409b187d5dcd2bddfd054326fc809d00aeChris Lattner// 3ed47a0409b187d5dcd2bddfd054326fc809d00aeChris Lattner// The LLVM Compiler Infrastructure 4ed47a0409b187d5dcd2bddfd054326fc809d00aeChris Lattner// 5ed47a0409b187d5dcd2bddfd054326fc809d00aeChris Lattner// This file is distributed under the University of Illinois Open Source 6ed47a0409b187d5dcd2bddfd054326fc809d00aeChris Lattner// License. See LICENSE.TXT for details. 7ed47a0409b187d5dcd2bddfd054326fc809d00aeChris Lattner// 8ed47a0409b187d5dcd2bddfd054326fc809d00aeChris Lattner//===----------------------------------------------------------------------===// 9ed47a0409b187d5dcd2bddfd054326fc809d00aeChris Lattner// 10ed47a0409b187d5dcd2bddfd054326fc809d00aeChris Lattner// This file includes code for rendering MCInst instances as Intel-style 11ed47a0409b187d5dcd2bddfd054326fc809d00aeChris Lattner// assembly. 12892e18239308f8a02a4c83758616be84a459c19dChris Lattner// 13892e18239308f8a02a4c83758616be84a459c19dChris Lattner//===----------------------------------------------------------------------===// 14ed47a0409b187d5dcd2bddfd054326fc809d00aeChris Lattner 15ed47a0409b187d5dcd2bddfd054326fc809d00aeChris Lattner#define DEBUG_TYPE "asm-printer" 16892e18239308f8a02a4c83758616be84a459c19dChris Lattner#include "X86IntelInstPrinter.h" 17892e18239308f8a02a4c83758616be84a459c19dChris Lattner#include "MCTargetDesc/X86BaseInfo.h" 18892e18239308f8a02a4c83758616be84a459c19dChris Lattner#include "MCTargetDesc/X86MCTargetDesc.h" 19892e18239308f8a02a4c83758616be84a459c19dChris Lattner#include "X86InstComments.h" 20ed47a0409b187d5dcd2bddfd054326fc809d00aeChris Lattner#include "llvm/MC/MCExpr.h" 21ed47a0409b187d5dcd2bddfd054326fc809d00aeChris Lattner#include "llvm/MC/MCInst.h" 22ed47a0409b187d5dcd2bddfd054326fc809d00aeChris Lattner#include "llvm/MC/MCInstrInfo.h" 23968ff1196768c0b6dbcc5508025a2923bfa73fabChris Lattner#include "llvm/Support/ErrorHandling.h" 24968ff1196768c0b6dbcc5508025a2923bfa73fabChris Lattner#include "llvm/Support/FormattedStream.h" 25968ff1196768c0b6dbcc5508025a2923bfa73fabChris Lattner#include <cctype> 26ed47a0409b187d5dcd2bddfd054326fc809d00aeChris Lattnerusing namespace llvm; 27ed47a0409b187d5dcd2bddfd054326fc809d00aeChris Lattner 28ed47a0409b187d5dcd2bddfd054326fc809d00aeChris Lattner#include "X86GenAsmWriter1.inc" 29ed47a0409b187d5dcd2bddfd054326fc809d00aeChris Lattner 30ed47a0409b187d5dcd2bddfd054326fc809d00aeChris Lattnervoid X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { 31892e18239308f8a02a4c83758616be84a459c19dChris Lattner OS << getRegisterName(RegNo); 32892e18239308f8a02a4c83758616be84a459c19dChris Lattner} 33892e18239308f8a02a4c83758616be84a459c19dChris Lattner 34a1c31b779cdde0090b8efcde87d7d0d898cabd38Chris Lattnervoid X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, 35a1c31b779cdde0090b8efcde87d7d0d898cabd38Chris Lattner StringRef Annot) { 36a1c31b779cdde0090b8efcde87d7d0d898cabd38Chris Lattner const MCInstrDesc &Desc = MII.get(MI->getOpcode()); 37a1c31b779cdde0090b8efcde87d7d0d898cabd38Chris Lattner uint64_t TSFlags = Desc.TSFlags; 38a1c31b779cdde0090b8efcde87d7d0d898cabd38Chris Lattner 39a1c31b779cdde0090b8efcde87d7d0d898cabd38Chris Lattner if (TSFlags & X86II::LOCK) 40892e18239308f8a02a4c83758616be84a459c19dChris Lattner OS << "\tlock\n"; 41892e18239308f8a02a4c83758616be84a459c19dChris Lattner 42892e18239308f8a02a4c83758616be84a459c19dChris Lattner printInstruction(MI, OS); 43892e18239308f8a02a4c83758616be84a459c19dChris Lattner 44892e18239308f8a02a4c83758616be84a459c19dChris Lattner // Next always print the annotation. 45892e18239308f8a02a4c83758616be84a459c19dChris Lattner printAnnotation(OS, Annot); 46892e18239308f8a02a4c83758616be84a459c19dChris Lattner 47892e18239308f8a02a4c83758616be84a459c19dChris Lattner // If verbose assembly is enabled, we can print some informative comments. 48892e18239308f8a02a4c83758616be84a459c19dChris Lattner if (CommentStream) 49892e18239308f8a02a4c83758616be84a459c19dChris Lattner EmitAnyX86InstComments(MI, *CommentStream, getRegisterName); 50892e18239308f8a02a4c83758616be84a459c19dChris Lattner} 51892e18239308f8a02a4c83758616be84a459c19dChris Lattner 52892e18239308f8a02a4c83758616be84a459c19dChris Lattnervoid X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op, 53892e18239308f8a02a4c83758616be84a459c19dChris Lattner raw_ostream &O) { 54892e18239308f8a02a4c83758616be84a459c19dChris Lattner int64_t Imm = MI->getOperand(Op).getImm() & 0xf; 55892e18239308f8a02a4c83758616be84a459c19dChris Lattner switch (Imm) { 56892e18239308f8a02a4c83758616be84a459c19dChris Lattner default: llvm_unreachable("Invalid ssecc argument!"); 57892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 0: O << "eq"; break; 58892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 1: O << "lt"; break; 59892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 2: O << "le"; break; 60892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 3: O << "unord"; break; 61892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 4: O << "neq"; break; 62892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 5: O << "nlt"; break; 63892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 6: O << "nle"; break; 64892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 7: O << "ord"; break; 65892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 8: O << "eq_uq"; break; 66892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 9: O << "nge"; break; 67892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 0xa: O << "ngt"; break; 68892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 0xb: O << "false"; break; 69892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 0xc: O << "neq_oq"; break; 70892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 0xd: O << "ge"; break; 71892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 0xe: O << "gt"; break; 72892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 0xf: O << "true"; break; 73892e18239308f8a02a4c83758616be84a459c19dChris Lattner } 74892e18239308f8a02a4c83758616be84a459c19dChris Lattner} 75892e18239308f8a02a4c83758616be84a459c19dChris Lattner 76892e18239308f8a02a4c83758616be84a459c19dChris Lattnervoid X86IntelInstPrinter::printAVXCC(const MCInst *MI, unsigned Op, 77892e18239308f8a02a4c83758616be84a459c19dChris Lattner raw_ostream &O) { 78892e18239308f8a02a4c83758616be84a459c19dChris Lattner int64_t Imm = MI->getOperand(Op).getImm() & 0x1f; 79892e18239308f8a02a4c83758616be84a459c19dChris Lattner switch (Imm) { 80892e18239308f8a02a4c83758616be84a459c19dChris Lattner default: llvm_unreachable("Invalid avxcc argument!"); 81892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 0: O << "eq"; break; 82892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 1: O << "lt"; break; 83892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 2: O << "le"; break; 84892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 3: O << "unord"; break; 85892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 4: O << "neq"; break; 86892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 5: O << "nlt"; break; 87892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 6: O << "nle"; break; 88892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 7: O << "ord"; break; 89892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 8: O << "eq_uq"; break; 90892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 9: O << "nge"; break; 91892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 0xa: O << "ngt"; break; 92892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 0xb: O << "false"; break; 93892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 0xc: O << "neq_oq"; break; 94892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 0xd: O << "ge"; break; 95892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 0xe: O << "gt"; break; 96892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 0xf: O << "true"; break; 97892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 0x10: O << "eq_os"; break; 98892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 0x11: O << "lt_oq"; break; 99892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 0x12: O << "le_oq"; break; 100892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 0x13: O << "unord_s"; break; 101892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 0x14: O << "neq_us"; break; 102892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 0x15: O << "nlt_uq"; break; 103892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 0x16: O << "nle_uq"; break; 104892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 0x17: O << "ord_s"; break; 105892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 0x18: O << "eq_us"; break; 106892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 0x19: O << "nge_uq"; break; 107892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 0x1a: O << "ngt_uq"; break; 108892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 0x1b: O << "false_os"; break; 109892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 0x1c: O << "neq_os"; break; 110892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 0x1d: O << "ge_oq"; break; 111892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 0x1e: O << "gt_oq"; break; 112892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 0x1f: O << "true_us"; break; 113892e18239308f8a02a4c83758616be84a459c19dChris Lattner } 114892e18239308f8a02a4c83758616be84a459c19dChris Lattner} 115a1c31b779cdde0090b8efcde87d7d0d898cabd38Chris Lattner 116a1c31b779cdde0090b8efcde87d7d0d898cabd38Chris Lattnervoid X86IntelInstPrinter::printRoundingControl(const MCInst *MI, unsigned Op, 117a1c31b779cdde0090b8efcde87d7d0d898cabd38Chris Lattner raw_ostream &O) { 118a1c31b779cdde0090b8efcde87d7d0d898cabd38Chris Lattner int64_t Imm = MI->getOperand(Op).getImm() & 0x3; 119a1c31b779cdde0090b8efcde87d7d0d898cabd38Chris Lattner switch (Imm) { 120a1c31b779cdde0090b8efcde87d7d0d898cabd38Chris Lattner case 0: O << "{rn-sae}"; break; 121892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 1: O << "{rd-sae}"; break; 122892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 2: O << "{ru-sae}"; break; 123892e18239308f8a02a4c83758616be84a459c19dChris Lattner case 3: O << "{rz-sae}"; break; 124892e18239308f8a02a4c83758616be84a459c19dChris Lattner } 125892e18239308f8a02a4c83758616be84a459c19dChris Lattner} 126892e18239308f8a02a4c83758616be84a459c19dChris Lattner 127892e18239308f8a02a4c83758616be84a459c19dChris Lattner/// printPCRelImm - This is used to print an immediate value that ends up 128892e18239308f8a02a4c83758616be84a459c19dChris Lattner/// being encoded as a pc-relative value. 129892e18239308f8a02a4c83758616be84a459c19dChris Lattnervoid X86IntelInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo, 130892e18239308f8a02a4c83758616be84a459c19dChris Lattner raw_ostream &O) { 131892e18239308f8a02a4c83758616be84a459c19dChris Lattner const MCOperand &Op = MI->getOperand(OpNo); 132a1c31b779cdde0090b8efcde87d7d0d898cabd38Chris Lattner if (Op.isImm()) 1337c599d056a41262681aa7fcd771eeed53a8e0bd2Chris Lattner O << formatImm(Op.getImm()); 134a1c31b779cdde0090b8efcde87d7d0d898cabd38Chris Lattner else { 1357c599d056a41262681aa7fcd771eeed53a8e0bd2Chris Lattner assert(Op.isExpr() && "unknown pcrel immediate operand"); 136a1c31b779cdde0090b8efcde87d7d0d898cabd38Chris Lattner // If a symbolic branch target was added as a constant expression then print 137a1c31b779cdde0090b8efcde87d7d0d898cabd38Chris Lattner // that address in hex. 138892e18239308f8a02a4c83758616be84a459c19dChris Lattner const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr()); 139892e18239308f8a02a4c83758616be84a459c19dChris Lattner int64_t Address; 140892e18239308f8a02a4c83758616be84a459c19dChris Lattner if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) { 141892e18239308f8a02a4c83758616be84a459c19dChris Lattner O << formatHex((uint64_t)Address); 142892e18239308f8a02a4c83758616be84a459c19dChris Lattner } 143892e18239308f8a02a4c83758616be84a459c19dChris Lattner else { 144892e18239308f8a02a4c83758616be84a459c19dChris Lattner // Otherwise, just print the expression. 145892e18239308f8a02a4c83758616be84a459c19dChris Lattner O << *Op.getExpr(); 146892e18239308f8a02a4c83758616be84a459c19dChris Lattner } 147892e18239308f8a02a4c83758616be84a459c19dChris Lattner } 148892e18239308f8a02a4c83758616be84a459c19dChris Lattner} 149892e18239308f8a02a4c83758616be84a459c19dChris Lattner 150892e18239308f8a02a4c83758616be84a459c19dChris Lattnervoid X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, 151892e18239308f8a02a4c83758616be84a459c19dChris Lattner raw_ostream &O) { 152 const MCOperand &Op = MI->getOperand(OpNo); 153 if (Op.isReg()) { 154 printRegName(O, Op.getReg()); 155 } else if (Op.isImm()) { 156 O << formatImm((int64_t)Op.getImm()); 157 } else { 158 assert(Op.isExpr() && "unknown operand kind in printOperand"); 159 O << *Op.getExpr(); 160 } 161} 162 163void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op, 164 raw_ostream &O) { 165 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); 166 unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm(); 167 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); 168 const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp); 169 const MCOperand &SegReg = MI->getOperand(Op+X86::AddrSegmentReg); 170 171 // If this has a segment register, print it. 172 if (SegReg.getReg()) { 173 printOperand(MI, Op+X86::AddrSegmentReg, O); 174 O << ':'; 175 } 176 177 O << '['; 178 179 bool NeedPlus = false; 180 if (BaseReg.getReg()) { 181 printOperand(MI, Op+X86::AddrBaseReg, O); 182 NeedPlus = true; 183 } 184 185 if (IndexReg.getReg()) { 186 if (NeedPlus) O << " + "; 187 if (ScaleVal != 1) 188 O << ScaleVal << '*'; 189 printOperand(MI, Op+X86::AddrIndexReg, O); 190 NeedPlus = true; 191 } 192 193 if (!DispSpec.isImm()) { 194 if (NeedPlus) O << " + "; 195 assert(DispSpec.isExpr() && "non-immediate displacement for LEA?"); 196 O << *DispSpec.getExpr(); 197 } else { 198 int64_t DispVal = DispSpec.getImm(); 199 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) { 200 if (NeedPlus) { 201 if (DispVal > 0) 202 O << " + "; 203 else { 204 O << " - "; 205 DispVal = -DispVal; 206 } 207 } 208 O << formatImm(DispVal); 209 } 210 } 211 212 O << ']'; 213} 214 215void X86IntelInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op, 216 raw_ostream &O) { 217 const MCOperand &SegReg = MI->getOperand(Op+1); 218 219 // If this has a segment register, print it. 220 if (SegReg.getReg()) { 221 printOperand(MI, Op+1, O); 222 O << ':'; 223 } 224 O << '['; 225 printOperand(MI, Op, O); 226 O << ']'; 227} 228 229void X86IntelInstPrinter::printDstIdx(const MCInst *MI, unsigned Op, 230 raw_ostream &O) { 231 // DI accesses are always ES-based. 232 O << "es:["; 233 printOperand(MI, Op, O); 234 O << ']'; 235} 236 237void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op, 238 raw_ostream &O) { 239 const MCOperand &DispSpec = MI->getOperand(Op); 240 const MCOperand &SegReg = MI->getOperand(Op+1); 241 242 // If this has a segment register, print it. 243 if (SegReg.getReg()) { 244 printOperand(MI, Op+1, O); 245 O << ':'; 246 } 247 248 O << '['; 249 250 if (DispSpec.isImm()) { 251 O << formatImm(DispSpec.getImm()); 252 } else { 253 assert(DispSpec.isExpr() && "non-immediate displacement?"); 254 O << *DispSpec.getExpr(); 255 } 256 257 O << ']'; 258} 259