X86IntelInstPrinter.cpp revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f 
1//===-- X86IntelInstPrinter.cpp - Intel assembly instruction printing -----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file includes code for rendering MCInst instances as Intel-style
11// assembly.
12//
13//===----------------------------------------------------------------------===//
14
15#include "X86IntelInstPrinter.h"
16#include "MCTargetDesc/X86BaseInfo.h"
17#include "MCTargetDesc/X86MCTargetDesc.h"
18#include "X86InstComments.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrInfo.h"
22#include "llvm/Support/ErrorHandling.h"
23#include "llvm/Support/FormattedStream.h"
24#include <cctype>
25using namespace llvm;
26
27#define DEBUG_TYPE "asm-printer"
28
29#include "X86GenAsmWriter1.inc"
30
31void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
32  OS << getRegisterName(RegNo);
33}
34
35void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
36                                    StringRef Annot) {
37  const MCInstrDesc &Desc = MII.get(MI->getOpcode());
38  uint64_t TSFlags = Desc.TSFlags;
39
40  if (TSFlags & X86II::LOCK)
41    OS << "\tlock\n";
42
43  printInstruction(MI, OS);
44
45  // Next always print the annotation.
46  printAnnotation(OS, Annot);
47
48  // If verbose assembly is enabled, we can print some informative comments.
49  if (CommentStream)
50    EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
51}
52
53void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
54                                     raw_ostream &O) {
55  int64_t Imm = MI->getOperand(Op).getImm() & 0xf;
56  switch (Imm) {
57  default: llvm_unreachable("Invalid ssecc argument!");
58  case    0: O << "eq"; break;
59  case    1: O << "lt"; break;
60  case    2: O << "le"; break;
61  case    3: O << "unord"; break;
62  case    4: O << "neq"; break;
63  case    5: O << "nlt"; break;
64  case    6: O << "nle"; break;
65  case    7: O << "ord"; break;
66  case    8: O << "eq_uq"; break;
67  case    9: O << "nge"; break;
68  case  0xa: O << "ngt"; break;
69  case  0xb: O << "false"; break;
70  case  0xc: O << "neq_oq"; break;
71  case  0xd: O << "ge"; break;
72  case  0xe: O << "gt"; break;
73  case  0xf: O << "true"; break;
74  }
75}
76
77void X86IntelInstPrinter::printAVXCC(const MCInst *MI, unsigned Op,
78                                     raw_ostream &O) {
79  int64_t Imm = MI->getOperand(Op).getImm() & 0x1f;
80  switch (Imm) {
81  default: llvm_unreachable("Invalid avxcc argument!");
82  case    0: O << "eq"; break;
83  case    1: O << "lt"; break;
84  case    2: O << "le"; break;
85  case    3: O << "unord"; break;
86  case    4: O << "neq"; break;
87  case    5: O << "nlt"; break;
88  case    6: O << "nle"; break;
89  case    7: O << "ord"; break;
90  case    8: O << "eq_uq"; break;
91  case    9: O << "nge"; break;
92  case  0xa: O << "ngt"; break;
93  case  0xb: O << "false"; break;
94  case  0xc: O << "neq_oq"; break;
95  case  0xd: O << "ge"; break;
96  case  0xe: O << "gt"; break;
97  case  0xf: O << "true"; break;
98  case 0x10: O << "eq_os"; break;
99  case 0x11: O << "lt_oq"; break;
100  case 0x12: O << "le_oq"; break;
101  case 0x13: O << "unord_s"; break;
102  case 0x14: O << "neq_us"; break;
103  case 0x15: O << "nlt_uq"; break;
104  case 0x16: O << "nle_uq"; break;
105  case 0x17: O << "ord_s"; break;
106  case 0x18: O << "eq_us"; break;
107  case 0x19: O << "nge_uq"; break;
108  case 0x1a: O << "ngt_uq"; break;
109  case 0x1b: O << "false_os"; break;
110  case 0x1c: O << "neq_os"; break;
111  case 0x1d: O << "ge_oq"; break;
112  case 0x1e: O << "gt_oq"; break;
113  case 0x1f: O << "true_us"; break;
114  }
115}
116
117void X86IntelInstPrinter::printRoundingControl(const MCInst *MI, unsigned Op,
118                                   raw_ostream &O) {
119  int64_t Imm = MI->getOperand(Op).getImm() & 0x3;
120  switch (Imm) {
121  case 0: O << "{rn-sae}"; break;
122  case 1: O << "{rd-sae}"; break;
123  case 2: O << "{ru-sae}"; break;
124  case 3: O << "{rz-sae}"; break;
125  }
126}
127
128/// printPCRelImm - This is used to print an immediate value that ends up
129/// being encoded as a pc-relative value.
130void X86IntelInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo,
131                                        raw_ostream &O) {
132  const MCOperand &Op = MI->getOperand(OpNo);
133  if (Op.isImm())
134    O << formatImm(Op.getImm());
135  else {
136    assert(Op.isExpr() && "unknown pcrel immediate operand");
137    // If a symbolic branch target was added as a constant expression then print
138    // that address in hex.
139    const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
140    int64_t Address;
141    if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
142      O << formatHex((uint64_t)Address);
143    }
144    else {
145      // Otherwise, just print the expression.
146      O << *Op.getExpr();
147    }
148  }
149}
150
151void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
152                                       raw_ostream &O) {
153  const MCOperand &Op = MI->getOperand(OpNo);
154  if (Op.isReg()) {
155    printRegName(O, Op.getReg());
156  } else if (Op.isImm()) {
157    O << formatImm((int64_t)Op.getImm());
158  } else {
159    assert(Op.isExpr() && "unknown operand kind in printOperand");
160    O << *Op.getExpr();
161  }
162}
163
164void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
165                                            raw_ostream &O) {
166  const MCOperand &BaseReg  = MI->getOperand(Op+X86::AddrBaseReg);
167  unsigned ScaleVal         = MI->getOperand(Op+X86::AddrScaleAmt).getImm();
168  const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
169  const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp);
170  const MCOperand &SegReg   = MI->getOperand(Op+X86::AddrSegmentReg);
171
172  // If this has a segment register, print it.
173  if (SegReg.getReg()) {
174    printOperand(MI, Op+X86::AddrSegmentReg, O);
175    O << ':';
176  }
177
178  O << '[';
179
180  bool NeedPlus = false;
181  if (BaseReg.getReg()) {
182    printOperand(MI, Op+X86::AddrBaseReg, O);
183    NeedPlus = true;
184  }
185
186  if (IndexReg.getReg()) {
187    if (NeedPlus) O << " + ";
188    if (ScaleVal != 1)
189      O << ScaleVal << '*';
190    printOperand(MI, Op+X86::AddrIndexReg, O);
191    NeedPlus = true;
192  }
193
194  if (!DispSpec.isImm()) {
195    if (NeedPlus) O << " + ";
196    assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
197    O << *DispSpec.getExpr();
198  } else {
199    int64_t DispVal = DispSpec.getImm();
200    if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
201      if (NeedPlus) {
202        if (DispVal > 0)
203          O << " + ";
204        else {
205          O << " - ";
206          DispVal = -DispVal;
207        }
208      }
209      O << formatImm(DispVal);
210    }
211  }
212
213  O << ']';
214}
215
216void X86IntelInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
217                                      raw_ostream &O) {
218  const MCOperand &SegReg   = MI->getOperand(Op+1);
219
220  // If this has a segment register, print it.
221  if (SegReg.getReg()) {
222    printOperand(MI, Op+1, O);
223    O << ':';
224  }
225  O << '[';
226  printOperand(MI, Op, O);
227  O << ']';
228}
229
230void X86IntelInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
231                                      raw_ostream &O) {
232  // DI accesses are always ES-based.
233  O << "es:[";
234  printOperand(MI, Op, O);
235  O << ']';
236}
237
238void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
239                                         raw_ostream &O) {
240  const MCOperand &DispSpec = MI->getOperand(Op);
241  const MCOperand &SegReg   = MI->getOperand(Op+1);
242
243  // If this has a segment register, print it.
244  if (SegReg.getReg()) {
245    printOperand(MI, Op+1, O);
246    O << ':';
247  }
248
249  O << '[';
250
251  if (DispSpec.isImm()) {
252    O << formatImm(DispSpec.getImm());
253  } else {
254    assert(DispSpec.isExpr() && "non-immediate displacement?");
255    O << *DispSpec.getExpr();
256  }
257
258  O << ']';
259}
260