X86AsmBackend.cpp revision 9ed81d16f71b60c246a7b8e9ed4fdd58a48ce4b9 
1//===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/X86BaseInfo.h"
11#include "MCTargetDesc/X86FixupKinds.h"
12#include "llvm/ADT/StringSwitch.h"
13#include "llvm/MC/MCAsmBackend.h"
14#include "llvm/MC/MCAssembler.h"
15#include "llvm/MC/MCELFObjectWriter.h"
16#include "llvm/MC/MCExpr.h"
17#include "llvm/MC/MCFixupKindInfo.h"
18#include "llvm/MC/MCMachObjectWriter.h"
19#include "llvm/MC/MCObjectWriter.h"
20#include "llvm/MC/MCSectionCOFF.h"
21#include "llvm/MC/MCSectionELF.h"
22#include "llvm/MC/MCSectionMachO.h"
23#include "llvm/Support/CommandLine.h"
24#include "llvm/Support/ELF.h"
25#include "llvm/Support/ErrorHandling.h"
26#include "llvm/Support/MachO.h"
27#include "llvm/Support/TargetRegistry.h"
28#include "llvm/Support/raw_ostream.h"
29using namespace llvm;
30
31// Option to allow disabling arithmetic relaxation to workaround PR9807, which
32// is useful when running bitwise comparison experiments on Darwin. We should be
33// able to remove this once PR9807 is resolved.
34static cl::opt<bool>
35MCDisableArithRelaxation("mc-x86-disable-arith-relaxation",
36         cl::desc("Disable relaxation of arithmetic instruction for X86"));
37
38static unsigned getFixupKindLog2Size(unsigned Kind) {
39  switch (Kind) {
40  default: llvm_unreachable("invalid fixup kind!");
41  case FK_PCRel_1:
42  case FK_SecRel_1:
43  case FK_Data_1: return 0;
44  case FK_PCRel_2:
45  case FK_SecRel_2:
46  case FK_Data_2: return 1;
47  case FK_PCRel_4:
48  case X86::reloc_riprel_4byte:
49  case X86::reloc_riprel_4byte_movq_load:
50  case X86::reloc_signed_4byte:
51  case X86::reloc_global_offset_table:
52  case FK_SecRel_4:
53  case FK_Data_4: return 2;
54  case FK_PCRel_8:
55  case FK_SecRel_8:
56  case FK_Data_8: return 3;
57  }
58}
59
60namespace {
61
62class X86ELFObjectWriter : public MCELFObjectTargetWriter {
63public:
64  X86ELFObjectWriter(bool is64Bit, uint8_t OSABI, uint16_t EMachine,
65                     bool HasRelocationAddend, bool foobar)
66    : MCELFObjectTargetWriter(is64Bit, OSABI, EMachine, HasRelocationAddend) {}
67};
68
69class X86AsmBackend : public MCAsmBackend {
70  StringRef CPU;
71public:
72  X86AsmBackend(const Target &T, StringRef _CPU)
73    : MCAsmBackend(), CPU(_CPU) {}
74
75  unsigned getNumFixupKinds() const {
76    return X86::NumTargetFixupKinds;
77  }
78
79  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
80    const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
81      { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
82      { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel},
83      { "reloc_signed_4byte", 0, 4 * 8, 0},
84      { "reloc_global_offset_table", 0, 4 * 8, 0}
85    };
86
87    if (Kind < FirstTargetFixupKind)
88      return MCAsmBackend::getFixupKindInfo(Kind);
89
90    assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
91           "Invalid kind!");
92    return Infos[Kind - FirstTargetFixupKind];
93  }
94
95  void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
96                  uint64_t Value) const {
97    unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
98
99    assert(Fixup.getOffset() + Size <= DataSize &&
100           "Invalid fixup offset!");
101
102    // Check that uppper bits are either all zeros or all ones.
103    // Specifically ignore overflow/underflow as long as the leakage is
104    // limited to the lower bits. This is to remain compatible with
105    // other assemblers.
106    assert(isIntN(Size * 8 + 1, Value) &&
107           "Value does not fit in the Fixup field");
108
109    for (unsigned i = 0; i != Size; ++i)
110      Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
111  }
112
113  bool mayNeedRelaxation(const MCInst &Inst) const;
114
115  bool fixupNeedsRelaxation(const MCFixup &Fixup,
116                            uint64_t Value,
117                            const MCRelaxableFragment *DF,
118                            const MCAsmLayout &Layout) const;
119
120  void relaxInstruction(const MCInst &Inst, MCInst &Res) const;
121
122  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const;
123};
124} // end anonymous namespace
125
126static unsigned getRelaxedOpcodeBranch(unsigned Op) {
127  switch (Op) {
128  default:
129    return Op;
130
131  case X86::JAE_1: return X86::JAE_4;
132  case X86::JA_1:  return X86::JA_4;
133  case X86::JBE_1: return X86::JBE_4;
134  case X86::JB_1:  return X86::JB_4;
135  case X86::JE_1:  return X86::JE_4;
136  case X86::JGE_1: return X86::JGE_4;
137  case X86::JG_1:  return X86::JG_4;
138  case X86::JLE_1: return X86::JLE_4;
139  case X86::JL_1:  return X86::JL_4;
140  case X86::JMP_1: return X86::JMP_4;
141  case X86::JNE_1: return X86::JNE_4;
142  case X86::JNO_1: return X86::JNO_4;
143  case X86::JNP_1: return X86::JNP_4;
144  case X86::JNS_1: return X86::JNS_4;
145  case X86::JO_1:  return X86::JO_4;
146  case X86::JP_1:  return X86::JP_4;
147  case X86::JS_1:  return X86::JS_4;
148  }
149}
150
151static unsigned getRelaxedOpcodeArith(unsigned Op) {
152  switch (Op) {
153  default:
154    return Op;
155
156    // IMUL
157  case X86::IMUL16rri8: return X86::IMUL16rri;
158  case X86::IMUL16rmi8: return X86::IMUL16rmi;
159  case X86::IMUL32rri8: return X86::IMUL32rri;
160  case X86::IMUL32rmi8: return X86::IMUL32rmi;
161  case X86::IMUL64rri8: return X86::IMUL64rri32;
162  case X86::IMUL64rmi8: return X86::IMUL64rmi32;
163
164    // AND
165  case X86::AND16ri8: return X86::AND16ri;
166  case X86::AND16mi8: return X86::AND16mi;
167  case X86::AND32ri8: return X86::AND32ri;
168  case X86::AND32mi8: return X86::AND32mi;
169  case X86::AND64ri8: return X86::AND64ri32;
170  case X86::AND64mi8: return X86::AND64mi32;
171
172    // OR
173  case X86::OR16ri8: return X86::OR16ri;
174  case X86::OR16mi8: return X86::OR16mi;
175  case X86::OR32ri8: return X86::OR32ri;
176  case X86::OR32mi8: return X86::OR32mi;
177  case X86::OR64ri8: return X86::OR64ri32;
178  case X86::OR64mi8: return X86::OR64mi32;
179
180    // XOR
181  case X86::XOR16ri8: return X86::XOR16ri;
182  case X86::XOR16mi8: return X86::XOR16mi;
183  case X86::XOR32ri8: return X86::XOR32ri;
184  case X86::XOR32mi8: return X86::XOR32mi;
185  case X86::XOR64ri8: return X86::XOR64ri32;
186  case X86::XOR64mi8: return X86::XOR64mi32;
187
188    // ADD
189  case X86::ADD16ri8: return X86::ADD16ri;
190  case X86::ADD16mi8: return X86::ADD16mi;
191  case X86::ADD32ri8: return X86::ADD32ri;
192  case X86::ADD32mi8: return X86::ADD32mi;
193  case X86::ADD64ri8: return X86::ADD64ri32;
194  case X86::ADD64mi8: return X86::ADD64mi32;
195
196    // SUB
197  case X86::SUB16ri8: return X86::SUB16ri;
198  case X86::SUB16mi8: return X86::SUB16mi;
199  case X86::SUB32ri8: return X86::SUB32ri;
200  case X86::SUB32mi8: return X86::SUB32mi;
201  case X86::SUB64ri8: return X86::SUB64ri32;
202  case X86::SUB64mi8: return X86::SUB64mi32;
203
204    // CMP
205  case X86::CMP16ri8: return X86::CMP16ri;
206  case X86::CMP16mi8: return X86::CMP16mi;
207  case X86::CMP32ri8: return X86::CMP32ri;
208  case X86::CMP32mi8: return X86::CMP32mi;
209  case X86::CMP64ri8: return X86::CMP64ri32;
210  case X86::CMP64mi8: return X86::CMP64mi32;
211
212    // PUSH
213  case X86::PUSHi8: return X86::PUSHi32;
214  case X86::PUSHi16: return X86::PUSHi32;
215  case X86::PUSH64i8: return X86::PUSH64i32;
216  case X86::PUSH64i16: return X86::PUSH64i32;
217  }
218}
219
220static unsigned getRelaxedOpcode(unsigned Op) {
221  unsigned R = getRelaxedOpcodeArith(Op);
222  if (R != Op)
223    return R;
224  return getRelaxedOpcodeBranch(Op);
225}
226
227bool X86AsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
228  // Branches can always be relaxed.
229  if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode())
230    return true;
231
232  if (MCDisableArithRelaxation)
233    return false;
234
235  // Check if this instruction is ever relaxable.
236  if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode())
237    return false;
238
239
240  // Check if it has an expression and is not RIP relative.
241  bool hasExp = false;
242  bool hasRIP = false;
243  for (unsigned i = 0; i < Inst.getNumOperands(); ++i) {
244    const MCOperand &Op = Inst.getOperand(i);
245    if (Op.isExpr())
246      hasExp = true;
247
248    if (Op.isReg() && Op.getReg() == X86::RIP)
249      hasRIP = true;
250  }
251
252  // FIXME: Why exactly do we need the !hasRIP? Is it just a limitation on
253  // how we do relaxations?
254  return hasExp && !hasRIP;
255}
256
257bool X86AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
258                                         uint64_t Value,
259                                         const MCRelaxableFragment *DF,
260                                         const MCAsmLayout &Layout) const {
261  // Relax if the value is too big for a (signed) i8.
262  return int64_t(Value) != int64_t(int8_t(Value));
263}
264
265// FIXME: Can tblgen help at all here to verify there aren't other instructions
266// we can relax?
267void X86AsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const {
268  // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
269  unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
270
271  if (RelaxedOp == Inst.getOpcode()) {
272    SmallString<256> Tmp;
273    raw_svector_ostream OS(Tmp);
274    Inst.dump_pretty(OS);
275    OS << "\n";
276    report_fatal_error("unexpected instruction to relax: " + OS.str());
277  }
278
279  Res = Inst;
280  Res.setOpcode(RelaxedOp);
281}
282
283/// \brief Write a sequence of optimal nops to the output, covering \p Count
284/// bytes.
285/// \return - true on success, false on failure
286bool X86AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
287  static const uint8_t Nops[10][10] = {
288    // nop
289    {0x90},
290    // xchg %ax,%ax
291    {0x66, 0x90},
292    // nopl (%[re]ax)
293    {0x0f, 0x1f, 0x00},
294    // nopl 0(%[re]ax)
295    {0x0f, 0x1f, 0x40, 0x00},
296    // nopl 0(%[re]ax,%[re]ax,1)
297    {0x0f, 0x1f, 0x44, 0x00, 0x00},
298    // nopw 0(%[re]ax,%[re]ax,1)
299    {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
300    // nopl 0L(%[re]ax)
301    {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
302    // nopl 0L(%[re]ax,%[re]ax,1)
303    {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
304    // nopw 0L(%[re]ax,%[re]ax,1)
305    {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
306    // nopw %cs:0L(%[re]ax,%[re]ax,1)
307    {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
308  };
309
310  // This CPU doesnt support long nops. If needed add more.
311  // FIXME: Can we get this from the subtarget somehow?
312  // FIXME: We could generated something better than plain 0x90.
313  if (CPU == "generic" || CPU == "i386" || CPU == "i486" || CPU == "i586" ||
314      CPU == "pentium" || CPU == "pentium-mmx" || CPU == "i686" ||
315      CPU == "k6" || CPU == "k6-2" || CPU == "k6-3" || CPU == "geode" ||
316      CPU == "winchip-c6" || CPU == "winchip2" || CPU == "c3" ||
317      CPU == "c3-2") {
318    for (uint64_t i = 0; i < Count; ++i)
319      OW->Write8(0x90);
320    return true;
321  }
322
323  // 15 is the longest single nop instruction.  Emit as many 15-byte nops as
324  // needed, then emit a nop of the remaining length.
325  do {
326    const uint8_t ThisNopLength = (uint8_t) std::min(Count, (uint64_t) 15);
327    const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10;
328    for (uint8_t i = 0; i < Prefixes; i++)
329      OW->Write8(0x66);
330    const uint8_t Rest = ThisNopLength - Prefixes;
331    for (uint8_t i = 0; i < Rest; i++)
332      OW->Write8(Nops[Rest - 1][i]);
333    Count -= ThisNopLength;
334  } while (Count != 0);
335
336  return true;
337}
338
339/* *** */
340
341namespace {
342
343class ELFX86AsmBackend : public X86AsmBackend {
344public:
345  uint8_t OSABI;
346  ELFX86AsmBackend(const Target &T, uint8_t _OSABI, StringRef CPU)
347    : X86AsmBackend(T, CPU), OSABI(_OSABI) {
348    HasReliableSymbolDifference = true;
349  }
350
351  virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
352    const MCSectionELF &ES = static_cast<const MCSectionELF&>(Section);
353    return ES.getFlags() & ELF::SHF_MERGE;
354  }
355};
356
357class ELFX86_32AsmBackend : public ELFX86AsmBackend {
358public:
359  ELFX86_32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
360    : ELFX86AsmBackend(T, OSABI, CPU) {}
361
362  MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
363    return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI, ELF::EM_386);
364  }
365};
366
367class ELFX86_64AsmBackend : public ELFX86AsmBackend {
368public:
369  ELFX86_64AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
370    : ELFX86AsmBackend(T, OSABI, CPU) {}
371
372  MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
373    return createX86ELFObjectWriter(OS, /*IsELF64*/ true, OSABI, ELF::EM_X86_64);
374  }
375};
376
377class WindowsX86AsmBackend : public X86AsmBackend {
378  bool Is64Bit;
379
380public:
381  WindowsX86AsmBackend(const Target &T, bool is64Bit, StringRef CPU)
382    : X86AsmBackend(T, CPU)
383    , Is64Bit(is64Bit) {
384  }
385
386  MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
387    return createX86WinCOFFObjectWriter(OS, Is64Bit);
388  }
389};
390
391namespace CU {
392
393  /// Compact unwind encoding values.
394  enum CompactUnwindEncodings {
395    /// [RE]BP based frame where [RE]BP is pused on the stack immediately after
396    /// the return address, then [RE]SP is moved to [RE]BP.
397    UNWIND_MODE_BP_FRAME                   = 0x01000000,
398
399    /// A frameless function with a small constant stack size.
400    UNWIND_MODE_STACK_IMMD                 = 0x02000000,
401
402    /// A frameless function with a large constant stack size.
403    UNWIND_MODE_STACK_IND                  = 0x03000000,
404
405    /// No compact unwind encoding is available.
406    UNWIND_MODE_DWARF                      = 0x04000000,
407
408    /// Mask for encoding the frame registers.
409    UNWIND_BP_FRAME_REGISTERS              = 0x00007FFF,
410
411    /// Mask for encoding the frameless registers.
412    UNWIND_FRAMELESS_STACK_REG_PERMUTATION = 0x000003FF
413  };
414
415} // end CU namespace
416
417class DarwinX86AsmBackend : public X86AsmBackend {
418  const MCRegisterInfo &MRI;
419
420  /// \brief Number of registers that can be saved in a compact unwind encoding.
421  enum { CU_NUM_SAVED_REGS = 6 };
422
423  mutable unsigned SavedRegs[CU_NUM_SAVED_REGS];
424  bool Is64Bit;
425
426  unsigned OffsetSize;                   ///< Offset of a "push" instruction.
427  unsigned PushInstrSize;                ///< Size of a "push" instruction.
428  unsigned MoveInstrSize;                ///< Size of a "move" instruction.
429  unsigned StackDivide;                  ///< Amount to adjust stack stize by.
430protected:
431  /// \brief Implementation of algorithm to generate the compact unwind encoding
432  /// for the CFI instructions.
433  uint32_t
434  generateCompactUnwindEncodingImpl(ArrayRef<MCCFIInstruction> Instrs) const {
435    if (Instrs.empty()) return 0;
436
437    // Reset the saved registers.
438    unsigned SavedRegIdx = 0;
439    memset(SavedRegs, 0, sizeof(SavedRegs));
440
441    bool HasFP = false;
442
443    // Encode that we are using EBP/RBP as the frame pointer.
444    uint32_t CompactUnwindEncoding = 0;
445
446    unsigned SubtractInstrIdx = Is64Bit ? 3 : 2;
447    unsigned InstrOffset = 0;
448    unsigned StackAdjust = 0;
449    unsigned StackSize = 0;
450    unsigned PrevStackSize = 0;
451    unsigned NumDefCFAOffsets = 0;
452
453    for (unsigned i = 0, e = Instrs.size(); i != e; ++i) {
454      const MCCFIInstruction &Inst = Instrs[i];
455
456      switch (Inst.getOperation()) {
457      default:
458        // Any other CFI directives indicate a frame that we aren't prepared
459        // to represent via compact unwind, so just bail out.
460        return 0;
461      case MCCFIInstruction::OpDefCfaRegister: {
462        // Defines a frame pointer. E.g.
463        //
464        //     movq %rsp, %rbp
465        //  L0:
466        //     .cfi_def_cfa_register %rbp
467        //
468        HasFP = true;
469        assert(MRI.getLLVMRegNum(Inst.getRegister(), true) ==
470               (Is64Bit ? X86::RBP : X86::EBP) && "Invalid frame pointer!");
471
472        // Reset the counts.
473        memset(SavedRegs, 0, sizeof(SavedRegs));
474        StackAdjust = 0;
475        SavedRegIdx = 0;
476        InstrOffset += MoveInstrSize;
477        break;
478      }
479      case MCCFIInstruction::OpDefCfaOffset: {
480        // Defines a new offset for the CFA. E.g.
481        //
482        //  With frame:
483        //
484        //     pushq %rbp
485        //  L0:
486        //     .cfi_def_cfa_offset 16
487        //
488        //  Without frame:
489        //
490        //     subq $72, %rsp
491        //  L0:
492        //     .cfi_def_cfa_offset 80
493        //
494        PrevStackSize = StackSize;
495        StackSize = std::abs(Inst.getOffset()) / StackDivide;
496        ++NumDefCFAOffsets;
497        break;
498      }
499      case MCCFIInstruction::OpOffset: {
500        // Defines a "push" of a callee-saved register. E.g.
501        //
502        //     pushq %r15
503        //     pushq %r14
504        //     pushq %rbx
505        //  L0:
506        //     subq $120, %rsp
507        //  L1:
508        //     .cfi_offset %rbx, -40
509        //     .cfi_offset %r14, -32
510        //     .cfi_offset %r15, -24
511        //
512        if (SavedRegIdx == CU_NUM_SAVED_REGS)
513          // If there are too many saved registers, we cannot use a compact
514          // unwind encoding.
515          return CU::UNWIND_MODE_DWARF;
516
517        unsigned Reg = MRI.getLLVMRegNum(Inst.getRegister(), true);
518        SavedRegs[SavedRegIdx++] = Reg;
519        StackAdjust += OffsetSize;
520        InstrOffset += PushInstrSize;
521        break;
522      }
523      }
524    }
525
526    StackAdjust /= StackDivide;
527
528    if (HasFP) {
529      if ((StackAdjust & 0xFF) != StackAdjust)
530        // Offset was too big for a compact unwind encoding.
531        return CU::UNWIND_MODE_DWARF;
532
533      // Get the encoding of the saved registers when we have a frame pointer.
534      uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame();
535      if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;
536
537      CompactUnwindEncoding |= CU::UNWIND_MODE_BP_FRAME;
538      CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16;
539      CompactUnwindEncoding |= RegEnc & CU::UNWIND_BP_FRAME_REGISTERS;
540    } else {
541      // If the amount of the stack allocation is the size of a register, then
542      // we "push" the RAX/EAX register onto the stack instead of adjusting the
543      // stack pointer with a SUB instruction. We don't support the push of the
544      // RAX/EAX register with compact unwind. So we check for that situation
545      // here.
546      if ((NumDefCFAOffsets == SavedRegIdx + 1 &&
547           StackSize - PrevStackSize == 1) ||
548          (Instrs.size() == 1 && NumDefCFAOffsets == 1 && StackSize == 2))
549        return CU::UNWIND_MODE_DWARF;
550
551      SubtractInstrIdx += InstrOffset;
552      ++StackAdjust;
553
554      if ((StackSize & 0xFF) == StackSize) {
555        // Frameless stack with a small stack size.
556        CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IMMD;
557
558        // Encode the stack size.
559        CompactUnwindEncoding |= (StackSize & 0xFF) << 16;
560      } else {
561        if ((StackAdjust & 0x7) != StackAdjust)
562          // The extra stack adjustments are too big for us to handle.
563          return CU::UNWIND_MODE_DWARF;
564
565        // Frameless stack with an offset too large for us to encode compactly.
566        CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IND;
567
568        // Encode the offset to the nnnnnn value in the 'subl $nnnnnn, ESP'
569        // instruction.
570        CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16;
571
572        // Encode any extra stack stack adjustments (done via push
573        // instructions).
574        CompactUnwindEncoding |= (StackAdjust & 0x7) << 13;
575      }
576
577      // Encode the number of registers saved. (Reverse the list first.)
578      std::reverse(&SavedRegs[0], &SavedRegs[SavedRegIdx]);
579      CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10;
580
581      // Get the encoding of the saved registers when we don't have a frame
582      // pointer.
583      uint32_t RegEnc = encodeCompactUnwindRegistersWithoutFrame(SavedRegIdx);
584      if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;
585
586      // Encode the register encoding.
587      CompactUnwindEncoding |=
588        RegEnc & CU::UNWIND_FRAMELESS_STACK_REG_PERMUTATION;
589    }
590
591    return CompactUnwindEncoding;
592  }
593
594private:
595  /// \brief Get the compact unwind number for a given register. The number
596  /// corresponds to the enum lists in compact_unwind_encoding.h.
597  int getCompactUnwindRegNum(unsigned Reg) const {
598    static const uint16_t CU32BitRegs[7] = {
599      X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
600    };
601    static const uint16_t CU64BitRegs[] = {
602      X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
603    };
604    const uint16_t *CURegs = Is64Bit ? CU64BitRegs : CU32BitRegs;
605    for (int Idx = 1; *CURegs; ++CURegs, ++Idx)
606      if (*CURegs == Reg)
607        return Idx;
608
609    return -1;
610  }
611
612  /// \brief Return the registers encoded for a compact encoding with a frame
613  /// pointer.
614  uint32_t encodeCompactUnwindRegistersWithFrame() const {
615    // Encode the registers in the order they were saved --- 3-bits per
616    // register. The list of saved registers is assumed to be in reverse
617    // order. The registers are numbered from 1 to CU_NUM_SAVED_REGS.
618    uint32_t RegEnc = 0;
619    for (int i = 0, Idx = 0; i != CU_NUM_SAVED_REGS; ++i) {
620      unsigned Reg = SavedRegs[i];
621      if (Reg == 0) break;
622
623      int CURegNum = getCompactUnwindRegNum(Reg);
624      if (CURegNum == -1) return ~0U;
625
626      // Encode the 3-bit register number in order, skipping over 3-bits for
627      // each register.
628      RegEnc |= (CURegNum & 0x7) << (Idx++ * 3);
629    }
630
631    assert((RegEnc & 0x3FFFF) == RegEnc &&
632           "Invalid compact register encoding!");
633    return RegEnc;
634  }
635
636  /// \brief Create the permutation encoding used with frameless stacks. It is
637  /// passed the number of registers to be saved and an array of the registers
638  /// saved.
639  uint32_t encodeCompactUnwindRegistersWithoutFrame(unsigned RegCount) const {
640    // The saved registers are numbered from 1 to 6. In order to encode the
641    // order in which they were saved, we re-number them according to their
642    // place in the register order. The re-numbering is relative to the last
643    // re-numbered register. E.g., if we have registers {6, 2, 4, 5} saved in
644    // that order:
645    //
646    //    Orig  Re-Num
647    //    ----  ------
648    //     6       6
649    //     2       2
650    //     4       3
651    //     5       3
652    //
653    for (unsigned i = 0; i != CU_NUM_SAVED_REGS; ++i) {
654      int CUReg = getCompactUnwindRegNum(SavedRegs[i]);
655      if (CUReg == -1) return ~0U;
656      SavedRegs[i] = CUReg;
657    }
658
659    // Reverse the list.
660    std::reverse(&SavedRegs[0], &SavedRegs[CU_NUM_SAVED_REGS]);
661
662    uint32_t RenumRegs[CU_NUM_SAVED_REGS];
663    for (unsigned i = CU_NUM_SAVED_REGS - RegCount; i < CU_NUM_SAVED_REGS; ++i){
664      unsigned Countless = 0;
665      for (unsigned j = CU_NUM_SAVED_REGS - RegCount; j < i; ++j)
666        if (SavedRegs[j] < SavedRegs[i])
667          ++Countless;
668
669      RenumRegs[i] = SavedRegs[i] - Countless - 1;
670    }
671
672    // Take the renumbered values and encode them into a 10-bit number.
673    uint32_t permutationEncoding = 0;
674    switch (RegCount) {
675    case 6:
676      permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1]
677                             + 6 * RenumRegs[2] +  2 * RenumRegs[3]
678                             +     RenumRegs[4];
679      break;
680    case 5:
681      permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2]
682                             + 6 * RenumRegs[3] +  2 * RenumRegs[4]
683                             +     RenumRegs[5];
684      break;
685    case 4:
686      permutationEncoding |=  60 * RenumRegs[2] + 12 * RenumRegs[3]
687                             + 3 * RenumRegs[4] +      RenumRegs[5];
688      break;
689    case 3:
690      permutationEncoding |=  20 * RenumRegs[3] +  4 * RenumRegs[4]
691                             +     RenumRegs[5];
692      break;
693    case 2:
694      permutationEncoding |=   5 * RenumRegs[4] +      RenumRegs[5];
695      break;
696    case 1:
697      permutationEncoding |=       RenumRegs[5];
698      break;
699    }
700
701    assert((permutationEncoding & 0x3FF) == permutationEncoding &&
702           "Invalid compact register encoding!");
703    return permutationEncoding;
704  }
705
706public:
707  DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef CPU,
708                      bool Is64Bit)
709    : X86AsmBackend(T, CPU), MRI(MRI), Is64Bit(Is64Bit) {
710    memset(SavedRegs, 0, sizeof(SavedRegs));
711    OffsetSize = Is64Bit ? 8 : 4;
712    MoveInstrSize = Is64Bit ? 3 : 2;
713    StackDivide = Is64Bit ? 8 : 4;
714    PushInstrSize = 1;
715  }
716};
717
718class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
719  bool SupportsCU;
720public:
721  DarwinX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,
722                         StringRef CPU, bool SupportsCU)
723    : DarwinX86AsmBackend(T, MRI, CPU, false), SupportsCU(SupportsCU) {}
724
725  MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
726    return createX86MachObjectWriter(OS, /*Is64Bit=*/false,
727                                     MachO::CPU_TYPE_I386,
728                                     MachO::CPU_SUBTYPE_I386_ALL);
729  }
730
731  /// \brief Generate the compact unwind encoding for the CFI instructions.
732  virtual uint32_t
733  generateCompactUnwindEncoding(ArrayRef<MCCFIInstruction> Instrs) const {
734    return SupportsCU ? generateCompactUnwindEncodingImpl(Instrs) : 0;
735  }
736};
737
738class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
739  bool SupportsCU;
740  const MachO::CPUSubTypeX86 Subtype;
741public:
742  DarwinX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI,
743                         StringRef CPU, bool SupportsCU,
744                         MachO::CPUSubTypeX86 st)
745    : DarwinX86AsmBackend(T, MRI, CPU, true), SupportsCU(SupportsCU),
746      Subtype(st) {
747    HasReliableSymbolDifference = true;
748  }
749
750  MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
751    return createX86MachObjectWriter(OS, /*Is64Bit=*/true,
752                                     MachO::CPU_TYPE_X86_64, Subtype);
753  }
754
755  virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
756    // Temporary labels in the string literals sections require symbols. The
757    // issue is that the x86_64 relocation format does not allow symbol +
758    // offset, and so the linker does not have enough information to resolve the
759    // access to the appropriate atom unless an external relocation is used. For
760    // non-cstring sections, we expect the compiler to use a non-temporary label
761    // for anything that could have an addend pointing outside the symbol.
762    //
763    // See <rdar://problem/4765733>.
764    const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
765    return SMO.getType() == MCSectionMachO::S_CSTRING_LITERALS;
766  }
767
768  virtual bool isSectionAtomizable(const MCSection &Section) const {
769    const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
770    // Fixed sized data sections are uniqued, they cannot be diced into atoms.
771    switch (SMO.getType()) {
772    default:
773      return true;
774
775    case MCSectionMachO::S_4BYTE_LITERALS:
776    case MCSectionMachO::S_8BYTE_LITERALS:
777    case MCSectionMachO::S_16BYTE_LITERALS:
778    case MCSectionMachO::S_LITERAL_POINTERS:
779    case MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS:
780    case MCSectionMachO::S_LAZY_SYMBOL_POINTERS:
781    case MCSectionMachO::S_MOD_INIT_FUNC_POINTERS:
782    case MCSectionMachO::S_MOD_TERM_FUNC_POINTERS:
783    case MCSectionMachO::S_INTERPOSING:
784      return false;
785    }
786  }
787
788  /// \brief Generate the compact unwind encoding for the CFI instructions.
789  virtual uint32_t
790  generateCompactUnwindEncoding(ArrayRef<MCCFIInstruction> Instrs) const {
791    return SupportsCU ? generateCompactUnwindEncodingImpl(Instrs) : 0;
792  }
793};
794
795} // end anonymous namespace
796
797MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
798                                           const MCRegisterInfo &MRI,
799                                           StringRef TT,
800                                           StringRef CPU) {
801  Triple TheTriple(TT);
802
803  if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
804    return new DarwinX86_32AsmBackend(T, MRI, CPU,
805                                      TheTriple.isMacOSX() &&
806                                      !TheTriple.isMacOSXVersionLT(10, 7));
807
808  if (TheTriple.isOSWindows() && TheTriple.getEnvironment() != Triple::ELF)
809    return new WindowsX86AsmBackend(T, false, CPU);
810
811  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
812  return new ELFX86_32AsmBackend(T, OSABI, CPU);
813}
814
815MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
816                                           const MCRegisterInfo &MRI,
817                                           StringRef TT,
818                                           StringRef CPU) {
819  Triple TheTriple(TT);
820
821  if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO) {
822    MachO::CPUSubTypeX86 CS =
823        StringSwitch<MachO::CPUSubTypeX86>(TheTriple.getArchName())
824            .Case("x86_64h", MachO::CPU_SUBTYPE_X86_64_H)
825            .Default(MachO::CPU_SUBTYPE_X86_64_ALL);
826    return new DarwinX86_64AsmBackend(T, MRI, CPU,
827                                      TheTriple.isMacOSX() &&
828                                      !TheTriple.isMacOSXVersionLT(10, 7), CS);
829  }
830
831  if (TheTriple.isOSWindows() && TheTriple.getEnvironment() != Triple::ELF)
832    return new WindowsX86AsmBackend(T, true, CPU);
833
834  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
835  return new ELFX86_64AsmBackend(T, OSABI, CPU);
836}
837