X86AsmBackend.cpp revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f 
1//===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/X86BaseInfo.h"
11#include "MCTargetDesc/X86FixupKinds.h"
12#include "llvm/ADT/StringSwitch.h"
13#include "llvm/MC/MCAsmBackend.h"
14#include "llvm/MC/MCAssembler.h"
15#include "llvm/MC/MCELFObjectWriter.h"
16#include "llvm/MC/MCExpr.h"
17#include "llvm/MC/MCFixupKindInfo.h"
18#include "llvm/MC/MCMachObjectWriter.h"
19#include "llvm/MC/MCObjectWriter.h"
20#include "llvm/MC/MCSectionCOFF.h"
21#include "llvm/MC/MCSectionELF.h"
22#include "llvm/MC/MCSectionMachO.h"
23#include "llvm/Support/CommandLine.h"
24#include "llvm/Support/ELF.h"
25#include "llvm/Support/ErrorHandling.h"
26#include "llvm/Support/MachO.h"
27#include "llvm/Support/TargetRegistry.h"
28#include "llvm/Support/raw_ostream.h"
29using namespace llvm;
30
31// Option to allow disabling arithmetic relaxation to workaround PR9807, which
32// is useful when running bitwise comparison experiments on Darwin. We should be
33// able to remove this once PR9807 is resolved.
34static cl::opt<bool>
35MCDisableArithRelaxation("mc-x86-disable-arith-relaxation",
36         cl::desc("Disable relaxation of arithmetic instruction for X86"));
37
38static unsigned getFixupKindLog2Size(unsigned Kind) {
39  switch (Kind) {
40  default:
41    llvm_unreachable("invalid fixup kind!");
42  case FK_PCRel_1:
43  case FK_SecRel_1:
44  case FK_Data_1:
45    return 0;
46  case FK_PCRel_2:
47  case FK_SecRel_2:
48  case FK_Data_2:
49    return 1;
50  case FK_PCRel_4:
51  case X86::reloc_riprel_4byte:
52  case X86::reloc_riprel_4byte_movq_load:
53  case X86::reloc_signed_4byte:
54  case X86::reloc_global_offset_table:
55  case FK_SecRel_4:
56  case FK_Data_4:
57    return 2;
58  case FK_PCRel_8:
59  case FK_SecRel_8:
60  case FK_Data_8:
61  case X86::reloc_global_offset_table8:
62    return 3;
63  }
64}
65
66namespace {
67
68class X86ELFObjectWriter : public MCELFObjectTargetWriter {
69public:
70  X86ELFObjectWriter(bool is64Bit, uint8_t OSABI, uint16_t EMachine,
71                     bool HasRelocationAddend, bool foobar)
72    : MCELFObjectTargetWriter(is64Bit, OSABI, EMachine, HasRelocationAddend) {}
73};
74
75class X86AsmBackend : public MCAsmBackend {
76  StringRef CPU;
77  bool HasNopl;
78public:
79  X86AsmBackend(const Target &T, StringRef _CPU)
80    : MCAsmBackend(), CPU(_CPU) {
81    HasNopl = CPU != "generic" && CPU != "i386" && CPU != "i486" &&
82              CPU != "i586" && CPU != "pentium" && CPU != "pentium-mmx" &&
83              CPU != "i686" && CPU != "k6" && CPU != "k6-2" && CPU != "k6-3" &&
84              CPU != "geode" && CPU != "winchip-c6" && CPU != "winchip2" &&
85              CPU != "c3" && CPU != "c3-2";
86  }
87
88  unsigned getNumFixupKinds() const override {
89    return X86::NumTargetFixupKinds;
90  }
91
92  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
93    const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
94      { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
95      { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel},
96      { "reloc_signed_4byte", 0, 4 * 8, 0},
97      { "reloc_global_offset_table", 0, 4 * 8, 0}
98    };
99
100    if (Kind < FirstTargetFixupKind)
101      return MCAsmBackend::getFixupKindInfo(Kind);
102
103    assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
104           "Invalid kind!");
105    return Infos[Kind - FirstTargetFixupKind];
106  }
107
108  void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
109                  uint64_t Value, bool IsPCRel) const override {
110    unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
111
112    assert(Fixup.getOffset() + Size <= DataSize &&
113           "Invalid fixup offset!");
114
115    // Check that uppper bits are either all zeros or all ones.
116    // Specifically ignore overflow/underflow as long as the leakage is
117    // limited to the lower bits. This is to remain compatible with
118    // other assemblers.
119    assert(isIntN(Size * 8 + 1, Value) &&
120           "Value does not fit in the Fixup field");
121
122    for (unsigned i = 0; i != Size; ++i)
123      Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
124  }
125
126  bool mayNeedRelaxation(const MCInst &Inst) const override;
127
128  bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
129                            const MCRelaxableFragment *DF,
130                            const MCAsmLayout &Layout) const override;
131
132  void relaxInstruction(const MCInst &Inst, MCInst &Res) const override;
133
134  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
135};
136} // end anonymous namespace
137
138static unsigned getRelaxedOpcodeBranch(unsigned Op) {
139  switch (Op) {
140  default:
141    return Op;
142
143  case X86::JAE_1: return X86::JAE_4;
144  case X86::JA_1:  return X86::JA_4;
145  case X86::JBE_1: return X86::JBE_4;
146  case X86::JB_1:  return X86::JB_4;
147  case X86::JE_1:  return X86::JE_4;
148  case X86::JGE_1: return X86::JGE_4;
149  case X86::JG_1:  return X86::JG_4;
150  case X86::JLE_1: return X86::JLE_4;
151  case X86::JL_1:  return X86::JL_4;
152  case X86::JMP_1: return X86::JMP_4;
153  case X86::JNE_1: return X86::JNE_4;
154  case X86::JNO_1: return X86::JNO_4;
155  case X86::JNP_1: return X86::JNP_4;
156  case X86::JNS_1: return X86::JNS_4;
157  case X86::JO_1:  return X86::JO_4;
158  case X86::JP_1:  return X86::JP_4;
159  case X86::JS_1:  return X86::JS_4;
160  }
161}
162
163static unsigned getRelaxedOpcodeArith(unsigned Op) {
164  switch (Op) {
165  default:
166    return Op;
167
168    // IMUL
169  case X86::IMUL16rri8: return X86::IMUL16rri;
170  case X86::IMUL16rmi8: return X86::IMUL16rmi;
171  case X86::IMUL32rri8: return X86::IMUL32rri;
172  case X86::IMUL32rmi8: return X86::IMUL32rmi;
173  case X86::IMUL64rri8: return X86::IMUL64rri32;
174  case X86::IMUL64rmi8: return X86::IMUL64rmi32;
175
176    // AND
177  case X86::AND16ri8: return X86::AND16ri;
178  case X86::AND16mi8: return X86::AND16mi;
179  case X86::AND32ri8: return X86::AND32ri;
180  case X86::AND32mi8: return X86::AND32mi;
181  case X86::AND64ri8: return X86::AND64ri32;
182  case X86::AND64mi8: return X86::AND64mi32;
183
184    // OR
185  case X86::OR16ri8: return X86::OR16ri;
186  case X86::OR16mi8: return X86::OR16mi;
187  case X86::OR32ri8: return X86::OR32ri;
188  case X86::OR32mi8: return X86::OR32mi;
189  case X86::OR64ri8: return X86::OR64ri32;
190  case X86::OR64mi8: return X86::OR64mi32;
191
192    // XOR
193  case X86::XOR16ri8: return X86::XOR16ri;
194  case X86::XOR16mi8: return X86::XOR16mi;
195  case X86::XOR32ri8: return X86::XOR32ri;
196  case X86::XOR32mi8: return X86::XOR32mi;
197  case X86::XOR64ri8: return X86::XOR64ri32;
198  case X86::XOR64mi8: return X86::XOR64mi32;
199
200    // ADD
201  case X86::ADD16ri8: return X86::ADD16ri;
202  case X86::ADD16mi8: return X86::ADD16mi;
203  case X86::ADD32ri8: return X86::ADD32ri;
204  case X86::ADD32mi8: return X86::ADD32mi;
205  case X86::ADD64ri8: return X86::ADD64ri32;
206  case X86::ADD64mi8: return X86::ADD64mi32;
207
208    // SUB
209  case X86::SUB16ri8: return X86::SUB16ri;
210  case X86::SUB16mi8: return X86::SUB16mi;
211  case X86::SUB32ri8: return X86::SUB32ri;
212  case X86::SUB32mi8: return X86::SUB32mi;
213  case X86::SUB64ri8: return X86::SUB64ri32;
214  case X86::SUB64mi8: return X86::SUB64mi32;
215
216    // CMP
217  case X86::CMP16ri8: return X86::CMP16ri;
218  case X86::CMP16mi8: return X86::CMP16mi;
219  case X86::CMP32ri8: return X86::CMP32ri;
220  case X86::CMP32mi8: return X86::CMP32mi;
221  case X86::CMP64ri8: return X86::CMP64ri32;
222  case X86::CMP64mi8: return X86::CMP64mi32;
223
224    // PUSH
225  case X86::PUSH32i8:  return X86::PUSHi32;
226  case X86::PUSH16i8:  return X86::PUSHi16;
227  case X86::PUSH64i8:  return X86::PUSH64i32;
228  case X86::PUSH64i16: return X86::PUSH64i32;
229  }
230}
231
232static unsigned getRelaxedOpcode(unsigned Op) {
233  unsigned R = getRelaxedOpcodeArith(Op);
234  if (R != Op)
235    return R;
236  return getRelaxedOpcodeBranch(Op);
237}
238
239bool X86AsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
240  // Branches can always be relaxed.
241  if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode())
242    return true;
243
244  if (MCDisableArithRelaxation)
245    return false;
246
247  // Check if this instruction is ever relaxable.
248  if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode())
249    return false;
250
251
252  // Check if it has an expression and is not RIP relative.
253  bool hasExp = false;
254  bool hasRIP = false;
255  for (unsigned i = 0; i < Inst.getNumOperands(); ++i) {
256    const MCOperand &Op = Inst.getOperand(i);
257    if (Op.isExpr())
258      hasExp = true;
259
260    if (Op.isReg() && Op.getReg() == X86::RIP)
261      hasRIP = true;
262  }
263
264  // FIXME: Why exactly do we need the !hasRIP? Is it just a limitation on
265  // how we do relaxations?
266  return hasExp && !hasRIP;
267}
268
269bool X86AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
270                                         uint64_t Value,
271                                         const MCRelaxableFragment *DF,
272                                         const MCAsmLayout &Layout) const {
273  // Relax if the value is too big for a (signed) i8.
274  return int64_t(Value) != int64_t(int8_t(Value));
275}
276
277// FIXME: Can tblgen help at all here to verify there aren't other instructions
278// we can relax?
279void X86AsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const {
280  // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
281  unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
282
283  if (RelaxedOp == Inst.getOpcode()) {
284    SmallString<256> Tmp;
285    raw_svector_ostream OS(Tmp);
286    Inst.dump_pretty(OS);
287    OS << "\n";
288    report_fatal_error("unexpected instruction to relax: " + OS.str());
289  }
290
291  Res = Inst;
292  Res.setOpcode(RelaxedOp);
293}
294
295/// \brief Write a sequence of optimal nops to the output, covering \p Count
296/// bytes.
297/// \return - true on success, false on failure
298bool X86AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
299  static const uint8_t Nops[10][10] = {
300    // nop
301    {0x90},
302    // xchg %ax,%ax
303    {0x66, 0x90},
304    // nopl (%[re]ax)
305    {0x0f, 0x1f, 0x00},
306    // nopl 0(%[re]ax)
307    {0x0f, 0x1f, 0x40, 0x00},
308    // nopl 0(%[re]ax,%[re]ax,1)
309    {0x0f, 0x1f, 0x44, 0x00, 0x00},
310    // nopw 0(%[re]ax,%[re]ax,1)
311    {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
312    // nopl 0L(%[re]ax)
313    {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
314    // nopl 0L(%[re]ax,%[re]ax,1)
315    {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
316    // nopw 0L(%[re]ax,%[re]ax,1)
317    {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
318    // nopw %cs:0L(%[re]ax,%[re]ax,1)
319    {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
320  };
321
322  // This CPU doesn't support long nops. If needed add more.
323  // FIXME: Can we get this from the subtarget somehow?
324  // FIXME: We could generated something better than plain 0x90.
325  if (!HasNopl) {
326    for (uint64_t i = 0; i < Count; ++i)
327      OW->Write8(0x90);
328    return true;
329  }
330
331  // 15 is the longest single nop instruction.  Emit as many 15-byte nops as
332  // needed, then emit a nop of the remaining length.
333  do {
334    const uint8_t ThisNopLength = (uint8_t) std::min(Count, (uint64_t) 15);
335    const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10;
336    for (uint8_t i = 0; i < Prefixes; i++)
337      OW->Write8(0x66);
338    const uint8_t Rest = ThisNopLength - Prefixes;
339    for (uint8_t i = 0; i < Rest; i++)
340      OW->Write8(Nops[Rest - 1][i]);
341    Count -= ThisNopLength;
342  } while (Count != 0);
343
344  return true;
345}
346
347/* *** */
348
349namespace {
350
351class ELFX86AsmBackend : public X86AsmBackend {
352public:
353  uint8_t OSABI;
354  ELFX86AsmBackend(const Target &T, uint8_t _OSABI, StringRef CPU)
355      : X86AsmBackend(T, CPU), OSABI(_OSABI) {}
356};
357
358class ELFX86_32AsmBackend : public ELFX86AsmBackend {
359public:
360  ELFX86_32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
361    : ELFX86AsmBackend(T, OSABI, CPU) {}
362
363  MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
364    return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI, ELF::EM_386);
365  }
366};
367
368class ELFX86_64AsmBackend : public ELFX86AsmBackend {
369public:
370  ELFX86_64AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
371    : ELFX86AsmBackend(T, OSABI, CPU) {}
372
373  MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
374    return createX86ELFObjectWriter(OS, /*IsELF64*/ true, OSABI, ELF::EM_X86_64);
375  }
376};
377
378class WindowsX86AsmBackend : public X86AsmBackend {
379  bool Is64Bit;
380
381public:
382  WindowsX86AsmBackend(const Target &T, bool is64Bit, StringRef CPU)
383    : X86AsmBackend(T, CPU)
384    , Is64Bit(is64Bit) {
385  }
386
387  MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
388    return createX86WinCOFFObjectWriter(OS, Is64Bit);
389  }
390};
391
392namespace CU {
393
394  /// Compact unwind encoding values.
395  enum CompactUnwindEncodings {
396    /// [RE]BP based frame where [RE]BP is pused on the stack immediately after
397    /// the return address, then [RE]SP is moved to [RE]BP.
398    UNWIND_MODE_BP_FRAME                   = 0x01000000,
399
400    /// A frameless function with a small constant stack size.
401    UNWIND_MODE_STACK_IMMD                 = 0x02000000,
402
403    /// A frameless function with a large constant stack size.
404    UNWIND_MODE_STACK_IND                  = 0x03000000,
405
406    /// No compact unwind encoding is available.
407    UNWIND_MODE_DWARF                      = 0x04000000,
408
409    /// Mask for encoding the frame registers.
410    UNWIND_BP_FRAME_REGISTERS              = 0x00007FFF,
411
412    /// Mask for encoding the frameless registers.
413    UNWIND_FRAMELESS_STACK_REG_PERMUTATION = 0x000003FF
414  };
415
416} // end CU namespace
417
418class DarwinX86AsmBackend : public X86AsmBackend {
419  const MCRegisterInfo &MRI;
420
421  /// \brief Number of registers that can be saved in a compact unwind encoding.
422  enum { CU_NUM_SAVED_REGS = 6 };
423
424  mutable unsigned SavedRegs[CU_NUM_SAVED_REGS];
425  bool Is64Bit;
426
427  unsigned OffsetSize;                   ///< Offset of a "push" instruction.
428  unsigned PushInstrSize;                ///< Size of a "push" instruction.
429  unsigned MoveInstrSize;                ///< Size of a "move" instruction.
430  unsigned StackDivide;                  ///< Amount to adjust stack stize by.
431protected:
432  /// \brief Implementation of algorithm to generate the compact unwind encoding
433  /// for the CFI instructions.
434  uint32_t
435  generateCompactUnwindEncodingImpl(ArrayRef<MCCFIInstruction> Instrs) const {
436    if (Instrs.empty()) return 0;
437
438    // Reset the saved registers.
439    unsigned SavedRegIdx = 0;
440    memset(SavedRegs, 0, sizeof(SavedRegs));
441
442    bool HasFP = false;
443
444    // Encode that we are using EBP/RBP as the frame pointer.
445    uint32_t CompactUnwindEncoding = 0;
446
447    unsigned SubtractInstrIdx = Is64Bit ? 3 : 2;
448    unsigned InstrOffset = 0;
449    unsigned StackAdjust = 0;
450    unsigned StackSize = 0;
451    unsigned PrevStackSize = 0;
452    unsigned NumDefCFAOffsets = 0;
453
454    for (unsigned i = 0, e = Instrs.size(); i != e; ++i) {
455      const MCCFIInstruction &Inst = Instrs[i];
456
457      switch (Inst.getOperation()) {
458      default:
459        // Any other CFI directives indicate a frame that we aren't prepared
460        // to represent via compact unwind, so just bail out.
461        return 0;
462      case MCCFIInstruction::OpDefCfaRegister: {
463        // Defines a frame pointer. E.g.
464        //
465        //     movq %rsp, %rbp
466        //  L0:
467        //     .cfi_def_cfa_register %rbp
468        //
469        HasFP = true;
470        assert(MRI.getLLVMRegNum(Inst.getRegister(), true) ==
471               (Is64Bit ? X86::RBP : X86::EBP) && "Invalid frame pointer!");
472
473        // Reset the counts.
474        memset(SavedRegs, 0, sizeof(SavedRegs));
475        StackAdjust = 0;
476        SavedRegIdx = 0;
477        InstrOffset += MoveInstrSize;
478        break;
479      }
480      case MCCFIInstruction::OpDefCfaOffset: {
481        // Defines a new offset for the CFA. E.g.
482        //
483        //  With frame:
484        //
485        //     pushq %rbp
486        //  L0:
487        //     .cfi_def_cfa_offset 16
488        //
489        //  Without frame:
490        //
491        //     subq $72, %rsp
492        //  L0:
493        //     .cfi_def_cfa_offset 80
494        //
495        PrevStackSize = StackSize;
496        StackSize = std::abs(Inst.getOffset()) / StackDivide;
497        ++NumDefCFAOffsets;
498        break;
499      }
500      case MCCFIInstruction::OpOffset: {
501        // Defines a "push" of a callee-saved register. E.g.
502        //
503        //     pushq %r15
504        //     pushq %r14
505        //     pushq %rbx
506        //  L0:
507        //     subq $120, %rsp
508        //  L1:
509        //     .cfi_offset %rbx, -40
510        //     .cfi_offset %r14, -32
511        //     .cfi_offset %r15, -24
512        //
513        if (SavedRegIdx == CU_NUM_SAVED_REGS)
514          // If there are too many saved registers, we cannot use a compact
515          // unwind encoding.
516          return CU::UNWIND_MODE_DWARF;
517
518        unsigned Reg = MRI.getLLVMRegNum(Inst.getRegister(), true);
519        SavedRegs[SavedRegIdx++] = Reg;
520        StackAdjust += OffsetSize;
521        InstrOffset += PushInstrSize;
522        break;
523      }
524      }
525    }
526
527    StackAdjust /= StackDivide;
528
529    if (HasFP) {
530      if ((StackAdjust & 0xFF) != StackAdjust)
531        // Offset was too big for a compact unwind encoding.
532        return CU::UNWIND_MODE_DWARF;
533
534      // Get the encoding of the saved registers when we have a frame pointer.
535      uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame();
536      if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;
537
538      CompactUnwindEncoding |= CU::UNWIND_MODE_BP_FRAME;
539      CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16;
540      CompactUnwindEncoding |= RegEnc & CU::UNWIND_BP_FRAME_REGISTERS;
541    } else {
542      // If the amount of the stack allocation is the size of a register, then
543      // we "push" the RAX/EAX register onto the stack instead of adjusting the
544      // stack pointer with a SUB instruction. We don't support the push of the
545      // RAX/EAX register with compact unwind. So we check for that situation
546      // here.
547      if ((NumDefCFAOffsets == SavedRegIdx + 1 &&
548           StackSize - PrevStackSize == 1) ||
549          (Instrs.size() == 1 && NumDefCFAOffsets == 1 && StackSize == 2))
550        return CU::UNWIND_MODE_DWARF;
551
552      SubtractInstrIdx += InstrOffset;
553      ++StackAdjust;
554
555      if ((StackSize & 0xFF) == StackSize) {
556        // Frameless stack with a small stack size.
557        CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IMMD;
558
559        // Encode the stack size.
560        CompactUnwindEncoding |= (StackSize & 0xFF) << 16;
561      } else {
562        if ((StackAdjust & 0x7) != StackAdjust)
563          // The extra stack adjustments are too big for us to handle.
564          return CU::UNWIND_MODE_DWARF;
565
566        // Frameless stack with an offset too large for us to encode compactly.
567        CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IND;
568
569        // Encode the offset to the nnnnnn value in the 'subl $nnnnnn, ESP'
570        // instruction.
571        CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16;
572
573        // Encode any extra stack stack adjustments (done via push
574        // instructions).
575        CompactUnwindEncoding |= (StackAdjust & 0x7) << 13;
576      }
577
578      // Encode the number of registers saved. (Reverse the list first.)
579      std::reverse(&SavedRegs[0], &SavedRegs[SavedRegIdx]);
580      CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10;
581
582      // Get the encoding of the saved registers when we don't have a frame
583      // pointer.
584      uint32_t RegEnc = encodeCompactUnwindRegistersWithoutFrame(SavedRegIdx);
585      if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;
586
587      // Encode the register encoding.
588      CompactUnwindEncoding |=
589        RegEnc & CU::UNWIND_FRAMELESS_STACK_REG_PERMUTATION;
590    }
591
592    return CompactUnwindEncoding;
593  }
594
595private:
596  /// \brief Get the compact unwind number for a given register. The number
597  /// corresponds to the enum lists in compact_unwind_encoding.h.
598  int getCompactUnwindRegNum(unsigned Reg) const {
599    static const uint16_t CU32BitRegs[7] = {
600      X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
601    };
602    static const uint16_t CU64BitRegs[] = {
603      X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
604    };
605    const uint16_t *CURegs = Is64Bit ? CU64BitRegs : CU32BitRegs;
606    for (int Idx = 1; *CURegs; ++CURegs, ++Idx)
607      if (*CURegs == Reg)
608        return Idx;
609
610    return -1;
611  }
612
613  /// \brief Return the registers encoded for a compact encoding with a frame
614  /// pointer.
615  uint32_t encodeCompactUnwindRegistersWithFrame() const {
616    // Encode the registers in the order they were saved --- 3-bits per
617    // register. The list of saved registers is assumed to be in reverse
618    // order. The registers are numbered from 1 to CU_NUM_SAVED_REGS.
619    uint32_t RegEnc = 0;
620    for (int i = 0, Idx = 0; i != CU_NUM_SAVED_REGS; ++i) {
621      unsigned Reg = SavedRegs[i];
622      if (Reg == 0) break;
623
624      int CURegNum = getCompactUnwindRegNum(Reg);
625      if (CURegNum == -1) return ~0U;
626
627      // Encode the 3-bit register number in order, skipping over 3-bits for
628      // each register.
629      RegEnc |= (CURegNum & 0x7) << (Idx++ * 3);
630    }
631
632    assert((RegEnc & 0x3FFFF) == RegEnc &&
633           "Invalid compact register encoding!");
634    return RegEnc;
635  }
636
637  /// \brief Create the permutation encoding used with frameless stacks. It is
638  /// passed the number of registers to be saved and an array of the registers
639  /// saved.
640  uint32_t encodeCompactUnwindRegistersWithoutFrame(unsigned RegCount) const {
641    // The saved registers are numbered from 1 to 6. In order to encode the
642    // order in which they were saved, we re-number them according to their
643    // place in the register order. The re-numbering is relative to the last
644    // re-numbered register. E.g., if we have registers {6, 2, 4, 5} saved in
645    // that order:
646    //
647    //    Orig  Re-Num
648    //    ----  ------
649    //     6       6
650    //     2       2
651    //     4       3
652    //     5       3
653    //
654    for (unsigned i = 0; i != CU_NUM_SAVED_REGS; ++i) {
655      int CUReg = getCompactUnwindRegNum(SavedRegs[i]);
656      if (CUReg == -1) return ~0U;
657      SavedRegs[i] = CUReg;
658    }
659
660    // Reverse the list.
661    std::reverse(&SavedRegs[0], &SavedRegs[CU_NUM_SAVED_REGS]);
662
663    uint32_t RenumRegs[CU_NUM_SAVED_REGS];
664    for (unsigned i = CU_NUM_SAVED_REGS - RegCount; i < CU_NUM_SAVED_REGS; ++i){
665      unsigned Countless = 0;
666      for (unsigned j = CU_NUM_SAVED_REGS - RegCount; j < i; ++j)
667        if (SavedRegs[j] < SavedRegs[i])
668          ++Countless;
669
670      RenumRegs[i] = SavedRegs[i] - Countless - 1;
671    }
672
673    // Take the renumbered values and encode them into a 10-bit number.
674    uint32_t permutationEncoding = 0;
675    switch (RegCount) {
676    case 6:
677      permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1]
678                             + 6 * RenumRegs[2] +  2 * RenumRegs[3]
679                             +     RenumRegs[4];
680      break;
681    case 5:
682      permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2]
683                             + 6 * RenumRegs[3] +  2 * RenumRegs[4]
684                             +     RenumRegs[5];
685      break;
686    case 4:
687      permutationEncoding |=  60 * RenumRegs[2] + 12 * RenumRegs[3]
688                             + 3 * RenumRegs[4] +      RenumRegs[5];
689      break;
690    case 3:
691      permutationEncoding |=  20 * RenumRegs[3] +  4 * RenumRegs[4]
692                             +     RenumRegs[5];
693      break;
694    case 2:
695      permutationEncoding |=   5 * RenumRegs[4] +      RenumRegs[5];
696      break;
697    case 1:
698      permutationEncoding |=       RenumRegs[5];
699      break;
700    }
701
702    assert((permutationEncoding & 0x3FF) == permutationEncoding &&
703           "Invalid compact register encoding!");
704    return permutationEncoding;
705  }
706
707public:
708  DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef CPU,
709                      bool Is64Bit)
710    : X86AsmBackend(T, CPU), MRI(MRI), Is64Bit(Is64Bit) {
711    memset(SavedRegs, 0, sizeof(SavedRegs));
712    OffsetSize = Is64Bit ? 8 : 4;
713    MoveInstrSize = Is64Bit ? 3 : 2;
714    StackDivide = Is64Bit ? 8 : 4;
715    PushInstrSize = 1;
716  }
717};
718
719class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
720  bool SupportsCU;
721public:
722  DarwinX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,
723                         StringRef CPU, bool SupportsCU)
724    : DarwinX86AsmBackend(T, MRI, CPU, false), SupportsCU(SupportsCU) {}
725
726  MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
727    return createX86MachObjectWriter(OS, /*Is64Bit=*/false,
728                                     MachO::CPU_TYPE_I386,
729                                     MachO::CPU_SUBTYPE_I386_ALL);
730  }
731
732  /// \brief Generate the compact unwind encoding for the CFI instructions.
733  uint32_t generateCompactUnwindEncoding(
734                             ArrayRef<MCCFIInstruction> Instrs) const override {
735    return SupportsCU ? generateCompactUnwindEncodingImpl(Instrs) : 0;
736  }
737};
738
739class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
740  bool SupportsCU;
741  const MachO::CPUSubTypeX86 Subtype;
742public:
743  DarwinX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI,
744                         StringRef CPU, bool SupportsCU,
745                         MachO::CPUSubTypeX86 st)
746    : DarwinX86AsmBackend(T, MRI, CPU, true), SupportsCU(SupportsCU),
747      Subtype(st) {
748  }
749
750  MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
751    return createX86MachObjectWriter(OS, /*Is64Bit=*/true,
752                                     MachO::CPU_TYPE_X86_64, Subtype);
753  }
754
755  bool doesSectionRequireSymbols(const MCSection &Section) const override {
756    // Temporary labels in the string literals sections require symbols. The
757    // issue is that the x86_64 relocation format does not allow symbol +
758    // offset, and so the linker does not have enough information to resolve the
759    // access to the appropriate atom unless an external relocation is used. For
760    // non-cstring sections, we expect the compiler to use a non-temporary label
761    // for anything that could have an addend pointing outside the symbol.
762    //
763    // See <rdar://problem/4765733>.
764    const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
765    return SMO.getType() == MachO::S_CSTRING_LITERALS;
766  }
767
768  bool isSectionAtomizable(const MCSection &Section) const override {
769    const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
770    // Fixed sized data sections are uniqued, they cannot be diced into atoms.
771    switch (SMO.getType()) {
772    default:
773      return true;
774
775    case MachO::S_4BYTE_LITERALS:
776    case MachO::S_8BYTE_LITERALS:
777    case MachO::S_16BYTE_LITERALS:
778    case MachO::S_LITERAL_POINTERS:
779    case MachO::S_NON_LAZY_SYMBOL_POINTERS:
780    case MachO::S_LAZY_SYMBOL_POINTERS:
781    case MachO::S_MOD_INIT_FUNC_POINTERS:
782    case MachO::S_MOD_TERM_FUNC_POINTERS:
783    case MachO::S_INTERPOSING:
784      return false;
785    }
786  }
787
788  /// \brief Generate the compact unwind encoding for the CFI instructions.
789  uint32_t generateCompactUnwindEncoding(
790                             ArrayRef<MCCFIInstruction> Instrs) const override {
791    return SupportsCU ? generateCompactUnwindEncodingImpl(Instrs) : 0;
792  }
793};
794
795} // end anonymous namespace
796
797MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
798                                           const MCRegisterInfo &MRI,
799                                           StringRef TT,
800                                           StringRef CPU) {
801  Triple TheTriple(TT);
802
803  if (TheTriple.isOSBinFormatMachO())
804    return new DarwinX86_32AsmBackend(T, MRI, CPU,
805                                      TheTriple.isMacOSX() &&
806                                      !TheTriple.isMacOSXVersionLT(10, 7));
807
808  if (TheTriple.isOSWindows() && !TheTriple.isOSBinFormatELF())
809    return new WindowsX86AsmBackend(T, false, CPU);
810
811  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
812  return new ELFX86_32AsmBackend(T, OSABI, CPU);
813}
814
815MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
816                                           const MCRegisterInfo &MRI,
817                                           StringRef TT,
818                                           StringRef CPU) {
819  Triple TheTriple(TT);
820
821  if (TheTriple.isOSBinFormatMachO()) {
822    MachO::CPUSubTypeX86 CS =
823        StringSwitch<MachO::CPUSubTypeX86>(TheTriple.getArchName())
824            .Case("x86_64h", MachO::CPU_SUBTYPE_X86_64_H)
825            .Default(MachO::CPU_SUBTYPE_X86_64_ALL);
826    return new DarwinX86_64AsmBackend(T, MRI, CPU,
827                                      TheTriple.isMacOSX() &&
828                                      !TheTriple.isMacOSXVersionLT(10, 7), CS);
829  }
830
831  if (TheTriple.isOSWindows() && !TheTriple.isOSBinFormatELF())
832    return new WindowsX86AsmBackend(T, true, CPU);
833
834  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
835  return new ELFX86_64AsmBackend(T, OSABI, CPU);
836}
837