X86MCCodeEmitter.cpp revision 177cf1e1a3685209ab805f82897902a8d2b61661
1//===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the X86MCCodeEmitter class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "mccodeemitter" 15#include "MCTargetDesc/X86MCTargetDesc.h" 16#include "MCTargetDesc/X86BaseInfo.h" 17#include "MCTargetDesc/X86FixupKinds.h" 18#include "llvm/MC/MCCodeEmitter.h" 19#include "llvm/MC/MCExpr.h" 20#include "llvm/MC/MCInst.h" 21#include "llvm/MC/MCInstrInfo.h" 22#include "llvm/MC/MCRegisterInfo.h" 23#include "llvm/MC/MCSubtargetInfo.h" 24#include "llvm/MC/MCSymbol.h" 25#include "llvm/Support/raw_ostream.h" 26 27using namespace llvm; 28 29namespace { 30class X86MCCodeEmitter : public MCCodeEmitter { 31 X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT 32 void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT 33 const MCInstrInfo &MCII; 34 const MCSubtargetInfo &STI; 35 MCContext &Ctx; 36public: 37 X86MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti, 38 MCContext &ctx) 39 : MCII(mcii), STI(sti), Ctx(ctx) { 40 } 41 42 ~X86MCCodeEmitter() {} 43 44 bool is64BitMode() const { 45 // FIXME: Can tablegen auto-generate this? 46 return (STI.getFeatureBits() & X86::Mode64Bit) != 0; 47 } 48 49 bool is32BitMode() const { 50 // FIXME: Can tablegen auto-generate this? 51 return (STI.getFeatureBits() & X86::Mode64Bit) == 0; 52 } 53 54 static unsigned GetX86RegNum(const MCOperand &MO) { 55 return X86_MC::getX86RegNum(MO.getReg()); 56 } 57 58 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range 59 // 0-7 and the difference between the 2 groups is given by the REX prefix. 60 // In the VEX prefix, registers are seen sequencially from 0-15 and encoded 61 // in 1's complement form, example: 62 // 63 // ModRM field => XMM9 => 1 64 // VEX.VVVV => XMM9 => ~9 65 // 66 // See table 4-35 of Intel AVX Programming Reference for details. 67 static unsigned char getVEXRegisterEncoding(const MCInst &MI, 68 unsigned OpNum) { 69 unsigned SrcReg = MI.getOperand(OpNum).getReg(); 70 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum)); 71 if (X86II::isX86_64ExtendedReg(SrcReg)) 72 SrcRegNum |= 8; 73 74 // The registers represented through VEX_VVVV should 75 // be encoded in 1's complement form. 76 return (~SrcRegNum) & 0xf; 77 } 78 79 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const { 80 OS << (char)C; 81 ++CurByte; 82 } 83 84 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte, 85 raw_ostream &OS) const { 86 // Output the constant in little endian byte order. 87 for (unsigned i = 0; i != Size; ++i) { 88 EmitByte(Val & 255, CurByte, OS); 89 Val >>= 8; 90 } 91 } 92 93 void EmitImmediate(const MCOperand &Disp, SMLoc Loc, 94 unsigned ImmSize, MCFixupKind FixupKind, 95 unsigned &CurByte, raw_ostream &OS, 96 SmallVectorImpl<MCFixup> &Fixups, 97 int ImmOffset = 0) const; 98 99 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode, 100 unsigned RM) { 101 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!"); 102 return RM | (RegOpcode << 3) | (Mod << 6); 103 } 104 105 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld, 106 unsigned &CurByte, raw_ostream &OS) const { 107 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS); 108 } 109 110 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base, 111 unsigned &CurByte, raw_ostream &OS) const { 112 // SIB byte is in the same format as the ModRMByte. 113 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS); 114 } 115 116 117 void EmitMemModRMByte(const MCInst &MI, unsigned Op, 118 unsigned RegOpcodeField, 119 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS, 120 SmallVectorImpl<MCFixup> &Fixups) const; 121 122 void EncodeInstruction(const MCInst &MI, raw_ostream &OS, 123 SmallVectorImpl<MCFixup> &Fixups) const; 124 125 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, 126 const MCInst &MI, const MCInstrDesc &Desc, 127 raw_ostream &OS) const; 128 129 void EmitSegmentOverridePrefix(uint64_t TSFlags, unsigned &CurByte, 130 int MemOperand, const MCInst &MI, 131 raw_ostream &OS) const; 132 133 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, 134 const MCInst &MI, const MCInstrDesc &Desc, 135 raw_ostream &OS) const; 136}; 137 138} // end anonymous namespace 139 140 141MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII, 142 const MCRegisterInfo &MRI, 143 const MCSubtargetInfo &STI, 144 MCContext &Ctx) { 145 return new X86MCCodeEmitter(MCII, STI, Ctx); 146} 147 148/// isDisp8 - Return true if this signed displacement fits in a 8-bit 149/// sign-extended field. 150static bool isDisp8(int Value) { 151 return Value == (signed char)Value; 152} 153 154/// getImmFixupKind - Return the appropriate fixup kind to use for an immediate 155/// in an instruction with the specified TSFlags. 156static MCFixupKind getImmFixupKind(uint64_t TSFlags) { 157 unsigned Size = X86II::getSizeOfImm(TSFlags); 158 bool isPCRel = X86II::isImmPCRel(TSFlags); 159 160 return MCFixup::getKindForSize(Size, isPCRel); 161} 162 163/// Is32BitMemOperand - Return true if the specified instruction has 164/// a 32-bit memory operand. Op specifies the operand # of the memoperand. 165static bool Is32BitMemOperand(const MCInst &MI, unsigned Op) { 166 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 167 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 168 169 if ((BaseReg.getReg() != 0 && 170 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || 171 (IndexReg.getReg() != 0 && 172 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg()))) 173 return true; 174 return false; 175} 176 177/// Is64BitMemOperand - Return true if the specified instruction has 178/// a 64-bit memory operand. Op specifies the operand # of the memoperand. 179#ifndef NDEBUG 180static bool Is64BitMemOperand(const MCInst &MI, unsigned Op) { 181 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 182 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 183 184 if ((BaseReg.getReg() != 0 && 185 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) || 186 (IndexReg.getReg() != 0 && 187 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg()))) 188 return true; 189 return false; 190} 191#endif 192 193/// Is16BitMemOperand - Return true if the specified instruction has 194/// a 16-bit memory operand. Op specifies the operand # of the memoperand. 195static bool Is16BitMemOperand(const MCInst &MI, unsigned Op) { 196 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 197 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 198 199 if ((BaseReg.getReg() != 0 && 200 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) || 201 (IndexReg.getReg() != 0 && 202 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg()))) 203 return true; 204 return false; 205} 206 207/// StartsWithGlobalOffsetTable - Check if this expression starts with 208/// _GLOBAL_OFFSET_TABLE_ and if it is of the form 209/// _GLOBAL_OFFSET_TABLE_-symbol. This is needed to support PIC on ELF 210/// i386 as _GLOBAL_OFFSET_TABLE_ is magical. We check only simple case that 211/// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start 212/// of a binary expression. 213enum GlobalOffsetTableExprKind { 214 GOT_None, 215 GOT_Normal, 216 GOT_SymDiff 217}; 218static GlobalOffsetTableExprKind 219StartsWithGlobalOffsetTable(const MCExpr *Expr) { 220 const MCExpr *RHS = 0; 221 if (Expr->getKind() == MCExpr::Binary) { 222 const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr); 223 Expr = BE->getLHS(); 224 RHS = BE->getRHS(); 225 } 226 227 if (Expr->getKind() != MCExpr::SymbolRef) 228 return GOT_None; 229 230 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr); 231 const MCSymbol &S = Ref->getSymbol(); 232 if (S.getName() != "_GLOBAL_OFFSET_TABLE_") 233 return GOT_None; 234 if (RHS && RHS->getKind() == MCExpr::SymbolRef) 235 return GOT_SymDiff; 236 return GOT_Normal; 237} 238 239void X86MCCodeEmitter:: 240EmitImmediate(const MCOperand &DispOp, SMLoc Loc, unsigned Size, 241 MCFixupKind FixupKind, unsigned &CurByte, raw_ostream &OS, 242 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const { 243 const MCExpr *Expr = NULL; 244 if (DispOp.isImm()) { 245 // If this is a simple integer displacement that doesn't require a 246 // relocation, emit it now. 247 if (FixupKind != FK_PCRel_1 && 248 FixupKind != FK_PCRel_2 && 249 FixupKind != FK_PCRel_4) { 250 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS); 251 return; 252 } 253 Expr = MCConstantExpr::Create(DispOp.getImm(), Ctx); 254 } else { 255 Expr = DispOp.getExpr(); 256 } 257 258 // If we have an immoffset, add it to the expression. 259 if ((FixupKind == FK_Data_4 || 260 FixupKind == FK_Data_8 || 261 FixupKind == MCFixupKind(X86::reloc_signed_4byte))) { 262 GlobalOffsetTableExprKind Kind = StartsWithGlobalOffsetTable(Expr); 263 if (Kind != GOT_None) { 264 assert(ImmOffset == 0); 265 266 FixupKind = MCFixupKind(X86::reloc_global_offset_table); 267 if (Kind == GOT_Normal) 268 ImmOffset = CurByte; 269 } else if (Expr->getKind() == MCExpr::SymbolRef) { 270 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr); 271 if (Ref->getKind() == MCSymbolRefExpr::VK_SECREL) { 272 FixupKind = MCFixupKind(FK_SecRel_4); 273 } 274 } 275 } 276 277 // If the fixup is pc-relative, we need to bias the value to be relative to 278 // the start of the field, not the end of the field. 279 if (FixupKind == FK_PCRel_4 || 280 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) || 281 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load)) 282 ImmOffset -= 4; 283 if (FixupKind == FK_PCRel_2) 284 ImmOffset -= 2; 285 if (FixupKind == FK_PCRel_1) 286 ImmOffset -= 1; 287 288 if (ImmOffset) 289 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(ImmOffset, Ctx), 290 Ctx); 291 292 // Emit a symbolic constant as a fixup and 4 zeros. 293 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind, Loc)); 294 EmitConstant(0, Size, CurByte, OS); 295} 296 297void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op, 298 unsigned RegOpcodeField, 299 uint64_t TSFlags, unsigned &CurByte, 300 raw_ostream &OS, 301 SmallVectorImpl<MCFixup> &Fixups) const{ 302 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp); 303 const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg); 304 const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt); 305 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 306 unsigned BaseReg = Base.getReg(); 307 308 // Handle %rip relative addressing. 309 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode 310 assert(is64BitMode() && "Rip-relative addressing requires 64-bit mode"); 311 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address"); 312 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS); 313 314 unsigned FixupKind = X86::reloc_riprel_4byte; 315 316 // movq loads are handled with a special relocation form which allows the 317 // linker to eliminate some loads for GOT references which end up in the 318 // same linkage unit. 319 if (MI.getOpcode() == X86::MOV64rm) 320 FixupKind = X86::reloc_riprel_4byte_movq_load; 321 322 // rip-relative addressing is actually relative to the *next* instruction. 323 // Since an immediate can follow the mod/rm byte for an instruction, this 324 // means that we need to bias the immediate field of the instruction with 325 // the size of the immediate field. If we have this case, add it into the 326 // expression to emit. 327 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0; 328 329 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), 330 CurByte, OS, Fixups, -ImmSize); 331 return; 332 } 333 334 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U; 335 336 // Determine whether a SIB byte is needed. 337 // If no BaseReg, issue a RIP relative instruction only if the MCE can 338 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table 339 // 2-7) and absolute references. 340 341 if (// The SIB byte must be used if there is an index register. 342 IndexReg.getReg() == 0 && 343 // The SIB byte must be used if the base is ESP/RSP/R12, all of which 344 // encode to an R/M value of 4, which indicates that a SIB byte is 345 // present. 346 BaseRegNo != N86::ESP && 347 // If there is no base register and we're in 64-bit mode, we need a SIB 348 // byte to emit an addr that is just 'disp32' (the non-RIP relative form). 349 (!is64BitMode() || BaseReg != 0)) { 350 351 if (BaseReg == 0) { // [disp32] in X86-32 mode 352 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS); 353 EmitImmediate(Disp, MI.getLoc(), 4, FK_Data_4, CurByte, OS, Fixups); 354 return; 355 } 356 357 // If the base is not EBP/ESP and there is no displacement, use simple 358 // indirect register encoding, this handles addresses like [EAX]. The 359 // encoding for [EBP] with no displacement means [disp32] so we handle it 360 // by emitting a displacement of 0 below. 361 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) { 362 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS); 363 return; 364 } 365 366 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8]. 367 if (Disp.isImm() && isDisp8(Disp.getImm())) { 368 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS); 369 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups); 370 return; 371 } 372 373 // Otherwise, emit the most general non-SIB encoding: [REG+disp32] 374 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS); 375 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS, 376 Fixups); 377 return; 378 } 379 380 // We need a SIB byte, so start by outputting the ModR/M byte first 381 assert(IndexReg.getReg() != X86::ESP && 382 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!"); 383 384 bool ForceDisp32 = false; 385 bool ForceDisp8 = false; 386 if (BaseReg == 0) { 387 // If there is no base register, we emit the special case SIB byte with 388 // MOD=0, BASE=5, to JUST get the index, scale, and displacement. 389 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS); 390 ForceDisp32 = true; 391 } else if (!Disp.isImm()) { 392 // Emit the normal disp32 encoding. 393 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS); 394 ForceDisp32 = true; 395 } else if (Disp.getImm() == 0 && 396 // Base reg can't be anything that ends up with '5' as the base 397 // reg, it is the magic [*] nomenclature that indicates no base. 398 BaseRegNo != N86::EBP) { 399 // Emit no displacement ModR/M byte 400 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS); 401 } else if (isDisp8(Disp.getImm())) { 402 // Emit the disp8 encoding. 403 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS); 404 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP 405 } else { 406 // Emit the normal disp32 encoding. 407 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS); 408 } 409 410 // Calculate what the SS field value should be... 411 static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 }; 412 unsigned SS = SSTable[Scale.getImm()]; 413 414 if (BaseReg == 0) { 415 // Handle the SIB byte for the case where there is no base, see Intel 416 // Manual 2A, table 2-7. The displacement has already been output. 417 unsigned IndexRegNo; 418 if (IndexReg.getReg()) 419 IndexRegNo = GetX86RegNum(IndexReg); 420 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5) 421 IndexRegNo = 4; 422 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS); 423 } else { 424 unsigned IndexRegNo; 425 if (IndexReg.getReg()) 426 IndexRegNo = GetX86RegNum(IndexReg); 427 else 428 IndexRegNo = 4; // For example [ESP+1*<noreg>+4] 429 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS); 430 } 431 432 // Do we need to output a displacement? 433 if (ForceDisp8) 434 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups); 435 else if (ForceDisp32 || Disp.getImm() != 0) 436 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte), 437 CurByte, OS, Fixups); 438} 439 440/// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix 441/// called VEX. 442void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, 443 int MemOperand, const MCInst &MI, 444 const MCInstrDesc &Desc, 445 raw_ostream &OS) const { 446 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V; 447 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3; 448 449 // VEX_R: opcode externsion equivalent to REX.R in 450 // 1's complement (inverted) form 451 // 452 // 1: Same as REX_R=0 (must be 1 in 32-bit mode) 453 // 0: Same as REX_R=1 (64 bit mode only) 454 // 455 unsigned char VEX_R = 0x1; 456 457 // VEX_X: equivalent to REX.X, only used when a 458 // register is used for index in SIB Byte. 459 // 460 // 1: Same as REX.X=0 (must be 1 in 32-bit mode) 461 // 0: Same as REX.X=1 (64-bit mode only) 462 unsigned char VEX_X = 0x1; 463 464 // VEX_B: 465 // 466 // 1: Same as REX_B=0 (ignored in 32-bit mode) 467 // 0: Same as REX_B=1 (64 bit mode only) 468 // 469 unsigned char VEX_B = 0x1; 470 471 // VEX_W: opcode specific (use like REX.W, or used for 472 // opcode extension, or ignored, depending on the opcode byte) 473 unsigned char VEX_W = 0; 474 475 // XOP: Use XOP prefix byte 0x8f instead of VEX. 476 unsigned char XOP = 0; 477 478 // VEX_5M (VEX m-mmmmm field): 479 // 480 // 0b00000: Reserved for future use 481 // 0b00001: implied 0F leading opcode 482 // 0b00010: implied 0F 38 leading opcode bytes 483 // 0b00011: implied 0F 3A leading opcode bytes 484 // 0b00100-0b11111: Reserved for future use 485 // 0b01000: XOP map select - 08h instructions with imm byte 486 // 0b10001: XOP map select - 09h instructions with no imm byte 487 unsigned char VEX_5M = 0x1; 488 489 // VEX_4V (VEX vvvv field): a register specifier 490 // (in 1's complement form) or 1111 if unused. 491 unsigned char VEX_4V = 0xf; 492 493 // VEX_L (Vector Length): 494 // 495 // 0: scalar or 128-bit vector 496 // 1: 256-bit vector 497 // 498 unsigned char VEX_L = 0; 499 500 // VEX_PP: opcode extension providing equivalent 501 // functionality of a SIMD prefix 502 // 503 // 0b00: None 504 // 0b01: 66 505 // 0b10: F3 506 // 0b11: F2 507 // 508 unsigned char VEX_PP = 0; 509 510 // Encode the operand size opcode prefix as needed. 511 if (TSFlags & X86II::OpSize) 512 VEX_PP = 0x01; 513 514 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W) 515 VEX_W = 1; 516 517 if ((TSFlags >> X86II::VEXShift) & X86II::XOP) 518 XOP = 1; 519 520 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_L) 521 VEX_L = 1; 522 523 switch (TSFlags & X86II::Op0Mask) { 524 default: llvm_unreachable("Invalid prefix!"); 525 case X86II::T8: // 0F 38 526 VEX_5M = 0x2; 527 break; 528 case X86II::TA: // 0F 3A 529 VEX_5M = 0x3; 530 break; 531 case X86II::T8XS: // F3 0F 38 532 VEX_PP = 0x2; 533 VEX_5M = 0x2; 534 break; 535 case X86II::T8XD: // F2 0F 38 536 VEX_PP = 0x3; 537 VEX_5M = 0x2; 538 break; 539 case X86II::TAXD: // F2 0F 3A 540 VEX_PP = 0x3; 541 VEX_5M = 0x3; 542 break; 543 case X86II::XS: // F3 0F 544 VEX_PP = 0x2; 545 break; 546 case X86II::XD: // F2 0F 547 VEX_PP = 0x3; 548 break; 549 case X86II::XOP8: 550 VEX_5M = 0x8; 551 break; 552 case X86II::XOP9: 553 VEX_5M = 0x9; 554 break; 555 case X86II::A6: // Bypass: Not used by VEX 556 case X86II::A7: // Bypass: Not used by VEX 557 case X86II::TB: // Bypass: Not used by VEX 558 case 0: 559 break; // No prefix! 560 } 561 562 563 // Set the vector length to 256-bit if YMM0-YMM15 is used 564 for (unsigned i = 0; i != MI.getNumOperands(); ++i) { 565 if (!MI.getOperand(i).isReg()) 566 continue; 567 unsigned SrcReg = MI.getOperand(i).getReg(); 568 if (SrcReg >= X86::YMM0 && SrcReg <= X86::YMM15) 569 VEX_L = 1; 570 } 571 572 // Classify VEX_B, VEX_4V, VEX_R, VEX_X 573 unsigned NumOps = Desc.getNumOperands(); 574 unsigned CurOp = 0; 575 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1) 576 ++CurOp; 577 578 switch (TSFlags & X86II::FormMask) { 579 case X86II::MRMInitReg: llvm_unreachable("FIXME: Remove this!"); 580 case X86II::MRMDestMem: { 581 // MRMDestMem instructions forms: 582 // MemAddr, src1(ModR/M) 583 // MemAddr, src1(VEX_4V), src2(ModR/M) 584 // MemAddr, src1(ModR/M), imm8 585 // 586 if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrBaseReg).getReg())) 587 VEX_B = 0x0; 588 if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrIndexReg).getReg())) 589 VEX_X = 0x0; 590 591 CurOp = X86::AddrNumOperands; 592 if (HasVEX_4V) 593 VEX_4V = getVEXRegisterEncoding(MI, CurOp++); 594 595 const MCOperand &MO = MI.getOperand(CurOp); 596 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg())) 597 VEX_R = 0x0; 598 break; 599 } 600 case X86II::MRMSrcMem: 601 // MRMSrcMem instructions forms: 602 // src1(ModR/M), MemAddr 603 // src1(ModR/M), src2(VEX_4V), MemAddr 604 // src1(ModR/M), MemAddr, imm8 605 // src1(ModR/M), MemAddr, src2(VEX_I8IMM) 606 // 607 // FMA4: 608 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM) 609 // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M), 610 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp++).getReg())) 611 VEX_R = 0x0; 612 613 if (HasVEX_4V) 614 VEX_4V = getVEXRegisterEncoding(MI, CurOp); 615 616 if (X86II::isX86_64ExtendedReg( 617 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg())) 618 VEX_B = 0x0; 619 if (X86II::isX86_64ExtendedReg( 620 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg())) 621 VEX_X = 0x0; 622 623 if (HasVEX_4VOp3) 624 VEX_4V = getVEXRegisterEncoding(MI, X86::AddrNumOperands+1); 625 break; 626 case X86II::MRM0m: case X86II::MRM1m: 627 case X86II::MRM2m: case X86II::MRM3m: 628 case X86II::MRM4m: case X86II::MRM5m: 629 case X86II::MRM6m: case X86II::MRM7m: { 630 // MRM[0-9]m instructions forms: 631 // MemAddr 632 // src1(VEX_4V), MemAddr 633 if (HasVEX_4V) 634 VEX_4V = getVEXRegisterEncoding(MI, 0); 635 636 if (X86II::isX86_64ExtendedReg( 637 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg())) 638 VEX_B = 0x0; 639 if (X86II::isX86_64ExtendedReg( 640 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg())) 641 VEX_X = 0x0; 642 break; 643 } 644 case X86II::MRMSrcReg: 645 // MRMSrcReg instructions forms: 646 // dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM) 647 // dst(ModR/M), src1(ModR/M) 648 // dst(ModR/M), src1(ModR/M), imm8 649 // 650 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 651 VEX_R = 0x0; 652 CurOp++; 653 654 if (HasVEX_4V) 655 VEX_4V = getVEXRegisterEncoding(MI, CurOp++); 656 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 657 VEX_B = 0x0; 658 CurOp++; 659 if (HasVEX_4VOp3) 660 VEX_4V = getVEXRegisterEncoding(MI, CurOp); 661 break; 662 case X86II::MRMDestReg: 663 // MRMDestReg instructions forms: 664 // dst(ModR/M), src(ModR/M) 665 // dst(ModR/M), src(ModR/M), imm8 666 if (X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) 667 VEX_B = 0x0; 668 if (X86II::isX86_64ExtendedReg(MI.getOperand(1).getReg())) 669 VEX_R = 0x0; 670 break; 671 case X86II::MRM0r: case X86II::MRM1r: 672 case X86II::MRM2r: case X86II::MRM3r: 673 case X86II::MRM4r: case X86II::MRM5r: 674 case X86II::MRM6r: case X86II::MRM7r: 675 // MRM0r-MRM7r instructions forms: 676 // dst(VEX_4V), src(ModR/M), imm8 677 VEX_4V = getVEXRegisterEncoding(MI, 0); 678 if (X86II::isX86_64ExtendedReg(MI.getOperand(1).getReg())) 679 VEX_B = 0x0; 680 break; 681 default: // RawFrm 682 break; 683 } 684 685 // Emit segment override opcode prefix as needed. 686 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS); 687 688 // VEX opcode prefix can have 2 or 3 bytes 689 // 690 // 3 bytes: 691 // +-----+ +--------------+ +-------------------+ 692 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp | 693 // +-----+ +--------------+ +-------------------+ 694 // 2 bytes: 695 // +-----+ +-------------------+ 696 // | C5h | | R | vvvv | L | pp | 697 // +-----+ +-------------------+ 698 // 699 unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3); 700 701 if (VEX_B && VEX_X && !VEX_W && !XOP && (VEX_5M == 1)) { // 2 byte VEX prefix 702 EmitByte(0xC5, CurByte, OS); 703 EmitByte(LastByte | (VEX_R << 7), CurByte, OS); 704 return; 705 } 706 707 // 3 byte VEX prefix 708 EmitByte(XOP ? 0x8F : 0xC4, CurByte, OS); 709 EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS); 710 EmitByte(LastByte | (VEX_W << 7), CurByte, OS); 711} 712 713/// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64 714/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand 715/// size, and 3) use of X86-64 extended registers. 716static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags, 717 const MCInstrDesc &Desc) { 718 unsigned REX = 0; 719 if (TSFlags & X86II::REX_W) 720 REX |= 1 << 3; // set REX.W 721 722 if (MI.getNumOperands() == 0) return REX; 723 724 unsigned NumOps = MI.getNumOperands(); 725 // FIXME: MCInst should explicitize the two-addrness. 726 bool isTwoAddr = NumOps > 1 && 727 Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1; 728 729 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix. 730 unsigned i = isTwoAddr ? 1 : 0; 731 for (; i != NumOps; ++i) { 732 const MCOperand &MO = MI.getOperand(i); 733 if (!MO.isReg()) continue; 734 unsigned Reg = MO.getReg(); 735 if (!X86II::isX86_64NonExtLowByteReg(Reg)) continue; 736 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything 737 // that returns non-zero. 738 REX |= 0x40; // REX fixed encoding prefix 739 break; 740 } 741 742 switch (TSFlags & X86II::FormMask) { 743 case X86II::MRMInitReg: llvm_unreachable("FIXME: Remove this!"); 744 case X86II::MRMSrcReg: 745 if (MI.getOperand(0).isReg() && 746 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) 747 REX |= 1 << 2; // set REX.R 748 i = isTwoAddr ? 2 : 1; 749 for (; i != NumOps; ++i) { 750 const MCOperand &MO = MI.getOperand(i); 751 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg())) 752 REX |= 1 << 0; // set REX.B 753 } 754 break; 755 case X86II::MRMSrcMem: { 756 if (MI.getOperand(0).isReg() && 757 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) 758 REX |= 1 << 2; // set REX.R 759 unsigned Bit = 0; 760 i = isTwoAddr ? 2 : 1; 761 for (; i != NumOps; ++i) { 762 const MCOperand &MO = MI.getOperand(i); 763 if (MO.isReg()) { 764 if (X86II::isX86_64ExtendedReg(MO.getReg())) 765 REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1) 766 Bit++; 767 } 768 } 769 break; 770 } 771 case X86II::MRM0m: case X86II::MRM1m: 772 case X86II::MRM2m: case X86II::MRM3m: 773 case X86II::MRM4m: case X86II::MRM5m: 774 case X86II::MRM6m: case X86II::MRM7m: 775 case X86II::MRMDestMem: { 776 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands); 777 i = isTwoAddr ? 1 : 0; 778 if (NumOps > e && MI.getOperand(e).isReg() && 779 X86II::isX86_64ExtendedReg(MI.getOperand(e).getReg())) 780 REX |= 1 << 2; // set REX.R 781 unsigned Bit = 0; 782 for (; i != e; ++i) { 783 const MCOperand &MO = MI.getOperand(i); 784 if (MO.isReg()) { 785 if (X86II::isX86_64ExtendedReg(MO.getReg())) 786 REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1) 787 Bit++; 788 } 789 } 790 break; 791 } 792 default: 793 if (MI.getOperand(0).isReg() && 794 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) 795 REX |= 1 << 0; // set REX.B 796 i = isTwoAddr ? 2 : 1; 797 for (unsigned e = NumOps; i != e; ++i) { 798 const MCOperand &MO = MI.getOperand(i); 799 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg())) 800 REX |= 1 << 2; // set REX.R 801 } 802 break; 803 } 804 return REX; 805} 806 807/// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed 808void X86MCCodeEmitter::EmitSegmentOverridePrefix(uint64_t TSFlags, 809 unsigned &CurByte, int MemOperand, 810 const MCInst &MI, 811 raw_ostream &OS) const { 812 switch (TSFlags & X86II::SegOvrMask) { 813 default: llvm_unreachable("Invalid segment!"); 814 case 0: 815 // No segment override, check for explicit one on memory operand. 816 if (MemOperand != -1) { // If the instruction has a memory operand. 817 switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) { 818 default: llvm_unreachable("Unknown segment register!"); 819 case 0: break; 820 case X86::CS: EmitByte(0x2E, CurByte, OS); break; 821 case X86::SS: EmitByte(0x36, CurByte, OS); break; 822 case X86::DS: EmitByte(0x3E, CurByte, OS); break; 823 case X86::ES: EmitByte(0x26, CurByte, OS); break; 824 case X86::FS: EmitByte(0x64, CurByte, OS); break; 825 case X86::GS: EmitByte(0x65, CurByte, OS); break; 826 } 827 } 828 break; 829 case X86II::FS: 830 EmitByte(0x64, CurByte, OS); 831 break; 832 case X86II::GS: 833 EmitByte(0x65, CurByte, OS); 834 break; 835 } 836} 837 838/// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode. 839/// 840/// MemOperand is the operand # of the start of a memory operand if present. If 841/// Not present, it is -1. 842void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, 843 int MemOperand, const MCInst &MI, 844 const MCInstrDesc &Desc, 845 raw_ostream &OS) const { 846 847 // Emit the lock opcode prefix as needed. 848 if (TSFlags & X86II::LOCK) 849 EmitByte(0xF0, CurByte, OS); 850 851 // Emit segment override opcode prefix as needed. 852 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS); 853 854 // Emit the repeat opcode prefix as needed. 855 if ((TSFlags & X86II::Op0Mask) == X86II::REP) 856 EmitByte(0xF3, CurByte, OS); 857 858 // Emit the address size opcode prefix as needed. 859 bool need_address_override; 860 if (TSFlags & X86II::AdSize) { 861 need_address_override = true; 862 } else if (MemOperand == -1) { 863 need_address_override = false; 864 } else if (is64BitMode()) { 865 assert(!Is16BitMemOperand(MI, MemOperand)); 866 need_address_override = Is32BitMemOperand(MI, MemOperand); 867 } else if (is32BitMode()) { 868 assert(!Is64BitMemOperand(MI, MemOperand)); 869 need_address_override = Is16BitMemOperand(MI, MemOperand); 870 } else { 871 need_address_override = false; 872 } 873 874 if (need_address_override) 875 EmitByte(0x67, CurByte, OS); 876 877 // Emit the operand size opcode prefix as needed. 878 if (TSFlags & X86II::OpSize) 879 EmitByte(0x66, CurByte, OS); 880 881 bool Need0FPrefix = false; 882 switch (TSFlags & X86II::Op0Mask) { 883 default: llvm_unreachable("Invalid prefix!"); 884 case 0: break; // No prefix! 885 case X86II::REP: break; // already handled. 886 case X86II::TB: // Two-byte opcode prefix 887 case X86II::T8: // 0F 38 888 case X86II::TA: // 0F 3A 889 case X86II::A6: // 0F A6 890 case X86II::A7: // 0F A7 891 Need0FPrefix = true; 892 break; 893 case X86II::T8XS: // F3 0F 38 894 EmitByte(0xF3, CurByte, OS); 895 Need0FPrefix = true; 896 break; 897 case X86II::T8XD: // F2 0F 38 898 EmitByte(0xF2, CurByte, OS); 899 Need0FPrefix = true; 900 break; 901 case X86II::TAXD: // F2 0F 3A 902 EmitByte(0xF2, CurByte, OS); 903 Need0FPrefix = true; 904 break; 905 case X86II::XS: // F3 0F 906 EmitByte(0xF3, CurByte, OS); 907 Need0FPrefix = true; 908 break; 909 case X86II::XD: // F2 0F 910 EmitByte(0xF2, CurByte, OS); 911 Need0FPrefix = true; 912 break; 913 case X86II::D8: EmitByte(0xD8, CurByte, OS); break; 914 case X86II::D9: EmitByte(0xD9, CurByte, OS); break; 915 case X86II::DA: EmitByte(0xDA, CurByte, OS); break; 916 case X86II::DB: EmitByte(0xDB, CurByte, OS); break; 917 case X86II::DC: EmitByte(0xDC, CurByte, OS); break; 918 case X86II::DD: EmitByte(0xDD, CurByte, OS); break; 919 case X86II::DE: EmitByte(0xDE, CurByte, OS); break; 920 case X86II::DF: EmitByte(0xDF, CurByte, OS); break; 921 } 922 923 // Handle REX prefix. 924 // FIXME: Can this come before F2 etc to simplify emission? 925 if (is64BitMode()) { 926 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc)) 927 EmitByte(0x40 | REX, CurByte, OS); 928 } 929 930 // 0x0F escape code must be emitted just before the opcode. 931 if (Need0FPrefix) 932 EmitByte(0x0F, CurByte, OS); 933 934 // FIXME: Pull this up into previous switch if REX can be moved earlier. 935 switch (TSFlags & X86II::Op0Mask) { 936 case X86II::T8XS: // F3 0F 38 937 case X86II::T8XD: // F2 0F 38 938 case X86II::T8: // 0F 38 939 EmitByte(0x38, CurByte, OS); 940 break; 941 case X86II::TAXD: // F2 0F 3A 942 case X86II::TA: // 0F 3A 943 EmitByte(0x3A, CurByte, OS); 944 break; 945 case X86II::A6: // 0F A6 946 EmitByte(0xA6, CurByte, OS); 947 break; 948 case X86II::A7: // 0F A7 949 EmitByte(0xA7, CurByte, OS); 950 break; 951 } 952} 953 954void X86MCCodeEmitter:: 955EncodeInstruction(const MCInst &MI, raw_ostream &OS, 956 SmallVectorImpl<MCFixup> &Fixups) const { 957 unsigned Opcode = MI.getOpcode(); 958 const MCInstrDesc &Desc = MCII.get(Opcode); 959 uint64_t TSFlags = Desc.TSFlags; 960 961 // Pseudo instructions don't get encoded. 962 if ((TSFlags & X86II::FormMask) == X86II::Pseudo) 963 return; 964 965 // If this is a two-address instruction, skip one of the register operands. 966 // FIXME: This should be handled during MCInst lowering. 967 unsigned NumOps = Desc.getNumOperands(); 968 unsigned CurOp = 0; 969 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1) 970 ++CurOp; 971 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, MCOI::TIED_TO)== 0) 972 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32 973 --NumOps; 974 975 // Keep track of the current byte being emitted. 976 unsigned CurByte = 0; 977 978 // Is this instruction encoded using the AVX VEX prefix? 979 bool HasVEXPrefix = (TSFlags >> X86II::VEXShift) & X86II::VEX; 980 981 // It uses the VEX.VVVV field? 982 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V; 983 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3; 984 bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4; 985 const unsigned MemOp4_I8IMMOperand = 2; 986 987 // Determine where the memory operand starts, if present. 988 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags, Opcode); 989 if (MemoryOperand != -1) MemoryOperand += CurOp; 990 991 if (!HasVEXPrefix) 992 EmitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS); 993 else 994 EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS); 995 996 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); 997 998 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode) 999 BaseOpcode = 0x0F; // Weird 3DNow! encoding. 1000 1001 unsigned SrcRegNum = 0; 1002 switch (TSFlags & X86II::FormMask) { 1003 case X86II::MRMInitReg: 1004 llvm_unreachable("FIXME: Remove this form when the JIT moves to MCCodeEmitter!"); 1005 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n"; 1006 llvm_unreachable("Unknown FormMask value in X86MCCodeEmitter!"); 1007 case X86II::Pseudo: 1008 llvm_unreachable("Pseudo instruction shouldn't be emitted"); 1009 case X86II::RawFrm: 1010 EmitByte(BaseOpcode, CurByte, OS); 1011 break; 1012 case X86II::RawFrmImm8: 1013 EmitByte(BaseOpcode, CurByte, OS); 1014 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1015 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), 1016 CurByte, OS, Fixups); 1017 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1, FK_Data_1, CurByte, 1018 OS, Fixups); 1019 break; 1020 case X86II::RawFrmImm16: 1021 EmitByte(BaseOpcode, CurByte, OS); 1022 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1023 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), 1024 CurByte, OS, Fixups); 1025 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 2, FK_Data_2, CurByte, 1026 OS, Fixups); 1027 break; 1028 1029 case X86II::AddRegFrm: 1030 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS); 1031 break; 1032 1033 case X86II::MRMDestReg: 1034 EmitByte(BaseOpcode, CurByte, OS); 1035 EmitRegModRMByte(MI.getOperand(CurOp), 1036 GetX86RegNum(MI.getOperand(CurOp+1)), CurByte, OS); 1037 CurOp += 2; 1038 break; 1039 1040 case X86II::MRMDestMem: 1041 EmitByte(BaseOpcode, CurByte, OS); 1042 SrcRegNum = CurOp + X86::AddrNumOperands; 1043 1044 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1045 ++SrcRegNum; 1046 1047 EmitMemModRMByte(MI, CurOp, 1048 GetX86RegNum(MI.getOperand(SrcRegNum)), 1049 TSFlags, CurByte, OS, Fixups); 1050 CurOp = SrcRegNum + 1; 1051 break; 1052 1053 case X86II::MRMSrcReg: 1054 EmitByte(BaseOpcode, CurByte, OS); 1055 SrcRegNum = CurOp + 1; 1056 1057 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1058 ++SrcRegNum; 1059 1060 if (HasMemOp4) // Skip 2nd src (which is encoded in I8IMM) 1061 ++SrcRegNum; 1062 1063 EmitRegModRMByte(MI.getOperand(SrcRegNum), 1064 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS); 1065 1066 // 2 operands skipped with HasMemOp4, compensate accordingly 1067 CurOp = HasMemOp4 ? SrcRegNum : SrcRegNum + 1; 1068 if (HasVEX_4VOp3) 1069 ++CurOp; 1070 break; 1071 1072 case X86II::MRMSrcMem: { 1073 int AddrOperands = X86::AddrNumOperands; 1074 unsigned FirstMemOp = CurOp+1; 1075 if (HasVEX_4V) { 1076 ++AddrOperands; 1077 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV). 1078 } 1079 if (HasMemOp4) // Skip second register source (encoded in I8IMM) 1080 ++FirstMemOp; 1081 1082 EmitByte(BaseOpcode, CurByte, OS); 1083 1084 EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)), 1085 TSFlags, CurByte, OS, Fixups); 1086 CurOp += AddrOperands + 1; 1087 if (HasVEX_4VOp3) 1088 ++CurOp; 1089 break; 1090 } 1091 1092 case X86II::MRM0r: case X86II::MRM1r: 1093 case X86II::MRM2r: case X86II::MRM3r: 1094 case X86II::MRM4r: case X86II::MRM5r: 1095 case X86II::MRM6r: case X86II::MRM7r: 1096 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV). 1097 ++CurOp; 1098 EmitByte(BaseOpcode, CurByte, OS); 1099 EmitRegModRMByte(MI.getOperand(CurOp++), 1100 (TSFlags & X86II::FormMask)-X86II::MRM0r, 1101 CurByte, OS); 1102 break; 1103 case X86II::MRM0m: case X86II::MRM1m: 1104 case X86II::MRM2m: case X86II::MRM3m: 1105 case X86II::MRM4m: case X86II::MRM5m: 1106 case X86II::MRM6m: case X86II::MRM7m: 1107 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV). 1108 ++CurOp; 1109 EmitByte(BaseOpcode, CurByte, OS); 1110 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m, 1111 TSFlags, CurByte, OS, Fixups); 1112 CurOp += X86::AddrNumOperands; 1113 break; 1114 case X86II::MRM_C1: case X86II::MRM_C2: 1115 case X86II::MRM_C3: case X86II::MRM_C4: 1116 case X86II::MRM_C8: case X86II::MRM_C9: 1117 case X86II::MRM_D0: case X86II::MRM_D1: 1118 case X86II::MRM_D4: case X86II::MRM_D8: 1119 case X86II::MRM_D9: case X86II::MRM_DA: 1120 case X86II::MRM_DB: case X86II::MRM_DC: 1121 case X86II::MRM_DD: case X86II::MRM_DE: 1122 case X86II::MRM_DF: case X86II::MRM_E8: 1123 case X86II::MRM_F0: case X86II::MRM_F8: 1124 case X86II::MRM_F9: 1125 EmitByte(BaseOpcode, CurByte, OS); 1126 1127 unsigned char MRM; 1128 switch (TSFlags & X86II::FormMask) { 1129 default: llvm_unreachable("Invalid Form"); 1130 case X86II::MRM_C1: MRM = 0xC1; break; 1131 case X86II::MRM_C2: MRM = 0xC2; break; 1132 case X86II::MRM_C3: MRM = 0xC3; break; 1133 case X86II::MRM_C4: MRM = 0xC4; break; 1134 case X86II::MRM_C8: MRM = 0xC8; break; 1135 case X86II::MRM_C9: MRM = 0xC9; break; 1136 case X86II::MRM_D0: MRM = 0xD0; break; 1137 case X86II::MRM_D1: MRM = 0xD1; break; 1138 case X86II::MRM_D4: MRM = 0xD4; break; 1139 case X86II::MRM_D8: MRM = 0xD8; break; 1140 case X86II::MRM_D9: MRM = 0xD9; break; 1141 case X86II::MRM_DA: MRM = 0xDA; break; 1142 case X86II::MRM_DB: MRM = 0xDB; break; 1143 case X86II::MRM_DC: MRM = 0xDC; break; 1144 case X86II::MRM_DD: MRM = 0xDD; break; 1145 case X86II::MRM_DE: MRM = 0xDE; break; 1146 case X86II::MRM_DF: MRM = 0xDF; break; 1147 case X86II::MRM_E8: MRM = 0xE8; break; 1148 case X86II::MRM_F0: MRM = 0xF0; break; 1149 case X86II::MRM_F8: MRM = 0xF8; break; 1150 case X86II::MRM_F9: MRM = 0xF9; break; 1151 } 1152 EmitByte(MRM, CurByte, OS); 1153 break; 1154 } 1155 1156 // If there is a remaining operand, it must be a trailing immediate. Emit it 1157 // according to the right size for the instruction. Some instructions 1158 // (SSE4a extrq and insertq) have two trailing immediates. 1159 while (CurOp != NumOps && NumOps - CurOp <= 2) { 1160 // The last source register of a 4 operand instruction in AVX is encoded 1161 // in bits[7:4] of a immediate byte. 1162 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) { 1163 const MCOperand &MO = MI.getOperand(HasMemOp4 ? MemOp4_I8IMMOperand 1164 : CurOp); 1165 ++CurOp; 1166 unsigned RegNum = GetX86RegNum(MO) << 4; 1167 if (X86II::isX86_64ExtendedReg(MO.getReg())) 1168 RegNum |= 1 << 7; 1169 // If there is an additional 5th operand it must be an immediate, which 1170 // is encoded in bits[3:0] 1171 if (CurOp != NumOps) { 1172 const MCOperand &MIMM = MI.getOperand(CurOp++); 1173 if (MIMM.isImm()) { 1174 unsigned Val = MIMM.getImm(); 1175 assert(Val < 16 && "Immediate operand value out of range"); 1176 RegNum |= Val; 1177 } 1178 } 1179 EmitImmediate(MCOperand::CreateImm(RegNum), MI.getLoc(), 1, FK_Data_1, 1180 CurByte, OS, Fixups); 1181 } else { 1182 unsigned FixupKind; 1183 // FIXME: Is there a better way to know that we need a signed relocation? 1184 if (MI.getOpcode() == X86::ADD64ri32 || 1185 MI.getOpcode() == X86::MOV64ri32 || 1186 MI.getOpcode() == X86::MOV64mi32 || 1187 MI.getOpcode() == X86::PUSH64i32) 1188 FixupKind = X86::reloc_signed_4byte; 1189 else 1190 FixupKind = getImmFixupKind(TSFlags); 1191 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1192 X86II::getSizeOfImm(TSFlags), MCFixupKind(FixupKind), 1193 CurByte, OS, Fixups); 1194 } 1195 } 1196 1197 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode) 1198 EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS); 1199 1200#ifndef NDEBUG 1201 // FIXME: Verify. 1202 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) { 1203 errs() << "Cannot encode all operands of: "; 1204 MI.dump(); 1205 errs() << '\n'; 1206 abort(); 1207 } 1208#endif 1209} 1210