X86MCCodeEmitter.cpp revision 4fd3d292753bd8232a76d5ac6b107f5899e5bfaa
1//===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the X86MCCodeEmitter class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "mccodeemitter" 15#include "MCTargetDesc/X86MCTargetDesc.h" 16#include "MCTargetDesc/X86BaseInfo.h" 17#include "MCTargetDesc/X86FixupKinds.h" 18#include "llvm/MC/MCCodeEmitter.h" 19#include "llvm/MC/MCExpr.h" 20#include "llvm/MC/MCInst.h" 21#include "llvm/MC/MCInstrInfo.h" 22#include "llvm/MC/MCRegisterInfo.h" 23#include "llvm/MC/MCSubtargetInfo.h" 24#include "llvm/MC/MCSymbol.h" 25#include "llvm/Support/raw_ostream.h" 26 27using namespace llvm; 28 29namespace { 30class X86MCCodeEmitter : public MCCodeEmitter { 31 X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT 32 void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT 33 const MCInstrInfo &MCII; 34 const MCSubtargetInfo &STI; 35 MCContext &Ctx; 36public: 37 X86MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti, 38 MCContext &ctx) 39 : MCII(mcii), STI(sti), Ctx(ctx) { 40 } 41 42 ~X86MCCodeEmitter() {} 43 44 bool is64BitMode() const { 45 // FIXME: Can tablegen auto-generate this? 46 return (STI.getFeatureBits() & X86::Mode64Bit) != 0; 47 } 48 49 bool is32BitMode() const { 50 // FIXME: Can tablegen auto-generate this? 51 return (STI.getFeatureBits() & X86::Mode64Bit) == 0; 52 } 53 54 static unsigned GetX86RegNum(const MCOperand &MO) { 55 return X86_MC::getX86RegNum(MO.getReg()); 56 } 57 58 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range 59 // 0-7 and the difference between the 2 groups is given by the REX prefix. 60 // In the VEX prefix, registers are seen sequencially from 0-15 and encoded 61 // in 1's complement form, example: 62 // 63 // ModRM field => XMM9 => 1 64 // VEX.VVVV => XMM9 => ~9 65 // 66 // See table 4-35 of Intel AVX Programming Reference for details. 67 static unsigned char getVEXRegisterEncoding(const MCInst &MI, 68 unsigned OpNum) { 69 unsigned SrcReg = MI.getOperand(OpNum).getReg(); 70 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum)); 71 if (X86II::isX86_64ExtendedReg(SrcReg)) 72 SrcRegNum |= 8; 73 74 // The registers represented through VEX_VVVV should 75 // be encoded in 1's complement form. 76 return (~SrcRegNum) & 0xf; 77 } 78 79 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const { 80 OS << (char)C; 81 ++CurByte; 82 } 83 84 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte, 85 raw_ostream &OS) const { 86 // Output the constant in little endian byte order. 87 for (unsigned i = 0; i != Size; ++i) { 88 EmitByte(Val & 255, CurByte, OS); 89 Val >>= 8; 90 } 91 } 92 93 void EmitImmediate(const MCOperand &Disp, SMLoc Loc, 94 unsigned ImmSize, MCFixupKind FixupKind, 95 unsigned &CurByte, raw_ostream &OS, 96 SmallVectorImpl<MCFixup> &Fixups, 97 int ImmOffset = 0) const; 98 99 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode, 100 unsigned RM) { 101 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!"); 102 return RM | (RegOpcode << 3) | (Mod << 6); 103 } 104 105 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld, 106 unsigned &CurByte, raw_ostream &OS) const { 107 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS); 108 } 109 110 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base, 111 unsigned &CurByte, raw_ostream &OS) const { 112 // SIB byte is in the same format as the ModRMByte. 113 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS); 114 } 115 116 117 void EmitMemModRMByte(const MCInst &MI, unsigned Op, 118 unsigned RegOpcodeField, 119 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS, 120 SmallVectorImpl<MCFixup> &Fixups) const; 121 122 void EncodeInstruction(const MCInst &MI, raw_ostream &OS, 123 SmallVectorImpl<MCFixup> &Fixups) const; 124 125 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, 126 const MCInst &MI, const MCInstrDesc &Desc, 127 raw_ostream &OS) const; 128 129 void EmitSegmentOverridePrefix(uint64_t TSFlags, unsigned &CurByte, 130 int MemOperand, const MCInst &MI, 131 raw_ostream &OS) const; 132 133 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, 134 const MCInst &MI, const MCInstrDesc &Desc, 135 raw_ostream &OS) const; 136}; 137 138} // end anonymous namespace 139 140 141MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII, 142 const MCSubtargetInfo &STI, 143 MCContext &Ctx) { 144 return new X86MCCodeEmitter(MCII, STI, Ctx); 145} 146 147/// isDisp8 - Return true if this signed displacement fits in a 8-bit 148/// sign-extended field. 149static bool isDisp8(int Value) { 150 return Value == (signed char)Value; 151} 152 153/// getImmFixupKind - Return the appropriate fixup kind to use for an immediate 154/// in an instruction with the specified TSFlags. 155static MCFixupKind getImmFixupKind(uint64_t TSFlags) { 156 unsigned Size = X86II::getSizeOfImm(TSFlags); 157 bool isPCRel = X86II::isImmPCRel(TSFlags); 158 159 return MCFixup::getKindForSize(Size, isPCRel); 160} 161 162/// Is32BitMemOperand - Return true if the specified instruction has 163/// a 32-bit memory operand. Op specifies the operand # of the memoperand. 164static bool Is32BitMemOperand(const MCInst &MI, unsigned Op) { 165 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 166 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 167 168 if ((BaseReg.getReg() != 0 && 169 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || 170 (IndexReg.getReg() != 0 && 171 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg()))) 172 return true; 173 return false; 174} 175 176/// Is64BitMemOperand - Return true if the specified instruction has 177/// a 64-bit memory operand. Op specifies the operand # of the memoperand. 178static bool Is64BitMemOperand(const MCInst &MI, unsigned Op) { 179 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 180 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 181 182 if ((BaseReg.getReg() != 0 && 183 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) || 184 (IndexReg.getReg() != 0 && 185 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg()))) 186 return true; 187 return false; 188} 189 190/// Is16BitMemOperand - Return true if the specified instruction has 191/// a 16-bit memory operand. Op specifies the operand # of the memoperand. 192static bool Is16BitMemOperand(const MCInst &MI, unsigned Op) { 193 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 194 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 195 196 if ((BaseReg.getReg() != 0 && 197 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) || 198 (IndexReg.getReg() != 0 && 199 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg()))) 200 return true; 201 return false; 202} 203 204/// StartsWithGlobalOffsetTable - Check if this expression starts with 205/// _GLOBAL_OFFSET_TABLE_ and if it is of the form 206/// _GLOBAL_OFFSET_TABLE_-symbol. This is needed to support PIC on ELF 207/// i386 as _GLOBAL_OFFSET_TABLE_ is magical. We check only simple case that 208/// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start 209/// of a binary expression. 210enum GlobalOffsetTableExprKind { 211 GOT_None, 212 GOT_Normal, 213 GOT_SymDiff 214}; 215static GlobalOffsetTableExprKind 216StartsWithGlobalOffsetTable(const MCExpr *Expr) { 217 const MCExpr *RHS = 0; 218 if (Expr->getKind() == MCExpr::Binary) { 219 const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr); 220 Expr = BE->getLHS(); 221 RHS = BE->getRHS(); 222 } 223 224 if (Expr->getKind() != MCExpr::SymbolRef) 225 return GOT_None; 226 227 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr); 228 const MCSymbol &S = Ref->getSymbol(); 229 if (S.getName() != "_GLOBAL_OFFSET_TABLE_") 230 return GOT_None; 231 if (RHS && RHS->getKind() == MCExpr::SymbolRef) 232 return GOT_SymDiff; 233 return GOT_Normal; 234} 235 236void X86MCCodeEmitter:: 237EmitImmediate(const MCOperand &DispOp, SMLoc Loc, unsigned Size, 238 MCFixupKind FixupKind, unsigned &CurByte, raw_ostream &OS, 239 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const { 240 const MCExpr *Expr = NULL; 241 if (DispOp.isImm()) { 242 // If this is a simple integer displacement that doesn't require a 243 // relocation, emit it now. 244 if (FixupKind != FK_PCRel_1 && 245 FixupKind != FK_PCRel_2 && 246 FixupKind != FK_PCRel_4) { 247 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS); 248 return; 249 } 250 Expr = MCConstantExpr::Create(DispOp.getImm(), Ctx); 251 } else { 252 Expr = DispOp.getExpr(); 253 } 254 255 // If we have an immoffset, add it to the expression. 256 if ((FixupKind == FK_Data_4 || 257 FixupKind == FK_Data_8 || 258 FixupKind == MCFixupKind(X86::reloc_signed_4byte))) { 259 GlobalOffsetTableExprKind Kind = StartsWithGlobalOffsetTable(Expr); 260 if (Kind != GOT_None) { 261 assert(ImmOffset == 0); 262 263 FixupKind = MCFixupKind(X86::reloc_global_offset_table); 264 if (Kind == GOT_Normal) 265 ImmOffset = CurByte; 266 } else if (Expr->getKind() == MCExpr::SymbolRef) { 267 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr); 268 if (Ref->getKind() == MCSymbolRefExpr::VK_SECREL) { 269 FixupKind = MCFixupKind(FK_SecRel_4); 270 } 271 } 272 } 273 274 // If the fixup is pc-relative, we need to bias the value to be relative to 275 // the start of the field, not the end of the field. 276 if (FixupKind == FK_PCRel_4 || 277 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) || 278 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load)) 279 ImmOffset -= 4; 280 if (FixupKind == FK_PCRel_2) 281 ImmOffset -= 2; 282 if (FixupKind == FK_PCRel_1) 283 ImmOffset -= 1; 284 285 if (ImmOffset) 286 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(ImmOffset, Ctx), 287 Ctx); 288 289 // Emit a symbolic constant as a fixup and 4 zeros. 290 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind, Loc)); 291 EmitConstant(0, Size, CurByte, OS); 292} 293 294void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op, 295 unsigned RegOpcodeField, 296 uint64_t TSFlags, unsigned &CurByte, 297 raw_ostream &OS, 298 SmallVectorImpl<MCFixup> &Fixups) const{ 299 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp); 300 const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg); 301 const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt); 302 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 303 unsigned BaseReg = Base.getReg(); 304 305 // Handle %rip relative addressing. 306 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode 307 assert(is64BitMode() && "Rip-relative addressing requires 64-bit mode"); 308 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address"); 309 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS); 310 311 unsigned FixupKind = X86::reloc_riprel_4byte; 312 313 // movq loads are handled with a special relocation form which allows the 314 // linker to eliminate some loads for GOT references which end up in the 315 // same linkage unit. 316 if (MI.getOpcode() == X86::MOV64rm) 317 FixupKind = X86::reloc_riprel_4byte_movq_load; 318 319 // rip-relative addressing is actually relative to the *next* instruction. 320 // Since an immediate can follow the mod/rm byte for an instruction, this 321 // means that we need to bias the immediate field of the instruction with 322 // the size of the immediate field. If we have this case, add it into the 323 // expression to emit. 324 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0; 325 326 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), 327 CurByte, OS, Fixups, -ImmSize); 328 return; 329 } 330 331 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U; 332 333 // Determine whether a SIB byte is needed. 334 // If no BaseReg, issue a RIP relative instruction only if the MCE can 335 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table 336 // 2-7) and absolute references. 337 338 if (// The SIB byte must be used if there is an index register. 339 IndexReg.getReg() == 0 && 340 // The SIB byte must be used if the base is ESP/RSP/R12, all of which 341 // encode to an R/M value of 4, which indicates that a SIB byte is 342 // present. 343 BaseRegNo != N86::ESP && 344 // If there is no base register and we're in 64-bit mode, we need a SIB 345 // byte to emit an addr that is just 'disp32' (the non-RIP relative form). 346 (!is64BitMode() || BaseReg != 0)) { 347 348 if (BaseReg == 0) { // [disp32] in X86-32 mode 349 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS); 350 EmitImmediate(Disp, MI.getLoc(), 4, FK_Data_4, CurByte, OS, Fixups); 351 return; 352 } 353 354 // If the base is not EBP/ESP and there is no displacement, use simple 355 // indirect register encoding, this handles addresses like [EAX]. The 356 // encoding for [EBP] with no displacement means [disp32] so we handle it 357 // by emitting a displacement of 0 below. 358 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) { 359 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS); 360 return; 361 } 362 363 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8]. 364 if (Disp.isImm() && isDisp8(Disp.getImm())) { 365 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS); 366 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups); 367 return; 368 } 369 370 // Otherwise, emit the most general non-SIB encoding: [REG+disp32] 371 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS); 372 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS, 373 Fixups); 374 return; 375 } 376 377 // We need a SIB byte, so start by outputting the ModR/M byte first 378 assert(IndexReg.getReg() != X86::ESP && 379 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!"); 380 381 bool ForceDisp32 = false; 382 bool ForceDisp8 = false; 383 if (BaseReg == 0) { 384 // If there is no base register, we emit the special case SIB byte with 385 // MOD=0, BASE=5, to JUST get the index, scale, and displacement. 386 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS); 387 ForceDisp32 = true; 388 } else if (!Disp.isImm()) { 389 // Emit the normal disp32 encoding. 390 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS); 391 ForceDisp32 = true; 392 } else if (Disp.getImm() == 0 && 393 // Base reg can't be anything that ends up with '5' as the base 394 // reg, it is the magic [*] nomenclature that indicates no base. 395 BaseRegNo != N86::EBP) { 396 // Emit no displacement ModR/M byte 397 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS); 398 } else if (isDisp8(Disp.getImm())) { 399 // Emit the disp8 encoding. 400 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS); 401 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP 402 } else { 403 // Emit the normal disp32 encoding. 404 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS); 405 } 406 407 // Calculate what the SS field value should be... 408 static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 }; 409 unsigned SS = SSTable[Scale.getImm()]; 410 411 if (BaseReg == 0) { 412 // Handle the SIB byte for the case where there is no base, see Intel 413 // Manual 2A, table 2-7. The displacement has already been output. 414 unsigned IndexRegNo; 415 if (IndexReg.getReg()) 416 IndexRegNo = GetX86RegNum(IndexReg); 417 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5) 418 IndexRegNo = 4; 419 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS); 420 } else { 421 unsigned IndexRegNo; 422 if (IndexReg.getReg()) 423 IndexRegNo = GetX86RegNum(IndexReg); 424 else 425 IndexRegNo = 4; // For example [ESP+1*<noreg>+4] 426 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS); 427 } 428 429 // Do we need to output a displacement? 430 if (ForceDisp8) 431 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups); 432 else if (ForceDisp32 || Disp.getImm() != 0) 433 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte), 434 CurByte, OS, Fixups); 435} 436 437/// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix 438/// called VEX. 439void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, 440 int MemOperand, const MCInst &MI, 441 const MCInstrDesc &Desc, 442 raw_ostream &OS) const { 443 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V; 444 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3; 445 446 // VEX_R: opcode externsion equivalent to REX.R in 447 // 1's complement (inverted) form 448 // 449 // 1: Same as REX_R=0 (must be 1 in 32-bit mode) 450 // 0: Same as REX_R=1 (64 bit mode only) 451 // 452 unsigned char VEX_R = 0x1; 453 454 // VEX_X: equivalent to REX.X, only used when a 455 // register is used for index in SIB Byte. 456 // 457 // 1: Same as REX.X=0 (must be 1 in 32-bit mode) 458 // 0: Same as REX.X=1 (64-bit mode only) 459 unsigned char VEX_X = 0x1; 460 461 // VEX_B: 462 // 463 // 1: Same as REX_B=0 (ignored in 32-bit mode) 464 // 0: Same as REX_B=1 (64 bit mode only) 465 // 466 unsigned char VEX_B = 0x1; 467 468 // VEX_W: opcode specific (use like REX.W, or used for 469 // opcode extension, or ignored, depending on the opcode byte) 470 unsigned char VEX_W = 0; 471 472 // XOP: Use XOP prefix byte 0x8f instead of VEX. 473 unsigned char XOP = 0; 474 475 // VEX_5M (VEX m-mmmmm field): 476 // 477 // 0b00000: Reserved for future use 478 // 0b00001: implied 0F leading opcode 479 // 0b00010: implied 0F 38 leading opcode bytes 480 // 0b00011: implied 0F 3A leading opcode bytes 481 // 0b00100-0b11111: Reserved for future use 482 // 0b01000: XOP map select - 08h instructions with imm byte 483 // 0b10001: XOP map select - 09h instructions with no imm byte 484 unsigned char VEX_5M = 0x1; 485 486 // VEX_4V (VEX vvvv field): a register specifier 487 // (in 1's complement form) or 1111 if unused. 488 unsigned char VEX_4V = 0xf; 489 490 // VEX_L (Vector Length): 491 // 492 // 0: scalar or 128-bit vector 493 // 1: 256-bit vector 494 // 495 unsigned char VEX_L = 0; 496 497 // VEX_PP: opcode extension providing equivalent 498 // functionality of a SIMD prefix 499 // 500 // 0b00: None 501 // 0b01: 66 502 // 0b10: F3 503 // 0b11: F2 504 // 505 unsigned char VEX_PP = 0; 506 507 // Encode the operand size opcode prefix as needed. 508 if (TSFlags & X86II::OpSize) 509 VEX_PP = 0x01; 510 511 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W) 512 VEX_W = 1; 513 514 if ((TSFlags >> X86II::VEXShift) & X86II::XOP) 515 XOP = 1; 516 517 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_L) 518 VEX_L = 1; 519 520 switch (TSFlags & X86II::Op0Mask) { 521 default: llvm_unreachable("Invalid prefix!"); 522 case X86II::T8: // 0F 38 523 VEX_5M = 0x2; 524 break; 525 case X86II::TA: // 0F 3A 526 VEX_5M = 0x3; 527 break; 528 case X86II::T8XS: // F3 0F 38 529 VEX_PP = 0x2; 530 VEX_5M = 0x2; 531 break; 532 case X86II::T8XD: // F2 0F 38 533 VEX_PP = 0x3; 534 VEX_5M = 0x2; 535 break; 536 case X86II::TAXD: // F2 0F 3A 537 VEX_PP = 0x3; 538 VEX_5M = 0x3; 539 break; 540 case X86II::XS: // F3 0F 541 VEX_PP = 0x2; 542 break; 543 case X86II::XD: // F2 0F 544 VEX_PP = 0x3; 545 break; 546 case X86II::XOP8: 547 VEX_5M = 0x8; 548 break; 549 case X86II::XOP9: 550 VEX_5M = 0x9; 551 break; 552 case X86II::A6: // Bypass: Not used by VEX 553 case X86II::A7: // Bypass: Not used by VEX 554 case X86II::TB: // Bypass: Not used by VEX 555 case 0: 556 break; // No prefix! 557 } 558 559 560 // Set the vector length to 256-bit if YMM0-YMM15 is used 561 for (unsigned i = 0; i != MI.getNumOperands(); ++i) { 562 if (!MI.getOperand(i).isReg()) 563 continue; 564 unsigned SrcReg = MI.getOperand(i).getReg(); 565 if (SrcReg >= X86::YMM0 && SrcReg <= X86::YMM15) 566 VEX_L = 1; 567 } 568 569 // Classify VEX_B, VEX_4V, VEX_R, VEX_X 570 unsigned CurOp = 0; 571 switch (TSFlags & X86II::FormMask) { 572 case X86II::MRMInitReg: llvm_unreachable("FIXME: Remove this!"); 573 case X86II::MRMDestMem: { 574 // MRMDestMem instructions forms: 575 // MemAddr, src1(ModR/M) 576 // MemAddr, src1(VEX_4V), src2(ModR/M) 577 // MemAddr, src1(ModR/M), imm8 578 // 579 if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrBaseReg).getReg())) 580 VEX_B = 0x0; 581 if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrIndexReg).getReg())) 582 VEX_X = 0x0; 583 584 CurOp = X86::AddrNumOperands; 585 if (HasVEX_4V) 586 VEX_4V = getVEXRegisterEncoding(MI, CurOp++); 587 588 const MCOperand &MO = MI.getOperand(CurOp); 589 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg())) 590 VEX_R = 0x0; 591 break; 592 } 593 case X86II::MRMSrcMem: 594 // MRMSrcMem instructions forms: 595 // src1(ModR/M), MemAddr 596 // src1(ModR/M), src2(VEX_4V), MemAddr 597 // src1(ModR/M), MemAddr, imm8 598 // src1(ModR/M), MemAddr, src2(VEX_I8IMM) 599 // 600 // FMA4: 601 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM) 602 // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M), 603 if (X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) 604 VEX_R = 0x0; 605 606 if (HasVEX_4V) 607 VEX_4V = getVEXRegisterEncoding(MI, 1); 608 609 if (X86II::isX86_64ExtendedReg( 610 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg())) 611 VEX_B = 0x0; 612 if (X86II::isX86_64ExtendedReg( 613 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg())) 614 VEX_X = 0x0; 615 616 if (HasVEX_4VOp3) 617 VEX_4V = getVEXRegisterEncoding(MI, X86::AddrNumOperands+1); 618 break; 619 case X86II::MRM0m: case X86II::MRM1m: 620 case X86II::MRM2m: case X86II::MRM3m: 621 case X86II::MRM4m: case X86II::MRM5m: 622 case X86II::MRM6m: case X86II::MRM7m: { 623 // MRM[0-9]m instructions forms: 624 // MemAddr 625 // src1(VEX_4V), MemAddr 626 if (HasVEX_4V) 627 VEX_4V = getVEXRegisterEncoding(MI, 0); 628 629 if (X86II::isX86_64ExtendedReg( 630 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg())) 631 VEX_B = 0x0; 632 if (X86II::isX86_64ExtendedReg( 633 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg())) 634 VEX_X = 0x0; 635 break; 636 } 637 case X86II::MRMSrcReg: 638 // MRMSrcReg instructions forms: 639 // dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM) 640 // dst(ModR/M), src1(ModR/M) 641 // dst(ModR/M), src1(ModR/M), imm8 642 // 643 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 644 VEX_R = 0x0; 645 CurOp++; 646 647 if (HasVEX_4V) 648 VEX_4V = getVEXRegisterEncoding(MI, CurOp++); 649 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 650 VEX_B = 0x0; 651 CurOp++; 652 if (HasVEX_4VOp3) 653 VEX_4V = getVEXRegisterEncoding(MI, CurOp); 654 break; 655 case X86II::MRMDestReg: 656 // MRMDestReg instructions forms: 657 // dst(ModR/M), src(ModR/M) 658 // dst(ModR/M), src(ModR/M), imm8 659 if (X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) 660 VEX_B = 0x0; 661 if (X86II::isX86_64ExtendedReg(MI.getOperand(1).getReg())) 662 VEX_R = 0x0; 663 break; 664 case X86II::MRM0r: case X86II::MRM1r: 665 case X86II::MRM2r: case X86II::MRM3r: 666 case X86II::MRM4r: case X86II::MRM5r: 667 case X86II::MRM6r: case X86II::MRM7r: 668 // MRM0r-MRM7r instructions forms: 669 // dst(VEX_4V), src(ModR/M), imm8 670 VEX_4V = getVEXRegisterEncoding(MI, 0); 671 if (X86II::isX86_64ExtendedReg(MI.getOperand(1).getReg())) 672 VEX_B = 0x0; 673 break; 674 default: // RawFrm 675 break; 676 } 677 678 // Emit segment override opcode prefix as needed. 679 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS); 680 681 // VEX opcode prefix can have 2 or 3 bytes 682 // 683 // 3 bytes: 684 // +-----+ +--------------+ +-------------------+ 685 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp | 686 // +-----+ +--------------+ +-------------------+ 687 // 2 bytes: 688 // +-----+ +-------------------+ 689 // | C5h | | R | vvvv | L | pp | 690 // +-----+ +-------------------+ 691 // 692 unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3); 693 694 if (VEX_B && VEX_X && !VEX_W && !XOP && (VEX_5M == 1)) { // 2 byte VEX prefix 695 EmitByte(0xC5, CurByte, OS); 696 EmitByte(LastByte | (VEX_R << 7), CurByte, OS); 697 return; 698 } 699 700 // 3 byte VEX prefix 701 EmitByte(XOP ? 0x8F : 0xC4, CurByte, OS); 702 EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS); 703 EmitByte(LastByte | (VEX_W << 7), CurByte, OS); 704} 705 706/// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64 707/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand 708/// size, and 3) use of X86-64 extended registers. 709static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags, 710 const MCInstrDesc &Desc) { 711 unsigned REX = 0; 712 if (TSFlags & X86II::REX_W) 713 REX |= 1 << 3; // set REX.W 714 715 if (MI.getNumOperands() == 0) return REX; 716 717 unsigned NumOps = MI.getNumOperands(); 718 // FIXME: MCInst should explicitize the two-addrness. 719 bool isTwoAddr = NumOps > 1 && 720 Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1; 721 722 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix. 723 unsigned i = isTwoAddr ? 1 : 0; 724 for (; i != NumOps; ++i) { 725 const MCOperand &MO = MI.getOperand(i); 726 if (!MO.isReg()) continue; 727 unsigned Reg = MO.getReg(); 728 if (!X86II::isX86_64NonExtLowByteReg(Reg)) continue; 729 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything 730 // that returns non-zero. 731 REX |= 0x40; // REX fixed encoding prefix 732 break; 733 } 734 735 switch (TSFlags & X86II::FormMask) { 736 case X86II::MRMInitReg: llvm_unreachable("FIXME: Remove this!"); 737 case X86II::MRMSrcReg: 738 if (MI.getOperand(0).isReg() && 739 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) 740 REX |= 1 << 2; // set REX.R 741 i = isTwoAddr ? 2 : 1; 742 for (; i != NumOps; ++i) { 743 const MCOperand &MO = MI.getOperand(i); 744 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg())) 745 REX |= 1 << 0; // set REX.B 746 } 747 break; 748 case X86II::MRMSrcMem: { 749 if (MI.getOperand(0).isReg() && 750 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) 751 REX |= 1 << 2; // set REX.R 752 unsigned Bit = 0; 753 i = isTwoAddr ? 2 : 1; 754 for (; i != NumOps; ++i) { 755 const MCOperand &MO = MI.getOperand(i); 756 if (MO.isReg()) { 757 if (X86II::isX86_64ExtendedReg(MO.getReg())) 758 REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1) 759 Bit++; 760 } 761 } 762 break; 763 } 764 case X86II::MRM0m: case X86II::MRM1m: 765 case X86II::MRM2m: case X86II::MRM3m: 766 case X86II::MRM4m: case X86II::MRM5m: 767 case X86II::MRM6m: case X86II::MRM7m: 768 case X86II::MRMDestMem: { 769 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands); 770 i = isTwoAddr ? 1 : 0; 771 if (NumOps > e && MI.getOperand(e).isReg() && 772 X86II::isX86_64ExtendedReg(MI.getOperand(e).getReg())) 773 REX |= 1 << 2; // set REX.R 774 unsigned Bit = 0; 775 for (; i != e; ++i) { 776 const MCOperand &MO = MI.getOperand(i); 777 if (MO.isReg()) { 778 if (X86II::isX86_64ExtendedReg(MO.getReg())) 779 REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1) 780 Bit++; 781 } 782 } 783 break; 784 } 785 default: 786 if (MI.getOperand(0).isReg() && 787 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) 788 REX |= 1 << 0; // set REX.B 789 i = isTwoAddr ? 2 : 1; 790 for (unsigned e = NumOps; i != e; ++i) { 791 const MCOperand &MO = MI.getOperand(i); 792 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg())) 793 REX |= 1 << 2; // set REX.R 794 } 795 break; 796 } 797 return REX; 798} 799 800/// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed 801void X86MCCodeEmitter::EmitSegmentOverridePrefix(uint64_t TSFlags, 802 unsigned &CurByte, int MemOperand, 803 const MCInst &MI, 804 raw_ostream &OS) const { 805 switch (TSFlags & X86II::SegOvrMask) { 806 default: llvm_unreachable("Invalid segment!"); 807 case 0: 808 // No segment override, check for explicit one on memory operand. 809 if (MemOperand != -1) { // If the instruction has a memory operand. 810 switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) { 811 default: llvm_unreachable("Unknown segment register!"); 812 case 0: break; 813 case X86::CS: EmitByte(0x2E, CurByte, OS); break; 814 case X86::SS: EmitByte(0x36, CurByte, OS); break; 815 case X86::DS: EmitByte(0x3E, CurByte, OS); break; 816 case X86::ES: EmitByte(0x26, CurByte, OS); break; 817 case X86::FS: EmitByte(0x64, CurByte, OS); break; 818 case X86::GS: EmitByte(0x65, CurByte, OS); break; 819 } 820 } 821 break; 822 case X86II::FS: 823 EmitByte(0x64, CurByte, OS); 824 break; 825 case X86II::GS: 826 EmitByte(0x65, CurByte, OS); 827 break; 828 } 829} 830 831/// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode. 832/// 833/// MemOperand is the operand # of the start of a memory operand if present. If 834/// Not present, it is -1. 835void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, 836 int MemOperand, const MCInst &MI, 837 const MCInstrDesc &Desc, 838 raw_ostream &OS) const { 839 840 // Emit the lock opcode prefix as needed. 841 if (TSFlags & X86II::LOCK) 842 EmitByte(0xF0, CurByte, OS); 843 844 // Emit segment override opcode prefix as needed. 845 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS); 846 847 // Emit the repeat opcode prefix as needed. 848 if ((TSFlags & X86II::Op0Mask) == X86II::REP) 849 EmitByte(0xF3, CurByte, OS); 850 851 // Emit the address size opcode prefix as needed. 852 bool need_address_override; 853 if (TSFlags & X86II::AdSize) { 854 need_address_override = true; 855 } else if (MemOperand == -1) { 856 need_address_override = false; 857 } else if (is64BitMode()) { 858 assert(!Is16BitMemOperand(MI, MemOperand)); 859 need_address_override = Is32BitMemOperand(MI, MemOperand); 860 } else if (is32BitMode()) { 861 assert(!Is64BitMemOperand(MI, MemOperand)); 862 need_address_override = Is16BitMemOperand(MI, MemOperand); 863 } else { 864 need_address_override = false; 865 } 866 867 if (need_address_override) 868 EmitByte(0x67, CurByte, OS); 869 870 // Emit the operand size opcode prefix as needed. 871 if (TSFlags & X86II::OpSize) 872 EmitByte(0x66, CurByte, OS); 873 874 bool Need0FPrefix = false; 875 switch (TSFlags & X86II::Op0Mask) { 876 default: llvm_unreachable("Invalid prefix!"); 877 case 0: break; // No prefix! 878 case X86II::REP: break; // already handled. 879 case X86II::TB: // Two-byte opcode prefix 880 case X86II::T8: // 0F 38 881 case X86II::TA: // 0F 3A 882 case X86II::A6: // 0F A6 883 case X86II::A7: // 0F A7 884 Need0FPrefix = true; 885 break; 886 case X86II::T8XS: // F3 0F 38 887 EmitByte(0xF3, CurByte, OS); 888 Need0FPrefix = true; 889 break; 890 case X86II::T8XD: // F2 0F 38 891 EmitByte(0xF2, CurByte, OS); 892 Need0FPrefix = true; 893 break; 894 case X86II::TAXD: // F2 0F 3A 895 EmitByte(0xF2, CurByte, OS); 896 Need0FPrefix = true; 897 break; 898 case X86II::XS: // F3 0F 899 EmitByte(0xF3, CurByte, OS); 900 Need0FPrefix = true; 901 break; 902 case X86II::XD: // F2 0F 903 EmitByte(0xF2, CurByte, OS); 904 Need0FPrefix = true; 905 break; 906 case X86II::D8: EmitByte(0xD8, CurByte, OS); break; 907 case X86II::D9: EmitByte(0xD9, CurByte, OS); break; 908 case X86II::DA: EmitByte(0xDA, CurByte, OS); break; 909 case X86II::DB: EmitByte(0xDB, CurByte, OS); break; 910 case X86II::DC: EmitByte(0xDC, CurByte, OS); break; 911 case X86II::DD: EmitByte(0xDD, CurByte, OS); break; 912 case X86II::DE: EmitByte(0xDE, CurByte, OS); break; 913 case X86II::DF: EmitByte(0xDF, CurByte, OS); break; 914 } 915 916 // Handle REX prefix. 917 // FIXME: Can this come before F2 etc to simplify emission? 918 if (is64BitMode()) { 919 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc)) 920 EmitByte(0x40 | REX, CurByte, OS); 921 } 922 923 // 0x0F escape code must be emitted just before the opcode. 924 if (Need0FPrefix) 925 EmitByte(0x0F, CurByte, OS); 926 927 // FIXME: Pull this up into previous switch if REX can be moved earlier. 928 switch (TSFlags & X86II::Op0Mask) { 929 case X86II::T8XS: // F3 0F 38 930 case X86II::T8XD: // F2 0F 38 931 case X86II::T8: // 0F 38 932 EmitByte(0x38, CurByte, OS); 933 break; 934 case X86II::TAXD: // F2 0F 3A 935 case X86II::TA: // 0F 3A 936 EmitByte(0x3A, CurByte, OS); 937 break; 938 case X86II::A6: // 0F A6 939 EmitByte(0xA6, CurByte, OS); 940 break; 941 case X86II::A7: // 0F A7 942 EmitByte(0xA7, CurByte, OS); 943 break; 944 } 945} 946 947void X86MCCodeEmitter:: 948EncodeInstruction(const MCInst &MI, raw_ostream &OS, 949 SmallVectorImpl<MCFixup> &Fixups) const { 950 unsigned Opcode = MI.getOpcode(); 951 const MCInstrDesc &Desc = MCII.get(Opcode); 952 uint64_t TSFlags = Desc.TSFlags; 953 954 // Pseudo instructions don't get encoded. 955 if ((TSFlags & X86II::FormMask) == X86II::Pseudo) 956 return; 957 958 // If this is a two-address instruction, skip one of the register operands. 959 // FIXME: This should be handled during MCInst lowering. 960 unsigned NumOps = Desc.getNumOperands(); 961 unsigned CurOp = 0; 962 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1) 963 ++CurOp; 964 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, MCOI::TIED_TO)== 0) 965 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32 966 --NumOps; 967 968 // Keep track of the current byte being emitted. 969 unsigned CurByte = 0; 970 971 // Is this instruction encoded using the AVX VEX prefix? 972 bool HasVEXPrefix = (TSFlags >> X86II::VEXShift) & X86II::VEX; 973 974 // It uses the VEX.VVVV field? 975 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V; 976 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3; 977 bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4; 978 const unsigned MemOp4_I8IMMOperand = 2; 979 980 // Determine where the memory operand starts, if present. 981 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags, Opcode); 982 if (MemoryOperand != -1) MemoryOperand += CurOp; 983 984 if (!HasVEXPrefix) 985 EmitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS); 986 else 987 EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS); 988 989 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); 990 991 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode) 992 BaseOpcode = 0x0F; // Weird 3DNow! encoding. 993 994 unsigned SrcRegNum = 0; 995 switch (TSFlags & X86II::FormMask) { 996 case X86II::MRMInitReg: 997 llvm_unreachable("FIXME: Remove this form when the JIT moves to MCCodeEmitter!"); 998 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n"; 999 llvm_unreachable("Unknown FormMask value in X86MCCodeEmitter!"); 1000 case X86II::Pseudo: 1001 llvm_unreachable("Pseudo instruction shouldn't be emitted"); 1002 case X86II::RawFrm: 1003 EmitByte(BaseOpcode, CurByte, OS); 1004 break; 1005 case X86II::RawFrmImm8: 1006 EmitByte(BaseOpcode, CurByte, OS); 1007 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1008 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), 1009 CurByte, OS, Fixups); 1010 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1, FK_Data_1, CurByte, 1011 OS, Fixups); 1012 break; 1013 case X86II::RawFrmImm16: 1014 EmitByte(BaseOpcode, CurByte, OS); 1015 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1016 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), 1017 CurByte, OS, Fixups); 1018 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 2, FK_Data_2, CurByte, 1019 OS, Fixups); 1020 break; 1021 1022 case X86II::AddRegFrm: 1023 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS); 1024 break; 1025 1026 case X86II::MRMDestReg: 1027 EmitByte(BaseOpcode, CurByte, OS); 1028 EmitRegModRMByte(MI.getOperand(CurOp), 1029 GetX86RegNum(MI.getOperand(CurOp+1)), CurByte, OS); 1030 CurOp += 2; 1031 break; 1032 1033 case X86II::MRMDestMem: 1034 EmitByte(BaseOpcode, CurByte, OS); 1035 SrcRegNum = CurOp + X86::AddrNumOperands; 1036 1037 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1038 SrcRegNum++; 1039 1040 EmitMemModRMByte(MI, CurOp, 1041 GetX86RegNum(MI.getOperand(SrcRegNum)), 1042 TSFlags, CurByte, OS, Fixups); 1043 CurOp = SrcRegNum + 1; 1044 break; 1045 1046 case X86II::MRMSrcReg: 1047 EmitByte(BaseOpcode, CurByte, OS); 1048 SrcRegNum = CurOp + 1; 1049 1050 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1051 SrcRegNum++; 1052 1053 if(HasMemOp4) // Skip 2nd src (which is encoded in I8IMM) 1054 SrcRegNum++; 1055 1056 EmitRegModRMByte(MI.getOperand(SrcRegNum), 1057 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS); 1058 1059 // 2 operands skipped with HasMemOp4, comensate accordingly 1060 CurOp = HasMemOp4 ? SrcRegNum : SrcRegNum + 1; 1061 if (HasVEX_4VOp3) 1062 ++CurOp; 1063 break; 1064 1065 case X86II::MRMSrcMem: { 1066 int AddrOperands = X86::AddrNumOperands; 1067 unsigned FirstMemOp = CurOp+1; 1068 if (HasVEX_4V) { 1069 ++AddrOperands; 1070 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV). 1071 } 1072 if(HasMemOp4) // Skip second register source (encoded in I8IMM) 1073 ++FirstMemOp; 1074 1075 EmitByte(BaseOpcode, CurByte, OS); 1076 1077 EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)), 1078 TSFlags, CurByte, OS, Fixups); 1079 CurOp += AddrOperands + 1; 1080 if (HasVEX_4VOp3) 1081 ++CurOp; 1082 break; 1083 } 1084 1085 case X86II::MRM0r: case X86II::MRM1r: 1086 case X86II::MRM2r: case X86II::MRM3r: 1087 case X86II::MRM4r: case X86II::MRM5r: 1088 case X86II::MRM6r: case X86II::MRM7r: 1089 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV). 1090 CurOp++; 1091 EmitByte(BaseOpcode, CurByte, OS); 1092 EmitRegModRMByte(MI.getOperand(CurOp++), 1093 (TSFlags & X86II::FormMask)-X86II::MRM0r, 1094 CurByte, OS); 1095 break; 1096 case X86II::MRM0m: case X86II::MRM1m: 1097 case X86II::MRM2m: case X86II::MRM3m: 1098 case X86II::MRM4m: case X86II::MRM5m: 1099 case X86II::MRM6m: case X86II::MRM7m: 1100 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV). 1101 CurOp++; 1102 EmitByte(BaseOpcode, CurByte, OS); 1103 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m, 1104 TSFlags, CurByte, OS, Fixups); 1105 CurOp += X86::AddrNumOperands; 1106 break; 1107 case X86II::MRM_C1: case X86II::MRM_C2: 1108 case X86II::MRM_C3: case X86II::MRM_C4: 1109 case X86II::MRM_C8: case X86II::MRM_C9: 1110 case X86II::MRM_D0: case X86II::MRM_D1: 1111 case X86II::MRM_D4: case X86II::MRM_D8: 1112 case X86II::MRM_D9: case X86II::MRM_DA: 1113 case X86II::MRM_DB: case X86II::MRM_DC: 1114 case X86II::MRM_DD: case X86II::MRM_DE: 1115 case X86II::MRM_DF: case X86II::MRM_E8: 1116 case X86II::MRM_F0: case X86II::MRM_F8: 1117 case X86II::MRM_F9: 1118 EmitByte(BaseOpcode, CurByte, OS); 1119 1120 unsigned char MRM; 1121 switch (TSFlags & X86II::FormMask) { 1122 default: llvm_unreachable("Invalid Form"); 1123 case X86II::MRM_C1: MRM = 0xC1; break; 1124 case X86II::MRM_C2: MRM = 0xC2; break; 1125 case X86II::MRM_C3: MRM = 0xC3; break; 1126 case X86II::MRM_C4: MRM = 0xC4; break; 1127 case X86II::MRM_C8: MRM = 0xC8; break; 1128 case X86II::MRM_C9: MRM = 0xC9; break; 1129 case X86II::MRM_D0: MRM = 0xD0; break; 1130 case X86II::MRM_D1: MRM = 0xD1; break; 1131 case X86II::MRM_D4: MRM = 0xD4; break; 1132 case X86II::MRM_D8: MRM = 0xD8; break; 1133 case X86II::MRM_D9: MRM = 0xD9; break; 1134 case X86II::MRM_DA: MRM = 0xDA; break; 1135 case X86II::MRM_DB: MRM = 0xDB; break; 1136 case X86II::MRM_DC: MRM = 0xDC; break; 1137 case X86II::MRM_DD: MRM = 0xDD; break; 1138 case X86II::MRM_DE: MRM = 0xDE; break; 1139 case X86II::MRM_DF: MRM = 0xDF; break; 1140 case X86II::MRM_E8: MRM = 0xE8; break; 1141 case X86II::MRM_F0: MRM = 0xF0; break; 1142 case X86II::MRM_F8: MRM = 0xF8; break; 1143 case X86II::MRM_F9: MRM = 0xF9; break; 1144 } 1145 EmitByte(MRM, CurByte, OS); 1146 break; 1147 } 1148 1149 // If there is a remaining operand, it must be a trailing immediate. Emit it 1150 // according to the right size for the instruction. 1151 if (CurOp != NumOps) { 1152 // The last source register of a 4 operand instruction in AVX is encoded 1153 // in bits[7:4] of a immediate byte. 1154 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) { 1155 const MCOperand &MO = MI.getOperand(HasMemOp4 ? MemOp4_I8IMMOperand 1156 : CurOp); 1157 CurOp++; 1158 bool IsExtReg = X86II::isX86_64ExtendedReg(MO.getReg()); 1159 unsigned RegNum = (IsExtReg ? (1 << 7) : 0); 1160 RegNum |= GetX86RegNum(MO) << 4; 1161 // If there is an additional 5th operand it must be an immediate, which 1162 // is encoded in bits[3:0] 1163 if(CurOp != NumOps) { 1164 const MCOperand &MIMM = MI.getOperand(CurOp++); 1165 if(MIMM.isImm()) { 1166 unsigned Val = MIMM.getImm(); 1167 assert(Val < 16 && "Immediate operand value out of range"); 1168 RegNum |= Val; 1169 } 1170 } 1171 EmitImmediate(MCOperand::CreateImm(RegNum), MI.getLoc(), 1, FK_Data_1, 1172 CurByte, OS, Fixups); 1173 } else { 1174 unsigned FixupKind; 1175 // FIXME: Is there a better way to know that we need a signed relocation? 1176 if (MI.getOpcode() == X86::ADD64ri32 || 1177 MI.getOpcode() == X86::MOV64ri32 || 1178 MI.getOpcode() == X86::MOV64mi32 || 1179 MI.getOpcode() == X86::PUSH64i32) 1180 FixupKind = X86::reloc_signed_4byte; 1181 else 1182 FixupKind = getImmFixupKind(TSFlags); 1183 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1184 X86II::getSizeOfImm(TSFlags), MCFixupKind(FixupKind), 1185 CurByte, OS, Fixups); 1186 } 1187 } 1188 1189 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode) 1190 EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS); 1191 1192#ifndef NDEBUG 1193 // FIXME: Verify. 1194 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) { 1195 errs() << "Cannot encode all operands of: "; 1196 MI.dump(); 1197 errs() << '\n'; 1198 abort(); 1199 } 1200#endif 1201} 1202