X86MCCodeEmitter.cpp revision 685707c28e2c7117f025fb4e95e6ca64ed179bb0
1//===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the X86MCCodeEmitter class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "mccodeemitter" 15#include "MCTargetDesc/X86MCTargetDesc.h" 16#include "MCTargetDesc/X86BaseInfo.h" 17#include "MCTargetDesc/X86FixupKinds.h" 18#include "llvm/MC/MCCodeEmitter.h" 19#include "llvm/MC/MCContext.h" 20#include "llvm/MC/MCExpr.h" 21#include "llvm/MC/MCInst.h" 22#include "llvm/MC/MCInstrInfo.h" 23#include "llvm/MC/MCRegisterInfo.h" 24#include "llvm/MC/MCSubtargetInfo.h" 25#include "llvm/MC/MCSymbol.h" 26#include "llvm/Support/raw_ostream.h" 27 28using namespace llvm; 29 30namespace { 31class X86MCCodeEmitter : public MCCodeEmitter { 32 X86MCCodeEmitter(const X86MCCodeEmitter &) LLVM_DELETED_FUNCTION; 33 void operator=(const X86MCCodeEmitter &) LLVM_DELETED_FUNCTION; 34 const MCInstrInfo &MCII; 35 const MCSubtargetInfo &STI; 36 MCContext &Ctx; 37public: 38 X86MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti, 39 MCContext &ctx) 40 : MCII(mcii), STI(sti), Ctx(ctx) { 41 } 42 43 ~X86MCCodeEmitter() {} 44 45 bool is64BitMode() const { 46 // FIXME: Can tablegen auto-generate this? 47 return (STI.getFeatureBits() & X86::Mode64Bit) != 0; 48 } 49 50 bool is32BitMode() const { 51 // FIXME: Can tablegen auto-generate this? 52 return (STI.getFeatureBits() & X86::Mode64Bit) == 0; 53 } 54 55 unsigned GetX86RegNum(const MCOperand &MO) const { 56 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7; 57 } 58 59 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range 60 // 0-7 and the difference between the 2 groups is given by the REX prefix. 61 // In the VEX prefix, registers are seen sequencially from 0-15 and encoded 62 // in 1's complement form, example: 63 // 64 // ModRM field => XMM9 => 1 65 // VEX.VVVV => XMM9 => ~9 66 // 67 // See table 4-35 of Intel AVX Programming Reference for details. 68 unsigned char getVEXRegisterEncoding(const MCInst &MI, 69 unsigned OpNum) const { 70 unsigned SrcReg = MI.getOperand(OpNum).getReg(); 71 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum)); 72 if (X86II::isX86_64ExtendedReg(SrcReg)) 73 SrcRegNum |= 8; 74 75 // The registers represented through VEX_VVVV should 76 // be encoded in 1's complement form. 77 return (~SrcRegNum) & 0xf; 78 } 79 80 unsigned char getWriteMaskRegisterEncoding(const MCInst &MI, 81 unsigned OpNum) const { 82 assert(X86::K0 != MI.getOperand(OpNum).getReg() && 83 "Invalid mask register as write-mask!"); 84 unsigned MaskRegNum = GetX86RegNum(MI.getOperand(OpNum)); 85 return MaskRegNum; 86 } 87 88 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const { 89 OS << (char)C; 90 ++CurByte; 91 } 92 93 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte, 94 raw_ostream &OS) const { 95 // Output the constant in little endian byte order. 96 for (unsigned i = 0; i != Size; ++i) { 97 EmitByte(Val & 255, CurByte, OS); 98 Val >>= 8; 99 } 100 } 101 102 void EmitImmediate(const MCOperand &Disp, SMLoc Loc, 103 unsigned ImmSize, MCFixupKind FixupKind, 104 unsigned &CurByte, raw_ostream &OS, 105 SmallVectorImpl<MCFixup> &Fixups, 106 int ImmOffset = 0) const; 107 108 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode, 109 unsigned RM) { 110 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!"); 111 return RM | (RegOpcode << 3) | (Mod << 6); 112 } 113 114 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld, 115 unsigned &CurByte, raw_ostream &OS) const { 116 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS); 117 } 118 119 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base, 120 unsigned &CurByte, raw_ostream &OS) const { 121 // SIB byte is in the same format as the ModRMByte. 122 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS); 123 } 124 125 126 void EmitMemModRMByte(const MCInst &MI, unsigned Op, 127 unsigned RegOpcodeField, 128 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS, 129 SmallVectorImpl<MCFixup> &Fixups) const; 130 131 void EncodeInstruction(const MCInst &MI, raw_ostream &OS, 132 SmallVectorImpl<MCFixup> &Fixups) const; 133 134 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, 135 const MCInst &MI, const MCInstrDesc &Desc, 136 raw_ostream &OS) const; 137 138 void EmitSegmentOverridePrefix(uint64_t TSFlags, unsigned &CurByte, 139 int MemOperand, const MCInst &MI, 140 raw_ostream &OS) const; 141 142 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, 143 const MCInst &MI, const MCInstrDesc &Desc, 144 raw_ostream &OS) const; 145}; 146 147} // end anonymous namespace 148 149 150MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII, 151 const MCRegisterInfo &MRI, 152 const MCSubtargetInfo &STI, 153 MCContext &Ctx) { 154 return new X86MCCodeEmitter(MCII, STI, Ctx); 155} 156 157/// isDisp8 - Return true if this signed displacement fits in a 8-bit 158/// sign-extended field. 159static bool isDisp8(int Value) { 160 return Value == (signed char)Value; 161} 162 163/// isCDisp8 - Return true if this signed displacement fits in a 8-bit 164/// compressed dispacement field. 165static bool isCDisp8(uint64_t TSFlags, int Value, int& CValue) { 166 assert(((TSFlags >> X86II::VEXShift) & X86II::EVEX) && 167 "Compressed 8-bit displacement is only valid for EVEX inst."); 168 169 unsigned CD8E = (TSFlags >> X86II::EVEX_CD8EShift) & X86II::EVEX_CD8EMask; 170 unsigned CD8V = (TSFlags >> X86II::EVEX_CD8VShift) & X86II::EVEX_CD8VMask; 171 172 if (CD8V == 0 && CD8E == 0) { 173 CValue = Value; 174 return isDisp8(Value); 175 } 176 177 unsigned MemObjSize = 1U << CD8E; 178 if (CD8V & 4) { 179 // Fixed vector length 180 MemObjSize *= 1U << (CD8V & 0x3); 181 } else { 182 // Modified vector length 183 bool EVEX_b = (TSFlags >> X86II::VEXShift) & X86II::EVEX_B; 184 if (!EVEX_b) { 185 unsigned EVEX_LL = ((TSFlags >> X86II::VEXShift) & X86II::VEX_L) ? 1 : 0; 186 EVEX_LL += ((TSFlags >> X86II::VEXShift) & X86II::EVEX_L2) ? 2 : 0; 187 assert(EVEX_LL < 3 && ""); 188 189 unsigned NumElems = (1U << (EVEX_LL + 4)) / MemObjSize; 190 NumElems /= 1U << (CD8V & 0x3); 191 192 MemObjSize *= NumElems; 193 } 194 } 195 196 unsigned MemObjMask = MemObjSize - 1; 197 assert((MemObjSize & MemObjMask) == 0 && "Invalid memory object size."); 198 199 if (Value & MemObjMask) // Unaligned offset 200 return false; 201 Value /= MemObjSize; 202 bool Ret = (Value == (signed char)Value); 203 204 if (Ret) 205 CValue = Value; 206 return Ret; 207} 208 209/// getImmFixupKind - Return the appropriate fixup kind to use for an immediate 210/// in an instruction with the specified TSFlags. 211static MCFixupKind getImmFixupKind(uint64_t TSFlags) { 212 unsigned Size = X86II::getSizeOfImm(TSFlags); 213 bool isPCRel = X86II::isImmPCRel(TSFlags); 214 215 return MCFixup::getKindForSize(Size, isPCRel); 216} 217 218/// Is32BitMemOperand - Return true if the specified instruction has 219/// a 32-bit memory operand. Op specifies the operand # of the memoperand. 220static bool Is32BitMemOperand(const MCInst &MI, unsigned Op) { 221 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 222 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 223 224 if ((BaseReg.getReg() != 0 && 225 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || 226 (IndexReg.getReg() != 0 && 227 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg()))) 228 return true; 229 return false; 230} 231 232/// Is64BitMemOperand - Return true if the specified instruction has 233/// a 64-bit memory operand. Op specifies the operand # of the memoperand. 234#ifndef NDEBUG 235static bool Is64BitMemOperand(const MCInst &MI, unsigned Op) { 236 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 237 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 238 239 if ((BaseReg.getReg() != 0 && 240 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) || 241 (IndexReg.getReg() != 0 && 242 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg()))) 243 return true; 244 return false; 245} 246#endif 247 248/// Is16BitMemOperand - Return true if the specified instruction has 249/// a 16-bit memory operand. Op specifies the operand # of the memoperand. 250static bool Is16BitMemOperand(const MCInst &MI, unsigned Op) { 251 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 252 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 253 254 if ((BaseReg.getReg() != 0 && 255 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) || 256 (IndexReg.getReg() != 0 && 257 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg()))) 258 return true; 259 return false; 260} 261 262/// StartsWithGlobalOffsetTable - Check if this expression starts with 263/// _GLOBAL_OFFSET_TABLE_ and if it is of the form 264/// _GLOBAL_OFFSET_TABLE_-symbol. This is needed to support PIC on ELF 265/// i386 as _GLOBAL_OFFSET_TABLE_ is magical. We check only simple case that 266/// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start 267/// of a binary expression. 268enum GlobalOffsetTableExprKind { 269 GOT_None, 270 GOT_Normal, 271 GOT_SymDiff 272}; 273static GlobalOffsetTableExprKind 274StartsWithGlobalOffsetTable(const MCExpr *Expr) { 275 const MCExpr *RHS = 0; 276 if (Expr->getKind() == MCExpr::Binary) { 277 const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr); 278 Expr = BE->getLHS(); 279 RHS = BE->getRHS(); 280 } 281 282 if (Expr->getKind() != MCExpr::SymbolRef) 283 return GOT_None; 284 285 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr); 286 const MCSymbol &S = Ref->getSymbol(); 287 if (S.getName() != "_GLOBAL_OFFSET_TABLE_") 288 return GOT_None; 289 if (RHS && RHS->getKind() == MCExpr::SymbolRef) 290 return GOT_SymDiff; 291 return GOT_Normal; 292} 293 294static bool HasSecRelSymbolRef(const MCExpr *Expr) { 295 if (Expr->getKind() == MCExpr::SymbolRef) { 296 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr); 297 return Ref->getKind() == MCSymbolRefExpr::VK_SECREL; 298 } 299 return false; 300} 301 302void X86MCCodeEmitter:: 303EmitImmediate(const MCOperand &DispOp, SMLoc Loc, unsigned Size, 304 MCFixupKind FixupKind, unsigned &CurByte, raw_ostream &OS, 305 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const { 306 const MCExpr *Expr = NULL; 307 if (DispOp.isImm()) { 308 // If this is a simple integer displacement that doesn't require a 309 // relocation, emit it now. 310 if (FixupKind != FK_PCRel_1 && 311 FixupKind != FK_PCRel_2 && 312 FixupKind != FK_PCRel_4) { 313 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS); 314 return; 315 } 316 Expr = MCConstantExpr::Create(DispOp.getImm(), Ctx); 317 } else { 318 Expr = DispOp.getExpr(); 319 } 320 321 // If we have an immoffset, add it to the expression. 322 if ((FixupKind == FK_Data_4 || 323 FixupKind == FK_Data_8 || 324 FixupKind == MCFixupKind(X86::reloc_signed_4byte))) { 325 GlobalOffsetTableExprKind Kind = StartsWithGlobalOffsetTable(Expr); 326 if (Kind != GOT_None) { 327 assert(ImmOffset == 0); 328 329 FixupKind = MCFixupKind(X86::reloc_global_offset_table); 330 if (Kind == GOT_Normal) 331 ImmOffset = CurByte; 332 } else if (Expr->getKind() == MCExpr::SymbolRef) { 333 if (HasSecRelSymbolRef(Expr)) { 334 FixupKind = MCFixupKind(FK_SecRel_4); 335 } 336 } else if (Expr->getKind() == MCExpr::Binary) { 337 const MCBinaryExpr *Bin = static_cast<const MCBinaryExpr*>(Expr); 338 if (HasSecRelSymbolRef(Bin->getLHS()) 339 || HasSecRelSymbolRef(Bin->getRHS())) { 340 FixupKind = MCFixupKind(FK_SecRel_4); 341 } 342 } 343 } 344 345 // If the fixup is pc-relative, we need to bias the value to be relative to 346 // the start of the field, not the end of the field. 347 if (FixupKind == FK_PCRel_4 || 348 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) || 349 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load)) 350 ImmOffset -= 4; 351 if (FixupKind == FK_PCRel_2) 352 ImmOffset -= 2; 353 if (FixupKind == FK_PCRel_1) 354 ImmOffset -= 1; 355 356 if (ImmOffset) 357 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(ImmOffset, Ctx), 358 Ctx); 359 360 // Emit a symbolic constant as a fixup and 4 zeros. 361 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind, Loc)); 362 EmitConstant(0, Size, CurByte, OS); 363} 364 365void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op, 366 unsigned RegOpcodeField, 367 uint64_t TSFlags, unsigned &CurByte, 368 raw_ostream &OS, 369 SmallVectorImpl<MCFixup> &Fixups) const{ 370 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp); 371 const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg); 372 const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt); 373 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 374 unsigned BaseReg = Base.getReg(); 375 bool HasEVEX = (TSFlags >> X86II::VEXShift) & X86II::EVEX; 376 377 // Handle %rip relative addressing. 378 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode 379 assert(is64BitMode() && "Rip-relative addressing requires 64-bit mode"); 380 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address"); 381 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS); 382 383 unsigned FixupKind = X86::reloc_riprel_4byte; 384 385 // movq loads are handled with a special relocation form which allows the 386 // linker to eliminate some loads for GOT references which end up in the 387 // same linkage unit. 388 if (MI.getOpcode() == X86::MOV64rm) 389 FixupKind = X86::reloc_riprel_4byte_movq_load; 390 391 // rip-relative addressing is actually relative to the *next* instruction. 392 // Since an immediate can follow the mod/rm byte for an instruction, this 393 // means that we need to bias the immediate field of the instruction with 394 // the size of the immediate field. If we have this case, add it into the 395 // expression to emit. 396 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0; 397 398 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), 399 CurByte, OS, Fixups, -ImmSize); 400 return; 401 } 402 403 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U; 404 405 // Determine whether a SIB byte is needed. 406 // If no BaseReg, issue a RIP relative instruction only if the MCE can 407 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table 408 // 2-7) and absolute references. 409 410 if (// The SIB byte must be used if there is an index register. 411 IndexReg.getReg() == 0 && 412 // The SIB byte must be used if the base is ESP/RSP/R12, all of which 413 // encode to an R/M value of 4, which indicates that a SIB byte is 414 // present. 415 BaseRegNo != N86::ESP && 416 // If there is no base register and we're in 64-bit mode, we need a SIB 417 // byte to emit an addr that is just 'disp32' (the non-RIP relative form). 418 (!is64BitMode() || BaseReg != 0)) { 419 420 if (BaseReg == 0) { // [disp32] in X86-32 mode 421 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS); 422 EmitImmediate(Disp, MI.getLoc(), 4, FK_Data_4, CurByte, OS, Fixups); 423 return; 424 } 425 426 // If the base is not EBP/ESP and there is no displacement, use simple 427 // indirect register encoding, this handles addresses like [EAX]. The 428 // encoding for [EBP] with no displacement means [disp32] so we handle it 429 // by emitting a displacement of 0 below. 430 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) { 431 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS); 432 return; 433 } 434 435 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8]. 436 if (Disp.isImm()) { 437 if (!HasEVEX && isDisp8(Disp.getImm())) { 438 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS); 439 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups); 440 return; 441 } 442 // Try EVEX compressed 8-bit displacement first; if failed, fall back to 443 // 32-bit displacement. 444 int CDisp8 = 0; 445 if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) { 446 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS); 447 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups, 448 CDisp8 - Disp.getImm()); 449 return; 450 } 451 } 452 453 // Otherwise, emit the most general non-SIB encoding: [REG+disp32] 454 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS); 455 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS, 456 Fixups); 457 return; 458 } 459 460 // We need a SIB byte, so start by outputting the ModR/M byte first 461 assert(IndexReg.getReg() != X86::ESP && 462 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!"); 463 464 bool ForceDisp32 = false; 465 bool ForceDisp8 = false; 466 int CDisp8 = 0; 467 int ImmOffset = 0; 468 if (BaseReg == 0) { 469 // If there is no base register, we emit the special case SIB byte with 470 // MOD=0, BASE=5, to JUST get the index, scale, and displacement. 471 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS); 472 ForceDisp32 = true; 473 } else if (!Disp.isImm()) { 474 // Emit the normal disp32 encoding. 475 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS); 476 ForceDisp32 = true; 477 } else if (Disp.getImm() == 0 && 478 // Base reg can't be anything that ends up with '5' as the base 479 // reg, it is the magic [*] nomenclature that indicates no base. 480 BaseRegNo != N86::EBP) { 481 // Emit no displacement ModR/M byte 482 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS); 483 } else if (!HasEVEX && isDisp8(Disp.getImm())) { 484 // Emit the disp8 encoding. 485 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS); 486 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP 487 } else if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) { 488 // Emit the disp8 encoding. 489 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS); 490 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP 491 ImmOffset = CDisp8 - Disp.getImm(); 492 } else { 493 // Emit the normal disp32 encoding. 494 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS); 495 } 496 497 // Calculate what the SS field value should be... 498 static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 }; 499 unsigned SS = SSTable[Scale.getImm()]; 500 501 if (BaseReg == 0) { 502 // Handle the SIB byte for the case where there is no base, see Intel 503 // Manual 2A, table 2-7. The displacement has already been output. 504 unsigned IndexRegNo; 505 if (IndexReg.getReg()) 506 IndexRegNo = GetX86RegNum(IndexReg); 507 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5) 508 IndexRegNo = 4; 509 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS); 510 } else { 511 unsigned IndexRegNo; 512 if (IndexReg.getReg()) 513 IndexRegNo = GetX86RegNum(IndexReg); 514 else 515 IndexRegNo = 4; // For example [ESP+1*<noreg>+4] 516 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS); 517 } 518 519 // Do we need to output a displacement? 520 if (ForceDisp8) 521 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups, ImmOffset); 522 else if (ForceDisp32 || Disp.getImm() != 0) 523 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte), 524 CurByte, OS, Fixups); 525} 526 527/// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix 528/// called VEX. 529void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, 530 int MemOperand, const MCInst &MI, 531 const MCInstrDesc &Desc, 532 raw_ostream &OS) const { 533 bool HasEVEX = (TSFlags >> X86II::VEXShift) & X86II::EVEX; 534 bool HasEVEX_K = HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_K); 535 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V; 536 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3; 537 bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4; 538 539 // VEX_R: opcode externsion equivalent to REX.R in 540 // 1's complement (inverted) form 541 // 542 // 1: Same as REX_R=0 (must be 1 in 32-bit mode) 543 // 0: Same as REX_R=1 (64 bit mode only) 544 // 545 unsigned char VEX_R = 0x1; 546 unsigned char EVEX_R2 = 0x1; 547 548 // VEX_X: equivalent to REX.X, only used when a 549 // register is used for index in SIB Byte. 550 // 551 // 1: Same as REX.X=0 (must be 1 in 32-bit mode) 552 // 0: Same as REX.X=1 (64-bit mode only) 553 unsigned char VEX_X = 0x1; 554 555 // VEX_B: 556 // 557 // 1: Same as REX_B=0 (ignored in 32-bit mode) 558 // 0: Same as REX_B=1 (64 bit mode only) 559 // 560 unsigned char VEX_B = 0x1; 561 562 // VEX_W: opcode specific (use like REX.W, or used for 563 // opcode extension, or ignored, depending on the opcode byte) 564 unsigned char VEX_W = 0; 565 566 // XOP: Use XOP prefix byte 0x8f instead of VEX. 567 unsigned char XOP = 0; 568 569 // VEX_5M (VEX m-mmmmm field): 570 // 571 // 0b00000: Reserved for future use 572 // 0b00001: implied 0F leading opcode 573 // 0b00010: implied 0F 38 leading opcode bytes 574 // 0b00011: implied 0F 3A leading opcode bytes 575 // 0b00100-0b11111: Reserved for future use 576 // 0b01000: XOP map select - 08h instructions with imm byte 577 // 0b10001: XOP map select - 09h instructions with no imm byte 578 unsigned char VEX_5M = 0x1; 579 580 // VEX_4V (VEX vvvv field): a register specifier 581 // (in 1's complement form) or 1111 if unused. 582 unsigned char VEX_4V = 0xf; 583 unsigned char EVEX_V2 = 0x1; 584 585 // VEX_L (Vector Length): 586 // 587 // 0: scalar or 128-bit vector 588 // 1: 256-bit vector 589 // 590 unsigned char VEX_L = 0; 591 unsigned char EVEX_L2 = 0; 592 593 // VEX_PP: opcode extension providing equivalent 594 // functionality of a SIMD prefix 595 // 596 // 0b00: None 597 // 0b01: 66 598 // 0b10: F3 599 // 0b11: F2 600 // 601 unsigned char VEX_PP = 0; 602 603 // EVEX_U 604 unsigned char EVEX_U = 1; // Always '1' so far 605 606 // EVEX_z 607 unsigned char EVEX_z = 0; 608 609 // EVEX_b 610 unsigned char EVEX_b = 0; 611 612 // EVEX_aaa 613 unsigned char EVEX_aaa = 0; 614 615 // Encode the operand size opcode prefix as needed. 616 if (TSFlags & X86II::OpSize) 617 VEX_PP = 0x01; 618 619 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W) 620 VEX_W = 1; 621 622 if ((TSFlags >> X86II::VEXShift) & X86II::XOP) 623 XOP = 1; 624 625 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_L) 626 VEX_L = 1; 627 if (HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_L2)) 628 EVEX_L2 = 1; 629 630 if (HasEVEX_K && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_Z)) 631 EVEX_z = 1; 632 633 if (HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_B)) 634 EVEX_b = 1; 635 636 switch (TSFlags & X86II::Op0Mask) { 637 default: llvm_unreachable("Invalid prefix!"); 638 case X86II::T8: // 0F 38 639 VEX_5M = 0x2; 640 break; 641 case X86II::TA: // 0F 3A 642 VEX_5M = 0x3; 643 break; 644 case X86II::T8XS: // F3 0F 38 645 VEX_PP = 0x2; 646 VEX_5M = 0x2; 647 break; 648 case X86II::T8XD: // F2 0F 38 649 VEX_PP = 0x3; 650 VEX_5M = 0x2; 651 break; 652 case X86II::TAXD: // F2 0F 3A 653 VEX_PP = 0x3; 654 VEX_5M = 0x3; 655 break; 656 case X86II::XS: // F3 0F 657 VEX_PP = 0x2; 658 break; 659 case X86II::XD: // F2 0F 660 VEX_PP = 0x3; 661 break; 662 case X86II::XOP8: 663 VEX_5M = 0x8; 664 break; 665 case X86II::XOP9: 666 VEX_5M = 0x9; 667 break; 668 case X86II::XOPA: 669 VEX_5M = 0xA; 670 break; 671 case X86II::A6: // Bypass: Not used by VEX 672 case X86II::A7: // Bypass: Not used by VEX 673 case X86II::TB: // Bypass: Not used by VEX 674 case 0: 675 break; // No prefix! 676 } 677 678 679 // Classify VEX_B, VEX_4V, VEX_R, VEX_X 680 unsigned NumOps = Desc.getNumOperands(); 681 unsigned CurOp = 0; 682 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0) 683 ++CurOp; 684 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && 685 Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1) 686 // Special case for AVX-512 GATHER with 2 TIED_TO operands 687 // Skip the first 2 operands: dst, mask_wb 688 CurOp += 2; 689 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && 690 Desc.getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1) 691 // Special case for GATHER with 2 TIED_TO operands 692 // Skip the first 2 operands: dst, mask_wb 693 CurOp += 2; 694 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps - 2, MCOI::TIED_TO) == 0) 695 // SCATTER 696 ++CurOp; 697 698 switch (TSFlags & X86II::FormMask) { 699 case X86II::MRMInitReg: llvm_unreachable("FIXME: Remove this!"); 700 case X86II::MRMDestMem: { 701 // MRMDestMem instructions forms: 702 // MemAddr, src1(ModR/M) 703 // MemAddr, src1(VEX_4V), src2(ModR/M) 704 // MemAddr, src1(ModR/M), imm8 705 // 706 if (X86II::isX86_64ExtendedReg(MI.getOperand(MemOperand + 707 X86::AddrBaseReg).getReg())) 708 VEX_B = 0x0; 709 if (X86II::isX86_64ExtendedReg(MI.getOperand(MemOperand + 710 X86::AddrIndexReg).getReg())) 711 VEX_X = 0x0; 712 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(MemOperand + 713 X86::AddrIndexReg).getReg())) 714 EVEX_V2 = 0x0; 715 716 CurOp += X86::AddrNumOperands; 717 718 if (HasEVEX_K) 719 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++); 720 721 if (HasVEX_4V) { 722 VEX_4V = getVEXRegisterEncoding(MI, CurOp); 723 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 724 EVEX_V2 = 0x0; 725 CurOp++; 726 } 727 728 const MCOperand &MO = MI.getOperand(CurOp); 729 if (MO.isReg()) { 730 if (X86II::isX86_64ExtendedReg(MO.getReg())) 731 VEX_R = 0x0; 732 if (HasEVEX && X86II::is32ExtendedReg(MO.getReg())) 733 EVEX_R2 = 0x0; 734 } 735 break; 736 } 737 case X86II::MRMSrcMem: 738 // MRMSrcMem instructions forms: 739 // src1(ModR/M), MemAddr 740 // src1(ModR/M), src2(VEX_4V), MemAddr 741 // src1(ModR/M), MemAddr, imm8 742 // src1(ModR/M), MemAddr, src2(VEX_I8IMM) 743 // 744 // FMA4: 745 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM) 746 // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M), 747 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 748 VEX_R = 0x0; 749 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 750 EVEX_R2 = 0x0; 751 CurOp++; 752 753 if (HasEVEX_K) 754 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++); 755 756 if (HasVEX_4V) { 757 VEX_4V = getVEXRegisterEncoding(MI, CurOp); 758 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 759 EVEX_V2 = 0x0; 760 CurOp++; 761 } 762 763 if (X86II::isX86_64ExtendedReg( 764 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg())) 765 VEX_B = 0x0; 766 if (X86II::isX86_64ExtendedReg( 767 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg())) 768 VEX_X = 0x0; 769 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(MemOperand + 770 X86::AddrIndexReg).getReg())) 771 EVEX_V2 = 0x0; 772 773 if (HasVEX_4VOp3) 774 // Instruction format for 4VOp3: 775 // src1(ModR/M), MemAddr, src3(VEX_4V) 776 // CurOp points to start of the MemoryOperand, 777 // it skips TIED_TO operands if exist, then increments past src1. 778 // CurOp + X86::AddrNumOperands will point to src3. 779 VEX_4V = getVEXRegisterEncoding(MI, CurOp+X86::AddrNumOperands); 780 break; 781 case X86II::MRM0m: case X86II::MRM1m: 782 case X86II::MRM2m: case X86II::MRM3m: 783 case X86II::MRM4m: case X86II::MRM5m: 784 case X86II::MRM6m: case X86II::MRM7m: { 785 // MRM[0-9]m instructions forms: 786 // MemAddr 787 // src1(VEX_4V), MemAddr 788 if (HasVEX_4V) { 789 VEX_4V = getVEXRegisterEncoding(MI, CurOp); 790 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 791 EVEX_V2 = 0x0; 792 CurOp++; 793 } 794 795 if (HasEVEX_K) 796 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++); 797 798 if (X86II::isX86_64ExtendedReg( 799 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg())) 800 VEX_B = 0x0; 801 if (X86II::isX86_64ExtendedReg( 802 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg())) 803 VEX_X = 0x0; 804 break; 805 } 806 case X86II::MRMSrcReg: 807 // MRMSrcReg instructions forms: 808 // dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM) 809 // dst(ModR/M), src1(ModR/M) 810 // dst(ModR/M), src1(ModR/M), imm8 811 // 812 // FMA4: 813 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM) 814 // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M), 815 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 816 VEX_R = 0x0; 817 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 818 EVEX_R2 = 0x0; 819 CurOp++; 820 821 if (HasEVEX_K) 822 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++); 823 824 if (HasVEX_4V) { 825 VEX_4V = getVEXRegisterEncoding(MI, CurOp); 826 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 827 EVEX_V2 = 0x0; 828 CurOp++; 829 } 830 831 if (HasMemOp4) // Skip second register source (encoded in I8IMM) 832 CurOp++; 833 834 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 835 VEX_B = 0x0; 836 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 837 VEX_X = 0x0; 838 CurOp++; 839 if (HasVEX_4VOp3) 840 VEX_4V = getVEXRegisterEncoding(MI, CurOp); 841 break; 842 case X86II::MRMDestReg: 843 // MRMDestReg instructions forms: 844 // dst(ModR/M), src(ModR/M) 845 // dst(ModR/M), src(ModR/M), imm8 846 // dst(ModR/M), src1(VEX_4V), src2(ModR/M) 847 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 848 VEX_B = 0x0; 849 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 850 VEX_X = 0x0; 851 CurOp++; 852 853 if (HasEVEX_K) 854 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++); 855 856 if (HasVEX_4V) { 857 VEX_4V = getVEXRegisterEncoding(MI, CurOp); 858 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 859 EVEX_V2 = 0x0; 860 CurOp++; 861 } 862 863 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 864 VEX_R = 0x0; 865 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 866 EVEX_R2 = 0x0; 867 break; 868 case X86II::MRM0r: case X86II::MRM1r: 869 case X86II::MRM2r: case X86II::MRM3r: 870 case X86II::MRM4r: case X86II::MRM5r: 871 case X86II::MRM6r: case X86II::MRM7r: 872 // MRM0r-MRM7r instructions forms: 873 // dst(VEX_4V), src(ModR/M), imm8 874 if (HasVEX_4V) { 875 VEX_4V = getVEXRegisterEncoding(MI, CurOp); 876 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 877 EVEX_V2 = 0x0; 878 CurOp++; 879 } 880 if (HasEVEX_K) 881 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++); 882 883 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 884 VEX_B = 0x0; 885 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 886 VEX_X = 0x0; 887 break; 888 default: // RawFrm 889 break; 890 } 891 892 // Emit segment override opcode prefix as needed. 893 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS); 894 895 if (!HasEVEX) { 896 // VEX opcode prefix can have 2 or 3 bytes 897 // 898 // 3 bytes: 899 // +-----+ +--------------+ +-------------------+ 900 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp | 901 // +-----+ +--------------+ +-------------------+ 902 // 2 bytes: 903 // +-----+ +-------------------+ 904 // | C5h | | R | vvvv | L | pp | 905 // +-----+ +-------------------+ 906 // 907 unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3); 908 909 if (VEX_B && VEX_X && !VEX_W && !XOP && (VEX_5M == 1)) { // 2 byte VEX prefix 910 EmitByte(0xC5, CurByte, OS); 911 EmitByte(LastByte | (VEX_R << 7), CurByte, OS); 912 return; 913 } 914 915 // 3 byte VEX prefix 916 EmitByte(XOP ? 0x8F : 0xC4, CurByte, OS); 917 EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS); 918 EmitByte(LastByte | (VEX_W << 7), CurByte, OS); 919 } else { 920 // EVEX opcode prefix can have 4 bytes 921 // 922 // +-----+ +--------------+ +-------------------+ +------------------------+ 923 // | 62h | | RXBR' | 00mm | | W | vvvv | U | pp | | z | L'L | b | v' | aaa | 924 // +-----+ +--------------+ +-------------------+ +------------------------+ 925 assert((VEX_5M & 0x3) == VEX_5M 926 && "More than 2 significant bits in VEX.m-mmmm fields for EVEX!"); 927 928 VEX_5M &= 0x3; 929 930 EmitByte(0x62, CurByte, OS); 931 EmitByte((VEX_R << 7) | 932 (VEX_X << 6) | 933 (VEX_B << 5) | 934 (EVEX_R2 << 4) | 935 VEX_5M, CurByte, OS); 936 EmitByte((VEX_W << 7) | 937 (VEX_4V << 3) | 938 (EVEX_U << 2) | 939 VEX_PP, CurByte, OS); 940 EmitByte((EVEX_z << 7) | 941 (EVEX_L2 << 6) | 942 (VEX_L << 5) | 943 (EVEX_b << 4) | 944 (EVEX_V2 << 3) | 945 EVEX_aaa, CurByte, OS); 946 } 947} 948 949/// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64 950/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand 951/// size, and 3) use of X86-64 extended registers. 952static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags, 953 const MCInstrDesc &Desc) { 954 unsigned REX = 0; 955 if (TSFlags & X86II::REX_W) 956 REX |= 1 << 3; // set REX.W 957 958 if (MI.getNumOperands() == 0) return REX; 959 960 unsigned NumOps = MI.getNumOperands(); 961 // FIXME: MCInst should explicitize the two-addrness. 962 bool isTwoAddr = NumOps > 1 && 963 Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1; 964 965 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix. 966 unsigned i = isTwoAddr ? 1 : 0; 967 for (; i != NumOps; ++i) { 968 const MCOperand &MO = MI.getOperand(i); 969 if (!MO.isReg()) continue; 970 unsigned Reg = MO.getReg(); 971 if (!X86II::isX86_64NonExtLowByteReg(Reg)) continue; 972 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything 973 // that returns non-zero. 974 REX |= 0x40; // REX fixed encoding prefix 975 break; 976 } 977 978 switch (TSFlags & X86II::FormMask) { 979 case X86II::MRMInitReg: llvm_unreachable("FIXME: Remove this!"); 980 case X86II::MRMSrcReg: 981 if (MI.getOperand(0).isReg() && 982 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) 983 REX |= 1 << 2; // set REX.R 984 i = isTwoAddr ? 2 : 1; 985 for (; i != NumOps; ++i) { 986 const MCOperand &MO = MI.getOperand(i); 987 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg())) 988 REX |= 1 << 0; // set REX.B 989 } 990 break; 991 case X86II::MRMSrcMem: { 992 if (MI.getOperand(0).isReg() && 993 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) 994 REX |= 1 << 2; // set REX.R 995 unsigned Bit = 0; 996 i = isTwoAddr ? 2 : 1; 997 for (; i != NumOps; ++i) { 998 const MCOperand &MO = MI.getOperand(i); 999 if (MO.isReg()) { 1000 if (X86II::isX86_64ExtendedReg(MO.getReg())) 1001 REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1) 1002 Bit++; 1003 } 1004 } 1005 break; 1006 } 1007 case X86II::MRM0m: case X86II::MRM1m: 1008 case X86II::MRM2m: case X86II::MRM3m: 1009 case X86II::MRM4m: case X86II::MRM5m: 1010 case X86II::MRM6m: case X86II::MRM7m: 1011 case X86II::MRMDestMem: { 1012 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands); 1013 i = isTwoAddr ? 1 : 0; 1014 if (NumOps > e && MI.getOperand(e).isReg() && 1015 X86II::isX86_64ExtendedReg(MI.getOperand(e).getReg())) 1016 REX |= 1 << 2; // set REX.R 1017 unsigned Bit = 0; 1018 for (; i != e; ++i) { 1019 const MCOperand &MO = MI.getOperand(i); 1020 if (MO.isReg()) { 1021 if (X86II::isX86_64ExtendedReg(MO.getReg())) 1022 REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1) 1023 Bit++; 1024 } 1025 } 1026 break; 1027 } 1028 default: 1029 if (MI.getOperand(0).isReg() && 1030 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) 1031 REX |= 1 << 0; // set REX.B 1032 i = isTwoAddr ? 2 : 1; 1033 for (unsigned e = NumOps; i != e; ++i) { 1034 const MCOperand &MO = MI.getOperand(i); 1035 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg())) 1036 REX |= 1 << 2; // set REX.R 1037 } 1038 break; 1039 } 1040 return REX; 1041} 1042 1043/// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed 1044void X86MCCodeEmitter::EmitSegmentOverridePrefix(uint64_t TSFlags, 1045 unsigned &CurByte, int MemOperand, 1046 const MCInst &MI, 1047 raw_ostream &OS) const { 1048 switch (TSFlags & X86II::SegOvrMask) { 1049 default: llvm_unreachable("Invalid segment!"); 1050 case 0: 1051 // No segment override, check for explicit one on memory operand. 1052 if (MemOperand != -1) { // If the instruction has a memory operand. 1053 switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) { 1054 default: llvm_unreachable("Unknown segment register!"); 1055 case 0: break; 1056 case X86::CS: EmitByte(0x2E, CurByte, OS); break; 1057 case X86::SS: EmitByte(0x36, CurByte, OS); break; 1058 case X86::DS: EmitByte(0x3E, CurByte, OS); break; 1059 case X86::ES: EmitByte(0x26, CurByte, OS); break; 1060 case X86::FS: EmitByte(0x64, CurByte, OS); break; 1061 case X86::GS: EmitByte(0x65, CurByte, OS); break; 1062 } 1063 } 1064 break; 1065 case X86II::FS: 1066 EmitByte(0x64, CurByte, OS); 1067 break; 1068 case X86II::GS: 1069 EmitByte(0x65, CurByte, OS); 1070 break; 1071 } 1072} 1073 1074/// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode. 1075/// 1076/// MemOperand is the operand # of the start of a memory operand if present. If 1077/// Not present, it is -1. 1078void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, 1079 int MemOperand, const MCInst &MI, 1080 const MCInstrDesc &Desc, 1081 raw_ostream &OS) const { 1082 1083 // Emit the lock opcode prefix as needed. 1084 if (TSFlags & X86II::LOCK) 1085 EmitByte(0xF0, CurByte, OS); 1086 1087 // Emit segment override opcode prefix as needed. 1088 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS); 1089 1090 // Emit the repeat opcode prefix as needed. 1091 if ((TSFlags & X86II::Op0Mask) == X86II::REP) 1092 EmitByte(0xF3, CurByte, OS); 1093 1094 // Emit the address size opcode prefix as needed. 1095 bool need_address_override; 1096 if (TSFlags & X86II::AdSize) { 1097 need_address_override = true; 1098 } else if (MemOperand == -1) { 1099 need_address_override = false; 1100 } else if (is64BitMode()) { 1101 assert(!Is16BitMemOperand(MI, MemOperand)); 1102 need_address_override = Is32BitMemOperand(MI, MemOperand); 1103 } else if (is32BitMode()) { 1104 assert(!Is64BitMemOperand(MI, MemOperand)); 1105 need_address_override = Is16BitMemOperand(MI, MemOperand); 1106 } else { 1107 need_address_override = false; 1108 } 1109 1110 if (need_address_override) 1111 EmitByte(0x67, CurByte, OS); 1112 1113 // Emit the operand size opcode prefix as needed. 1114 if (TSFlags & X86II::OpSize) 1115 EmitByte(0x66, CurByte, OS); 1116 1117 bool Need0FPrefix = false; 1118 switch (TSFlags & X86II::Op0Mask) { 1119 default: llvm_unreachable("Invalid prefix!"); 1120 case 0: break; // No prefix! 1121 case X86II::REP: break; // already handled. 1122 case X86II::TB: // Two-byte opcode prefix 1123 case X86II::T8: // 0F 38 1124 case X86II::TA: // 0F 3A 1125 case X86II::A6: // 0F A6 1126 case X86II::A7: // 0F A7 1127 Need0FPrefix = true; 1128 break; 1129 case X86II::T8XS: // F3 0F 38 1130 EmitByte(0xF3, CurByte, OS); 1131 Need0FPrefix = true; 1132 break; 1133 case X86II::T8XD: // F2 0F 38 1134 EmitByte(0xF2, CurByte, OS); 1135 Need0FPrefix = true; 1136 break; 1137 case X86II::TAXD: // F2 0F 3A 1138 EmitByte(0xF2, CurByte, OS); 1139 Need0FPrefix = true; 1140 break; 1141 case X86II::XS: // F3 0F 1142 EmitByte(0xF3, CurByte, OS); 1143 Need0FPrefix = true; 1144 break; 1145 case X86II::XD: // F2 0F 1146 EmitByte(0xF2, CurByte, OS); 1147 Need0FPrefix = true; 1148 break; 1149 case X86II::D8: EmitByte(0xD8, CurByte, OS); break; 1150 case X86II::D9: EmitByte(0xD9, CurByte, OS); break; 1151 case X86II::DA: EmitByte(0xDA, CurByte, OS); break; 1152 case X86II::DB: EmitByte(0xDB, CurByte, OS); break; 1153 case X86II::DC: EmitByte(0xDC, CurByte, OS); break; 1154 case X86II::DD: EmitByte(0xDD, CurByte, OS); break; 1155 case X86II::DE: EmitByte(0xDE, CurByte, OS); break; 1156 case X86II::DF: EmitByte(0xDF, CurByte, OS); break; 1157 } 1158 1159 // Handle REX prefix. 1160 // FIXME: Can this come before F2 etc to simplify emission? 1161 if (is64BitMode()) { 1162 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc)) 1163 EmitByte(0x40 | REX, CurByte, OS); 1164 } 1165 1166 // 0x0F escape code must be emitted just before the opcode. 1167 if (Need0FPrefix) 1168 EmitByte(0x0F, CurByte, OS); 1169 1170 // FIXME: Pull this up into previous switch if REX can be moved earlier. 1171 switch (TSFlags & X86II::Op0Mask) { 1172 case X86II::T8XS: // F3 0F 38 1173 case X86II::T8XD: // F2 0F 38 1174 case X86II::T8: // 0F 38 1175 EmitByte(0x38, CurByte, OS); 1176 break; 1177 case X86II::TAXD: // F2 0F 3A 1178 case X86II::TA: // 0F 3A 1179 EmitByte(0x3A, CurByte, OS); 1180 break; 1181 case X86II::A6: // 0F A6 1182 EmitByte(0xA6, CurByte, OS); 1183 break; 1184 case X86II::A7: // 0F A7 1185 EmitByte(0xA7, CurByte, OS); 1186 break; 1187 } 1188} 1189 1190void X86MCCodeEmitter:: 1191EncodeInstruction(const MCInst &MI, raw_ostream &OS, 1192 SmallVectorImpl<MCFixup> &Fixups) const { 1193 unsigned Opcode = MI.getOpcode(); 1194 const MCInstrDesc &Desc = MCII.get(Opcode); 1195 uint64_t TSFlags = Desc.TSFlags; 1196 1197 // Pseudo instructions don't get encoded. 1198 if ((TSFlags & X86II::FormMask) == X86II::Pseudo) 1199 return; 1200 1201 unsigned NumOps = Desc.getNumOperands(); 1202 unsigned CurOp = X86II::getOperandBias(Desc); 1203 1204 // Keep track of the current byte being emitted. 1205 unsigned CurByte = 0; 1206 1207 // Is this instruction encoded using the AVX VEX prefix? 1208 bool HasVEXPrefix = (TSFlags >> X86II::VEXShift) & X86II::VEX; 1209 1210 // It uses the VEX.VVVV field? 1211 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V; 1212 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3; 1213 bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4; 1214 const unsigned MemOp4_I8IMMOperand = 2; 1215 1216 // It uses the EVEX.aaa field? 1217 bool HasEVEX = (TSFlags >> X86II::VEXShift) & X86II::EVEX; 1218 bool HasEVEX_K = HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_K); 1219 1220 // Determine where the memory operand starts, if present. 1221 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags, Opcode); 1222 if (MemoryOperand != -1) MemoryOperand += CurOp; 1223 1224 if (!HasVEXPrefix) 1225 EmitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS); 1226 else 1227 EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS); 1228 1229 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); 1230 1231 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode) 1232 BaseOpcode = 0x0F; // Weird 3DNow! encoding. 1233 1234 unsigned SrcRegNum = 0; 1235 switch (TSFlags & X86II::FormMask) { 1236 case X86II::MRMInitReg: 1237 llvm_unreachable("FIXME: Remove this form when the JIT moves to MCCodeEmitter!"); 1238 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n"; 1239 llvm_unreachable("Unknown FormMask value in X86MCCodeEmitter!"); 1240 case X86II::Pseudo: 1241 llvm_unreachable("Pseudo instruction shouldn't be emitted"); 1242 case X86II::RawFrm: 1243 EmitByte(BaseOpcode, CurByte, OS); 1244 break; 1245 case X86II::RawFrmImm8: 1246 EmitByte(BaseOpcode, CurByte, OS); 1247 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1248 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), 1249 CurByte, OS, Fixups); 1250 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1, FK_Data_1, CurByte, 1251 OS, Fixups); 1252 break; 1253 case X86II::RawFrmImm16: 1254 EmitByte(BaseOpcode, CurByte, OS); 1255 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1256 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), 1257 CurByte, OS, Fixups); 1258 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 2, FK_Data_2, CurByte, 1259 OS, Fixups); 1260 break; 1261 1262 case X86II::AddRegFrm: 1263 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS); 1264 break; 1265 1266 case X86II::MRMDestReg: 1267 EmitByte(BaseOpcode, CurByte, OS); 1268 SrcRegNum = CurOp + 1; 1269 1270 if (HasEVEX_K) // Skip writemask 1271 SrcRegNum++; 1272 1273 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1274 ++SrcRegNum; 1275 1276 EmitRegModRMByte(MI.getOperand(CurOp), 1277 GetX86RegNum(MI.getOperand(SrcRegNum)), CurByte, OS); 1278 CurOp = SrcRegNum + 1; 1279 break; 1280 1281 case X86II::MRMDestMem: 1282 EmitByte(BaseOpcode, CurByte, OS); 1283 SrcRegNum = CurOp + X86::AddrNumOperands; 1284 1285 if (HasEVEX_K) // Skip writemask 1286 SrcRegNum++; 1287 1288 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1289 ++SrcRegNum; 1290 1291 EmitMemModRMByte(MI, CurOp, 1292 GetX86RegNum(MI.getOperand(SrcRegNum)), 1293 TSFlags, CurByte, OS, Fixups); 1294 CurOp = SrcRegNum + 1; 1295 break; 1296 1297 case X86II::MRMSrcReg: 1298 EmitByte(BaseOpcode, CurByte, OS); 1299 SrcRegNum = CurOp + 1; 1300 1301 if (HasEVEX_K) // Skip writemask 1302 SrcRegNum++; 1303 1304 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1305 ++SrcRegNum; 1306 1307 if (HasMemOp4) // Skip 2nd src (which is encoded in I8IMM) 1308 ++SrcRegNum; 1309 1310 EmitRegModRMByte(MI.getOperand(SrcRegNum), 1311 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS); 1312 1313 // 2 operands skipped with HasMemOp4, compensate accordingly 1314 CurOp = HasMemOp4 ? SrcRegNum : SrcRegNum + 1; 1315 if (HasVEX_4VOp3) 1316 ++CurOp; 1317 break; 1318 1319 case X86II::MRMSrcMem: { 1320 int AddrOperands = X86::AddrNumOperands; 1321 unsigned FirstMemOp = CurOp+1; 1322 1323 if (HasEVEX_K) { // Skip writemask 1324 ++AddrOperands; 1325 ++FirstMemOp; 1326 } 1327 1328 if (HasVEX_4V) { 1329 ++AddrOperands; 1330 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV). 1331 } 1332 if (HasMemOp4) // Skip second register source (encoded in I8IMM) 1333 ++FirstMemOp; 1334 1335 EmitByte(BaseOpcode, CurByte, OS); 1336 1337 EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)), 1338 TSFlags, CurByte, OS, Fixups); 1339 CurOp += AddrOperands + 1; 1340 if (HasVEX_4VOp3) 1341 ++CurOp; 1342 break; 1343 } 1344 1345 case X86II::MRM0r: case X86II::MRM1r: 1346 case X86II::MRM2r: case X86II::MRM3r: 1347 case X86II::MRM4r: case X86II::MRM5r: 1348 case X86II::MRM6r: case X86II::MRM7r: 1349 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV). 1350 ++CurOp; 1351 EmitByte(BaseOpcode, CurByte, OS); 1352 EmitRegModRMByte(MI.getOperand(CurOp++), 1353 (TSFlags & X86II::FormMask)-X86II::MRM0r, 1354 CurByte, OS); 1355 break; 1356 case X86II::MRM0m: case X86II::MRM1m: 1357 case X86II::MRM2m: case X86II::MRM3m: 1358 case X86II::MRM4m: case X86II::MRM5m: 1359 case X86II::MRM6m: case X86II::MRM7m: 1360 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV). 1361 ++CurOp; 1362 EmitByte(BaseOpcode, CurByte, OS); 1363 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m, 1364 TSFlags, CurByte, OS, Fixups); 1365 CurOp += X86::AddrNumOperands; 1366 break; 1367 case X86II::MRM_C1: case X86II::MRM_C2: case X86II::MRM_C3: 1368 case X86II::MRM_C4: case X86II::MRM_C8: case X86II::MRM_C9: 1369 case X86II::MRM_CA: case X86II::MRM_CB: case X86II::MRM_D0: 1370 case X86II::MRM_D1: case X86II::MRM_D4: case X86II::MRM_D5: 1371 case X86II::MRM_D6: case X86II::MRM_D8: case X86II::MRM_D9: 1372 case X86II::MRM_DA: case X86II::MRM_DB: case X86II::MRM_DC: 1373 case X86II::MRM_DD: case X86II::MRM_DE: case X86II::MRM_DF: 1374 case X86II::MRM_E8: case X86II::MRM_F0: case X86II::MRM_F8: 1375 case X86II::MRM_F9: 1376 EmitByte(BaseOpcode, CurByte, OS); 1377 1378 unsigned char MRM; 1379 switch (TSFlags & X86II::FormMask) { 1380 default: llvm_unreachable("Invalid Form"); 1381 case X86II::MRM_C1: MRM = 0xC1; break; 1382 case X86II::MRM_C2: MRM = 0xC2; break; 1383 case X86II::MRM_C3: MRM = 0xC3; break; 1384 case X86II::MRM_C4: MRM = 0xC4; break; 1385 case X86II::MRM_C8: MRM = 0xC8; break; 1386 case X86II::MRM_C9: MRM = 0xC9; break; 1387 case X86II::MRM_CA: MRM = 0xCA; break; 1388 case X86II::MRM_CB: MRM = 0xCB; break; 1389 case X86II::MRM_D0: MRM = 0xD0; break; 1390 case X86II::MRM_D1: MRM = 0xD1; break; 1391 case X86II::MRM_D4: MRM = 0xD4; break; 1392 case X86II::MRM_D5: MRM = 0xD5; break; 1393 case X86II::MRM_D6: MRM = 0xD6; break; 1394 case X86II::MRM_D8: MRM = 0xD8; break; 1395 case X86II::MRM_D9: MRM = 0xD9; break; 1396 case X86II::MRM_DA: MRM = 0xDA; break; 1397 case X86II::MRM_DB: MRM = 0xDB; break; 1398 case X86II::MRM_DC: MRM = 0xDC; break; 1399 case X86II::MRM_DD: MRM = 0xDD; break; 1400 case X86II::MRM_DE: MRM = 0xDE; break; 1401 case X86II::MRM_DF: MRM = 0xDF; break; 1402 case X86II::MRM_E8: MRM = 0xE8; break; 1403 case X86II::MRM_F0: MRM = 0xF0; break; 1404 case X86II::MRM_F8: MRM = 0xF8; break; 1405 case X86II::MRM_F9: MRM = 0xF9; break; 1406 } 1407 EmitByte(MRM, CurByte, OS); 1408 break; 1409 } 1410 1411 // If there is a remaining operand, it must be a trailing immediate. Emit it 1412 // according to the right size for the instruction. Some instructions 1413 // (SSE4a extrq and insertq) have two trailing immediates. 1414 while (CurOp != NumOps && NumOps - CurOp <= 2) { 1415 // The last source register of a 4 operand instruction in AVX is encoded 1416 // in bits[7:4] of a immediate byte. 1417 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) { 1418 const MCOperand &MO = MI.getOperand(HasMemOp4 ? MemOp4_I8IMMOperand 1419 : CurOp); 1420 ++CurOp; 1421 unsigned RegNum = GetX86RegNum(MO) << 4; 1422 if (X86II::isX86_64ExtendedReg(MO.getReg())) 1423 RegNum |= 1 << 7; 1424 // If there is an additional 5th operand it must be an immediate, which 1425 // is encoded in bits[3:0] 1426 if (CurOp != NumOps) { 1427 const MCOperand &MIMM = MI.getOperand(CurOp++); 1428 if (MIMM.isImm()) { 1429 unsigned Val = MIMM.getImm(); 1430 assert(Val < 16 && "Immediate operand value out of range"); 1431 RegNum |= Val; 1432 } 1433 } 1434 EmitImmediate(MCOperand::CreateImm(RegNum), MI.getLoc(), 1, FK_Data_1, 1435 CurByte, OS, Fixups); 1436 } else { 1437 unsigned FixupKind; 1438 // FIXME: Is there a better way to know that we need a signed relocation? 1439 if (MI.getOpcode() == X86::ADD64ri32 || 1440 MI.getOpcode() == X86::MOV64ri32 || 1441 MI.getOpcode() == X86::MOV64mi32 || 1442 MI.getOpcode() == X86::PUSH64i32) 1443 FixupKind = X86::reloc_signed_4byte; 1444 else 1445 FixupKind = getImmFixupKind(TSFlags); 1446 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1447 X86II::getSizeOfImm(TSFlags), MCFixupKind(FixupKind), 1448 CurByte, OS, Fixups); 1449 } 1450 } 1451 1452 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode) 1453 EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS); 1454 1455#ifndef NDEBUG 1456 // FIXME: Verify. 1457 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) { 1458 errs() << "Cannot encode all operands of: "; 1459 MI.dump(); 1460 errs() << '\n'; 1461 abort(); 1462 } 1463#endif 1464} 1465