X86MCCodeEmitter.cpp revision bd0decae3c0af9eb38592f305935559782096c9e
1//===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the X86MCCodeEmitter class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "mccodeemitter" 15#include "MCTargetDesc/X86MCTargetDesc.h" 16#include "MCTargetDesc/X86BaseInfo.h" 17#include "MCTargetDesc/X86FixupKinds.h" 18#include "llvm/MC/MCCodeEmitter.h" 19#include "llvm/MC/MCContext.h" 20#include "llvm/MC/MCExpr.h" 21#include "llvm/MC/MCInst.h" 22#include "llvm/MC/MCInstrInfo.h" 23#include "llvm/MC/MCRegisterInfo.h" 24#include "llvm/MC/MCSubtargetInfo.h" 25#include "llvm/MC/MCSymbol.h" 26#include "llvm/Support/raw_ostream.h" 27 28using namespace llvm; 29 30namespace { 31class X86MCCodeEmitter : public MCCodeEmitter { 32 X86MCCodeEmitter(const X86MCCodeEmitter &) LLVM_DELETED_FUNCTION; 33 void operator=(const X86MCCodeEmitter &) LLVM_DELETED_FUNCTION; 34 const MCInstrInfo &MCII; 35 const MCSubtargetInfo &STI; 36 MCContext &Ctx; 37public: 38 X86MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti, 39 MCContext &ctx) 40 : MCII(mcii), STI(sti), Ctx(ctx) { 41 } 42 43 ~X86MCCodeEmitter() {} 44 45 bool is64BitMode() const { 46 // FIXME: Can tablegen auto-generate this? 47 return (STI.getFeatureBits() & X86::Mode64Bit) != 0; 48 } 49 50 bool is32BitMode() const { 51 // FIXME: Can tablegen auto-generate this? 52 return (STI.getFeatureBits() & X86::Mode64Bit) == 0; 53 } 54 55 unsigned GetX86RegNum(const MCOperand &MO) const { 56 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7; 57 } 58 59 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range 60 // 0-7 and the difference between the 2 groups is given by the REX prefix. 61 // In the VEX prefix, registers are seen sequencially from 0-15 and encoded 62 // in 1's complement form, example: 63 // 64 // ModRM field => XMM9 => 1 65 // VEX.VVVV => XMM9 => ~9 66 // 67 // See table 4-35 of Intel AVX Programming Reference for details. 68 unsigned char getVEXRegisterEncoding(const MCInst &MI, 69 unsigned OpNum) const { 70 unsigned SrcReg = MI.getOperand(OpNum).getReg(); 71 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum)); 72 if (X86II::isX86_64ExtendedReg(SrcReg)) 73 SrcRegNum |= 8; 74 75 // The registers represented through VEX_VVVV should 76 // be encoded in 1's complement form. 77 return (~SrcRegNum) & 0xf; 78 } 79 80 unsigned char getWriteMaskRegisterEncoding(const MCInst &MI, 81 unsigned OpNum) const { 82 assert(X86::K0 != MI.getOperand(OpNum).getReg() && 83 "Invalid mask register as write-mask!"); 84 unsigned MaskRegNum = GetX86RegNum(MI.getOperand(OpNum)); 85 return MaskRegNum; 86 } 87 88 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const { 89 OS << (char)C; 90 ++CurByte; 91 } 92 93 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte, 94 raw_ostream &OS) const { 95 // Output the constant in little endian byte order. 96 for (unsigned i = 0; i != Size; ++i) { 97 EmitByte(Val & 255, CurByte, OS); 98 Val >>= 8; 99 } 100 } 101 102 void EmitImmediate(const MCOperand &Disp, SMLoc Loc, 103 unsigned ImmSize, MCFixupKind FixupKind, 104 unsigned &CurByte, raw_ostream &OS, 105 SmallVectorImpl<MCFixup> &Fixups, 106 int ImmOffset = 0) const; 107 108 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode, 109 unsigned RM) { 110 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!"); 111 return RM | (RegOpcode << 3) | (Mod << 6); 112 } 113 114 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld, 115 unsigned &CurByte, raw_ostream &OS) const { 116 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS); 117 } 118 119 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base, 120 unsigned &CurByte, raw_ostream &OS) const { 121 // SIB byte is in the same format as the ModRMByte. 122 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS); 123 } 124 125 126 void EmitMemModRMByte(const MCInst &MI, unsigned Op, 127 unsigned RegOpcodeField, 128 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS, 129 SmallVectorImpl<MCFixup> &Fixups) const; 130 131 void EncodeInstruction(const MCInst &MI, raw_ostream &OS, 132 SmallVectorImpl<MCFixup> &Fixups) const; 133 134 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, 135 const MCInst &MI, const MCInstrDesc &Desc, 136 raw_ostream &OS) const; 137 138 void EmitSegmentOverridePrefix(uint64_t TSFlags, unsigned &CurByte, 139 int MemOperand, const MCInst &MI, 140 raw_ostream &OS) const; 141 142 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, 143 const MCInst &MI, const MCInstrDesc &Desc, 144 raw_ostream &OS) const; 145}; 146 147} // end anonymous namespace 148 149 150MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII, 151 const MCRegisterInfo &MRI, 152 const MCSubtargetInfo &STI, 153 MCContext &Ctx) { 154 return new X86MCCodeEmitter(MCII, STI, Ctx); 155} 156 157/// isDisp8 - Return true if this signed displacement fits in a 8-bit 158/// sign-extended field. 159static bool isDisp8(int Value) { 160 return Value == (signed char)Value; 161} 162 163/// isCDisp8 - Return true if this signed displacement fits in a 8-bit 164/// compressed dispacement field. 165static bool isCDisp8(uint64_t TSFlags, int Value, int& CValue) { 166 assert(((TSFlags >> X86II::VEXShift) & X86II::EVEX) && 167 "Compressed 8-bit displacement is only valid for EVEX inst."); 168 169 unsigned CD8E = (TSFlags >> X86II::EVEX_CD8EShift) & X86II::EVEX_CD8EMask; 170 unsigned CD8V = (TSFlags >> X86II::EVEX_CD8VShift) & X86II::EVEX_CD8VMask; 171 172 if (CD8V == 0 && CD8E == 0) { 173 CValue = Value; 174 return isDisp8(Value); 175 } 176 177 unsigned MemObjSize = 1U << CD8E; 178 if (CD8V & 4) { 179 // Fixed vector length 180 MemObjSize *= 1U << (CD8V & 0x3); 181 } else { 182 // Modified vector length 183 bool EVEX_b = (TSFlags >> X86II::VEXShift) & X86II::EVEX_B; 184 if (!EVEX_b) { 185 unsigned EVEX_LL = ((TSFlags >> X86II::VEXShift) & X86II::VEX_L) ? 1 : 0; 186 EVEX_LL += ((TSFlags >> X86II::VEXShift) & X86II::EVEX_L2) ? 2 : 0; 187 assert(EVEX_LL < 3 && ""); 188 189 unsigned NumElems = (1U << (EVEX_LL + 4)) / MemObjSize; 190 NumElems /= 1U << (CD8V & 0x3); 191 192 MemObjSize *= NumElems; 193 } 194 } 195 196 unsigned MemObjMask = MemObjSize - 1; 197 assert((MemObjSize & MemObjMask) == 0 && "Invalid memory object size."); 198 199 if (Value & MemObjMask) // Unaligned offset 200 return false; 201 Value /= MemObjSize; 202 bool Ret = (Value == (signed char)Value); 203 204 if (Ret) 205 CValue = Value; 206 return Ret; 207} 208 209/// getImmFixupKind - Return the appropriate fixup kind to use for an immediate 210/// in an instruction with the specified TSFlags. 211static MCFixupKind getImmFixupKind(uint64_t TSFlags) { 212 unsigned Size = X86II::getSizeOfImm(TSFlags); 213 bool isPCRel = X86II::isImmPCRel(TSFlags); 214 215 return MCFixup::getKindForSize(Size, isPCRel); 216} 217 218/// Is32BitMemOperand - Return true if the specified instruction has 219/// a 32-bit memory operand. Op specifies the operand # of the memoperand. 220static bool Is32BitMemOperand(const MCInst &MI, unsigned Op) { 221 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 222 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 223 224 if ((BaseReg.getReg() != 0 && 225 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || 226 (IndexReg.getReg() != 0 && 227 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg()))) 228 return true; 229 return false; 230} 231 232/// Is64BitMemOperand - Return true if the specified instruction has 233/// a 64-bit memory operand. Op specifies the operand # of the memoperand. 234#ifndef NDEBUG 235static bool Is64BitMemOperand(const MCInst &MI, unsigned Op) { 236 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 237 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 238 239 if ((BaseReg.getReg() != 0 && 240 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) || 241 (IndexReg.getReg() != 0 && 242 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg()))) 243 return true; 244 return false; 245} 246#endif 247 248/// Is16BitMemOperand - Return true if the specified instruction has 249/// a 16-bit memory operand. Op specifies the operand # of the memoperand. 250static bool Is16BitMemOperand(const MCInst &MI, unsigned Op) { 251 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 252 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 253 254 if ((BaseReg.getReg() != 0 && 255 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) || 256 (IndexReg.getReg() != 0 && 257 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg()))) 258 return true; 259 return false; 260} 261 262/// StartsWithGlobalOffsetTable - Check if this expression starts with 263/// _GLOBAL_OFFSET_TABLE_ and if it is of the form 264/// _GLOBAL_OFFSET_TABLE_-symbol. This is needed to support PIC on ELF 265/// i386 as _GLOBAL_OFFSET_TABLE_ is magical. We check only simple case that 266/// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start 267/// of a binary expression. 268enum GlobalOffsetTableExprKind { 269 GOT_None, 270 GOT_Normal, 271 GOT_SymDiff 272}; 273static GlobalOffsetTableExprKind 274StartsWithGlobalOffsetTable(const MCExpr *Expr) { 275 const MCExpr *RHS = 0; 276 if (Expr->getKind() == MCExpr::Binary) { 277 const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr); 278 Expr = BE->getLHS(); 279 RHS = BE->getRHS(); 280 } 281 282 if (Expr->getKind() != MCExpr::SymbolRef) 283 return GOT_None; 284 285 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr); 286 const MCSymbol &S = Ref->getSymbol(); 287 if (S.getName() != "_GLOBAL_OFFSET_TABLE_") 288 return GOT_None; 289 if (RHS && RHS->getKind() == MCExpr::SymbolRef) 290 return GOT_SymDiff; 291 return GOT_Normal; 292} 293 294static bool HasSecRelSymbolRef(const MCExpr *Expr) { 295 if (Expr->getKind() == MCExpr::SymbolRef) { 296 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr); 297 return Ref->getKind() == MCSymbolRefExpr::VK_SECREL; 298 } 299 return false; 300} 301 302void X86MCCodeEmitter:: 303EmitImmediate(const MCOperand &DispOp, SMLoc Loc, unsigned Size, 304 MCFixupKind FixupKind, unsigned &CurByte, raw_ostream &OS, 305 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const { 306 const MCExpr *Expr = NULL; 307 if (DispOp.isImm()) { 308 // If this is a simple integer displacement that doesn't require a 309 // relocation, emit it now. 310 if (FixupKind != FK_PCRel_1 && 311 FixupKind != FK_PCRel_2 && 312 FixupKind != FK_PCRel_4) { 313 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS); 314 return; 315 } 316 Expr = MCConstantExpr::Create(DispOp.getImm(), Ctx); 317 } else { 318 Expr = DispOp.getExpr(); 319 } 320 321 // If we have an immoffset, add it to the expression. 322 if ((FixupKind == FK_Data_4 || 323 FixupKind == FK_Data_8 || 324 FixupKind == MCFixupKind(X86::reloc_signed_4byte))) { 325 GlobalOffsetTableExprKind Kind = StartsWithGlobalOffsetTable(Expr); 326 if (Kind != GOT_None) { 327 assert(ImmOffset == 0); 328 329 FixupKind = MCFixupKind(X86::reloc_global_offset_table); 330 if (Kind == GOT_Normal) 331 ImmOffset = CurByte; 332 } else if (Expr->getKind() == MCExpr::SymbolRef) { 333 if (HasSecRelSymbolRef(Expr)) { 334 FixupKind = MCFixupKind(FK_SecRel_4); 335 } 336 } else if (Expr->getKind() == MCExpr::Binary) { 337 const MCBinaryExpr *Bin = static_cast<const MCBinaryExpr*>(Expr); 338 if (HasSecRelSymbolRef(Bin->getLHS()) 339 || HasSecRelSymbolRef(Bin->getRHS())) { 340 FixupKind = MCFixupKind(FK_SecRel_4); 341 } 342 } 343 } 344 345 // If the fixup is pc-relative, we need to bias the value to be relative to 346 // the start of the field, not the end of the field. 347 if (FixupKind == FK_PCRel_4 || 348 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) || 349 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load)) 350 ImmOffset -= 4; 351 if (FixupKind == FK_PCRel_2) 352 ImmOffset -= 2; 353 if (FixupKind == FK_PCRel_1) 354 ImmOffset -= 1; 355 356 if (ImmOffset) 357 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(ImmOffset, Ctx), 358 Ctx); 359 360 // Emit a symbolic constant as a fixup and 4 zeros. 361 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind, Loc)); 362 EmitConstant(0, Size, CurByte, OS); 363} 364 365void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op, 366 unsigned RegOpcodeField, 367 uint64_t TSFlags, unsigned &CurByte, 368 raw_ostream &OS, 369 SmallVectorImpl<MCFixup> &Fixups) const{ 370 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp); 371 const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg); 372 const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt); 373 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 374 unsigned BaseReg = Base.getReg(); 375 bool HasEVEX = (TSFlags >> X86II::VEXShift) & X86II::EVEX; 376 377 // Handle %rip relative addressing. 378 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode 379 assert(is64BitMode() && "Rip-relative addressing requires 64-bit mode"); 380 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address"); 381 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS); 382 383 unsigned FixupKind = X86::reloc_riprel_4byte; 384 385 // movq loads are handled with a special relocation form which allows the 386 // linker to eliminate some loads for GOT references which end up in the 387 // same linkage unit. 388 if (MI.getOpcode() == X86::MOV64rm) 389 FixupKind = X86::reloc_riprel_4byte_movq_load; 390 391 // rip-relative addressing is actually relative to the *next* instruction. 392 // Since an immediate can follow the mod/rm byte for an instruction, this 393 // means that we need to bias the immediate field of the instruction with 394 // the size of the immediate field. If we have this case, add it into the 395 // expression to emit. 396 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0; 397 398 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), 399 CurByte, OS, Fixups, -ImmSize); 400 return; 401 } 402 403 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U; 404 405 // Determine whether a SIB byte is needed. 406 // If no BaseReg, issue a RIP relative instruction only if the MCE can 407 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table 408 // 2-7) and absolute references. 409 410 if (// The SIB byte must be used if there is an index register. 411 IndexReg.getReg() == 0 && 412 // The SIB byte must be used if the base is ESP/RSP/R12, all of which 413 // encode to an R/M value of 4, which indicates that a SIB byte is 414 // present. 415 BaseRegNo != N86::ESP && 416 // If there is no base register and we're in 64-bit mode, we need a SIB 417 // byte to emit an addr that is just 'disp32' (the non-RIP relative form). 418 (!is64BitMode() || BaseReg != 0)) { 419 420 if (BaseReg == 0) { // [disp32] in X86-32 mode 421 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS); 422 EmitImmediate(Disp, MI.getLoc(), 4, FK_Data_4, CurByte, OS, Fixups); 423 return; 424 } 425 426 // If the base is not EBP/ESP and there is no displacement, use simple 427 // indirect register encoding, this handles addresses like [EAX]. The 428 // encoding for [EBP] with no displacement means [disp32] so we handle it 429 // by emitting a displacement of 0 below. 430 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) { 431 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS); 432 return; 433 } 434 435 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8]. 436 if (Disp.isImm()) { 437 if (!HasEVEX && isDisp8(Disp.getImm())) { 438 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS); 439 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups); 440 return; 441 } 442 // Try EVEX compressed 8-bit displacement first; if failed, fall back to 443 // 32-bit displacement. 444 int CDisp8 = 0; 445 if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) { 446 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS); 447 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups, 448 CDisp8 - Disp.getImm()); 449 return; 450 } 451 } 452 453 // Otherwise, emit the most general non-SIB encoding: [REG+disp32] 454 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS); 455 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS, 456 Fixups); 457 return; 458 } 459 460 // We need a SIB byte, so start by outputting the ModR/M byte first 461 assert(IndexReg.getReg() != X86::ESP && 462 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!"); 463 464 bool ForceDisp32 = false; 465 bool ForceDisp8 = false; 466 int CDisp8 = 0; 467 int ImmOffset = 0; 468 if (BaseReg == 0) { 469 // If there is no base register, we emit the special case SIB byte with 470 // MOD=0, BASE=5, to JUST get the index, scale, and displacement. 471 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS); 472 ForceDisp32 = true; 473 } else if (!Disp.isImm()) { 474 // Emit the normal disp32 encoding. 475 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS); 476 ForceDisp32 = true; 477 } else if (Disp.getImm() == 0 && 478 // Base reg can't be anything that ends up with '5' as the base 479 // reg, it is the magic [*] nomenclature that indicates no base. 480 BaseRegNo != N86::EBP) { 481 // Emit no displacement ModR/M byte 482 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS); 483 } else if (!HasEVEX && isDisp8(Disp.getImm())) { 484 // Emit the disp8 encoding. 485 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS); 486 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP 487 } else if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) { 488 // Emit the disp8 encoding. 489 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS); 490 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP 491 ImmOffset = CDisp8 - Disp.getImm(); 492 } else { 493 // Emit the normal disp32 encoding. 494 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS); 495 } 496 497 // Calculate what the SS field value should be... 498 static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 }; 499 unsigned SS = SSTable[Scale.getImm()]; 500 501 if (BaseReg == 0) { 502 // Handle the SIB byte for the case where there is no base, see Intel 503 // Manual 2A, table 2-7. The displacement has already been output. 504 unsigned IndexRegNo; 505 if (IndexReg.getReg()) 506 IndexRegNo = GetX86RegNum(IndexReg); 507 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5) 508 IndexRegNo = 4; 509 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS); 510 } else { 511 unsigned IndexRegNo; 512 if (IndexReg.getReg()) 513 IndexRegNo = GetX86RegNum(IndexReg); 514 else 515 IndexRegNo = 4; // For example [ESP+1*<noreg>+4] 516 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS); 517 } 518 519 // Do we need to output a displacement? 520 if (ForceDisp8) 521 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups, ImmOffset); 522 else if (ForceDisp32 || Disp.getImm() != 0) 523 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte), 524 CurByte, OS, Fixups); 525} 526 527/// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix 528/// called VEX. 529void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, 530 int MemOperand, const MCInst &MI, 531 const MCInstrDesc &Desc, 532 raw_ostream &OS) const { 533 bool HasEVEX = (TSFlags >> X86II::VEXShift) & X86II::EVEX; 534 bool HasEVEX_K = HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_K); 535 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V; 536 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3; 537 bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4; 538 539 // VEX_R: opcode externsion equivalent to REX.R in 540 // 1's complement (inverted) form 541 // 542 // 1: Same as REX_R=0 (must be 1 in 32-bit mode) 543 // 0: Same as REX_R=1 (64 bit mode only) 544 // 545 unsigned char VEX_R = 0x1; 546 unsigned char EVEX_R2 = 0x1; 547 548 // VEX_X: equivalent to REX.X, only used when a 549 // register is used for index in SIB Byte. 550 // 551 // 1: Same as REX.X=0 (must be 1 in 32-bit mode) 552 // 0: Same as REX.X=1 (64-bit mode only) 553 unsigned char VEX_X = 0x1; 554 555 // VEX_B: 556 // 557 // 1: Same as REX_B=0 (ignored in 32-bit mode) 558 // 0: Same as REX_B=1 (64 bit mode only) 559 // 560 unsigned char VEX_B = 0x1; 561 562 // VEX_W: opcode specific (use like REX.W, or used for 563 // opcode extension, or ignored, depending on the opcode byte) 564 unsigned char VEX_W = 0; 565 566 // XOP: Use XOP prefix byte 0x8f instead of VEX. 567 unsigned char XOP = 0; 568 569 // VEX_5M (VEX m-mmmmm field): 570 // 571 // 0b00000: Reserved for future use 572 // 0b00001: implied 0F leading opcode 573 // 0b00010: implied 0F 38 leading opcode bytes 574 // 0b00011: implied 0F 3A leading opcode bytes 575 // 0b00100-0b11111: Reserved for future use 576 // 0b01000: XOP map select - 08h instructions with imm byte 577 // 0b01001: XOP map select - 09h instructions with no imm byte 578 // 0b01010: XOP map select - 0Ah instructions with imm dword 579 unsigned char VEX_5M = 0x1; 580 581 // VEX_4V (VEX vvvv field): a register specifier 582 // (in 1's complement form) or 1111 if unused. 583 unsigned char VEX_4V = 0xf; 584 unsigned char EVEX_V2 = 0x1; 585 586 // VEX_L (Vector Length): 587 // 588 // 0: scalar or 128-bit vector 589 // 1: 256-bit vector 590 // 591 unsigned char VEX_L = 0; 592 unsigned char EVEX_L2 = 0; 593 594 // VEX_PP: opcode extension providing equivalent 595 // functionality of a SIMD prefix 596 // 597 // 0b00: None 598 // 0b01: 66 599 // 0b10: F3 600 // 0b11: F2 601 // 602 unsigned char VEX_PP = 0; 603 604 // EVEX_U 605 unsigned char EVEX_U = 1; // Always '1' so far 606 607 // EVEX_z 608 unsigned char EVEX_z = 0; 609 610 // EVEX_b 611 unsigned char EVEX_b = 0; 612 613 // EVEX_aaa 614 unsigned char EVEX_aaa = 0; 615 616 // Encode the operand size opcode prefix as needed. 617 if (TSFlags & X86II::OpSize) 618 VEX_PP = 0x01; 619 620 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W) 621 VEX_W = 1; 622 623 if ((TSFlags >> X86II::VEXShift) & X86II::XOP) 624 XOP = 1; 625 626 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_L) 627 VEX_L = 1; 628 if (HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_L2)) 629 EVEX_L2 = 1; 630 631 if (HasEVEX_K && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_Z)) 632 EVEX_z = 1; 633 634 if (HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_B)) 635 EVEX_b = 1; 636 637 switch (TSFlags & X86II::Op0Mask) { 638 default: llvm_unreachable("Invalid prefix!"); 639 case X86II::T8: // 0F 38 640 VEX_5M = 0x2; 641 break; 642 case X86II::TA: // 0F 3A 643 VEX_5M = 0x3; 644 break; 645 case X86II::T8XS: // F3 0F 38 646 VEX_PP = 0x2; 647 VEX_5M = 0x2; 648 break; 649 case X86II::T8XD: // F2 0F 38 650 VEX_PP = 0x3; 651 VEX_5M = 0x2; 652 break; 653 case X86II::TAXD: // F2 0F 3A 654 VEX_PP = 0x3; 655 VEX_5M = 0x3; 656 break; 657 case X86II::XS: // F3 0F 658 VEX_PP = 0x2; 659 break; 660 case X86II::XD: // F2 0F 661 VEX_PP = 0x3; 662 break; 663 case X86II::XOP8: 664 VEX_5M = 0x8; 665 break; 666 case X86II::XOP9: 667 VEX_5M = 0x9; 668 break; 669 case X86II::XOPA: 670 VEX_5M = 0xA; 671 break; 672 case X86II::A6: // Bypass: Not used by VEX 673 case X86II::A7: // Bypass: Not used by VEX 674 case X86II::TB: // Bypass: Not used by VEX 675 case 0: 676 break; // No prefix! 677 } 678 679 680 // Classify VEX_B, VEX_4V, VEX_R, VEX_X 681 unsigned NumOps = Desc.getNumOperands(); 682 unsigned CurOp = 0; 683 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0) 684 ++CurOp; 685 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && 686 Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1) 687 // Special case for AVX-512 GATHER with 2 TIED_TO operands 688 // Skip the first 2 operands: dst, mask_wb 689 CurOp += 2; 690 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && 691 Desc.getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1) 692 // Special case for GATHER with 2 TIED_TO operands 693 // Skip the first 2 operands: dst, mask_wb 694 CurOp += 2; 695 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps - 2, MCOI::TIED_TO) == 0) 696 // SCATTER 697 ++CurOp; 698 699 switch (TSFlags & X86II::FormMask) { 700 case X86II::MRMInitReg: llvm_unreachable("FIXME: Remove this!"); 701 case X86II::MRMDestMem: { 702 // MRMDestMem instructions forms: 703 // MemAddr, src1(ModR/M) 704 // MemAddr, src1(VEX_4V), src2(ModR/M) 705 // MemAddr, src1(ModR/M), imm8 706 // 707 if (X86II::isX86_64ExtendedReg(MI.getOperand(MemOperand + 708 X86::AddrBaseReg).getReg())) 709 VEX_B = 0x0; 710 if (X86II::isX86_64ExtendedReg(MI.getOperand(MemOperand + 711 X86::AddrIndexReg).getReg())) 712 VEX_X = 0x0; 713 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(MemOperand + 714 X86::AddrIndexReg).getReg())) 715 EVEX_V2 = 0x0; 716 717 CurOp += X86::AddrNumOperands; 718 719 if (HasEVEX_K) 720 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++); 721 722 if (HasVEX_4V) { 723 VEX_4V = getVEXRegisterEncoding(MI, CurOp); 724 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 725 EVEX_V2 = 0x0; 726 CurOp++; 727 } 728 729 const MCOperand &MO = MI.getOperand(CurOp); 730 if (MO.isReg()) { 731 if (X86II::isX86_64ExtendedReg(MO.getReg())) 732 VEX_R = 0x0; 733 if (HasEVEX && X86II::is32ExtendedReg(MO.getReg())) 734 EVEX_R2 = 0x0; 735 } 736 break; 737 } 738 case X86II::MRMSrcMem: 739 // MRMSrcMem instructions forms: 740 // src1(ModR/M), MemAddr 741 // src1(ModR/M), src2(VEX_4V), MemAddr 742 // src1(ModR/M), MemAddr, imm8 743 // src1(ModR/M), MemAddr, src2(VEX_I8IMM) 744 // 745 // FMA4: 746 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM) 747 // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M), 748 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 749 VEX_R = 0x0; 750 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 751 EVEX_R2 = 0x0; 752 CurOp++; 753 754 if (HasEVEX_K) 755 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++); 756 757 if (HasVEX_4V) { 758 VEX_4V = getVEXRegisterEncoding(MI, CurOp); 759 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 760 EVEX_V2 = 0x0; 761 CurOp++; 762 } 763 764 if (X86II::isX86_64ExtendedReg( 765 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg())) 766 VEX_B = 0x0; 767 if (X86II::isX86_64ExtendedReg( 768 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg())) 769 VEX_X = 0x0; 770 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(MemOperand + 771 X86::AddrIndexReg).getReg())) 772 EVEX_V2 = 0x0; 773 774 if (HasVEX_4VOp3) 775 // Instruction format for 4VOp3: 776 // src1(ModR/M), MemAddr, src3(VEX_4V) 777 // CurOp points to start of the MemoryOperand, 778 // it skips TIED_TO operands if exist, then increments past src1. 779 // CurOp + X86::AddrNumOperands will point to src3. 780 VEX_4V = getVEXRegisterEncoding(MI, CurOp+X86::AddrNumOperands); 781 break; 782 case X86II::MRM0m: case X86II::MRM1m: 783 case X86II::MRM2m: case X86II::MRM3m: 784 case X86II::MRM4m: case X86II::MRM5m: 785 case X86II::MRM6m: case X86II::MRM7m: { 786 // MRM[0-9]m instructions forms: 787 // MemAddr 788 // src1(VEX_4V), MemAddr 789 if (HasVEX_4V) { 790 VEX_4V = getVEXRegisterEncoding(MI, CurOp); 791 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 792 EVEX_V2 = 0x0; 793 CurOp++; 794 } 795 796 if (HasEVEX_K) 797 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++); 798 799 if (X86II::isX86_64ExtendedReg( 800 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg())) 801 VEX_B = 0x0; 802 if (X86II::isX86_64ExtendedReg( 803 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg())) 804 VEX_X = 0x0; 805 break; 806 } 807 case X86II::MRMSrcReg: 808 // MRMSrcReg instructions forms: 809 // dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM) 810 // dst(ModR/M), src1(ModR/M) 811 // dst(ModR/M), src1(ModR/M), imm8 812 // 813 // FMA4: 814 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM) 815 // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M), 816 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 817 VEX_R = 0x0; 818 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 819 EVEX_R2 = 0x0; 820 CurOp++; 821 822 if (HasEVEX_K) 823 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++); 824 825 if (HasVEX_4V) { 826 VEX_4V = getVEXRegisterEncoding(MI, CurOp); 827 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 828 EVEX_V2 = 0x0; 829 CurOp++; 830 } 831 832 if (HasMemOp4) // Skip second register source (encoded in I8IMM) 833 CurOp++; 834 835 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 836 VEX_B = 0x0; 837 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 838 VEX_X = 0x0; 839 CurOp++; 840 if (HasVEX_4VOp3) 841 VEX_4V = getVEXRegisterEncoding(MI, CurOp); 842 break; 843 case X86II::MRMDestReg: 844 // MRMDestReg instructions forms: 845 // dst(ModR/M), src(ModR/M) 846 // dst(ModR/M), src(ModR/M), imm8 847 // dst(ModR/M), src1(VEX_4V), src2(ModR/M) 848 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 849 VEX_B = 0x0; 850 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 851 VEX_X = 0x0; 852 CurOp++; 853 854 if (HasEVEX_K) 855 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++); 856 857 if (HasVEX_4V) { 858 VEX_4V = getVEXRegisterEncoding(MI, CurOp); 859 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 860 EVEX_V2 = 0x0; 861 CurOp++; 862 } 863 864 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 865 VEX_R = 0x0; 866 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 867 EVEX_R2 = 0x0; 868 break; 869 case X86II::MRM0r: case X86II::MRM1r: 870 case X86II::MRM2r: case X86II::MRM3r: 871 case X86II::MRM4r: case X86II::MRM5r: 872 case X86II::MRM6r: case X86II::MRM7r: 873 // MRM0r-MRM7r instructions forms: 874 // dst(VEX_4V), src(ModR/M), imm8 875 if (HasVEX_4V) { 876 VEX_4V = getVEXRegisterEncoding(MI, CurOp); 877 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 878 EVEX_V2 = 0x0; 879 CurOp++; 880 } 881 if (HasEVEX_K) 882 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++); 883 884 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 885 VEX_B = 0x0; 886 if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 887 VEX_X = 0x0; 888 break; 889 default: // RawFrm 890 break; 891 } 892 893 // Emit segment override opcode prefix as needed. 894 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS); 895 896 if (!HasEVEX) { 897 // VEX opcode prefix can have 2 or 3 bytes 898 // 899 // 3 bytes: 900 // +-----+ +--------------+ +-------------------+ 901 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp | 902 // +-----+ +--------------+ +-------------------+ 903 // 2 bytes: 904 // +-----+ +-------------------+ 905 // | C5h | | R | vvvv | L | pp | 906 // +-----+ +-------------------+ 907 // 908 unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3); 909 910 if (VEX_B && VEX_X && !VEX_W && !XOP && (VEX_5M == 1)) { // 2 byte VEX prefix 911 EmitByte(0xC5, CurByte, OS); 912 EmitByte(LastByte | (VEX_R << 7), CurByte, OS); 913 return; 914 } 915 916 // 3 byte VEX prefix 917 EmitByte(XOP ? 0x8F : 0xC4, CurByte, OS); 918 EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS); 919 EmitByte(LastByte | (VEX_W << 7), CurByte, OS); 920 } else { 921 // EVEX opcode prefix can have 4 bytes 922 // 923 // +-----+ +--------------+ +-------------------+ +------------------------+ 924 // | 62h | | RXBR' | 00mm | | W | vvvv | U | pp | | z | L'L | b | v' | aaa | 925 // +-----+ +--------------+ +-------------------+ +------------------------+ 926 assert((VEX_5M & 0x3) == VEX_5M 927 && "More than 2 significant bits in VEX.m-mmmm fields for EVEX!"); 928 929 VEX_5M &= 0x3; 930 931 EmitByte(0x62, CurByte, OS); 932 EmitByte((VEX_R << 7) | 933 (VEX_X << 6) | 934 (VEX_B << 5) | 935 (EVEX_R2 << 4) | 936 VEX_5M, CurByte, OS); 937 EmitByte((VEX_W << 7) | 938 (VEX_4V << 3) | 939 (EVEX_U << 2) | 940 VEX_PP, CurByte, OS); 941 EmitByte((EVEX_z << 7) | 942 (EVEX_L2 << 6) | 943 (VEX_L << 5) | 944 (EVEX_b << 4) | 945 (EVEX_V2 << 3) | 946 EVEX_aaa, CurByte, OS); 947 } 948} 949 950/// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64 951/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand 952/// size, and 3) use of X86-64 extended registers. 953static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags, 954 const MCInstrDesc &Desc) { 955 unsigned REX = 0; 956 if (TSFlags & X86II::REX_W) 957 REX |= 1 << 3; // set REX.W 958 959 if (MI.getNumOperands() == 0) return REX; 960 961 unsigned NumOps = MI.getNumOperands(); 962 // FIXME: MCInst should explicitize the two-addrness. 963 bool isTwoAddr = NumOps > 1 && 964 Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1; 965 966 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix. 967 unsigned i = isTwoAddr ? 1 : 0; 968 for (; i != NumOps; ++i) { 969 const MCOperand &MO = MI.getOperand(i); 970 if (!MO.isReg()) continue; 971 unsigned Reg = MO.getReg(); 972 if (!X86II::isX86_64NonExtLowByteReg(Reg)) continue; 973 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything 974 // that returns non-zero. 975 REX |= 0x40; // REX fixed encoding prefix 976 break; 977 } 978 979 switch (TSFlags & X86II::FormMask) { 980 case X86II::MRMInitReg: llvm_unreachable("FIXME: Remove this!"); 981 case X86II::MRMSrcReg: 982 if (MI.getOperand(0).isReg() && 983 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) 984 REX |= 1 << 2; // set REX.R 985 i = isTwoAddr ? 2 : 1; 986 for (; i != NumOps; ++i) { 987 const MCOperand &MO = MI.getOperand(i); 988 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg())) 989 REX |= 1 << 0; // set REX.B 990 } 991 break; 992 case X86II::MRMSrcMem: { 993 if (MI.getOperand(0).isReg() && 994 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) 995 REX |= 1 << 2; // set REX.R 996 unsigned Bit = 0; 997 i = isTwoAddr ? 2 : 1; 998 for (; i != NumOps; ++i) { 999 const MCOperand &MO = MI.getOperand(i); 1000 if (MO.isReg()) { 1001 if (X86II::isX86_64ExtendedReg(MO.getReg())) 1002 REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1) 1003 Bit++; 1004 } 1005 } 1006 break; 1007 } 1008 case X86II::MRM0m: case X86II::MRM1m: 1009 case X86II::MRM2m: case X86II::MRM3m: 1010 case X86II::MRM4m: case X86II::MRM5m: 1011 case X86II::MRM6m: case X86II::MRM7m: 1012 case X86II::MRMDestMem: { 1013 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands); 1014 i = isTwoAddr ? 1 : 0; 1015 if (NumOps > e && MI.getOperand(e).isReg() && 1016 X86II::isX86_64ExtendedReg(MI.getOperand(e).getReg())) 1017 REX |= 1 << 2; // set REX.R 1018 unsigned Bit = 0; 1019 for (; i != e; ++i) { 1020 const MCOperand &MO = MI.getOperand(i); 1021 if (MO.isReg()) { 1022 if (X86II::isX86_64ExtendedReg(MO.getReg())) 1023 REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1) 1024 Bit++; 1025 } 1026 } 1027 break; 1028 } 1029 default: 1030 if (MI.getOperand(0).isReg() && 1031 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) 1032 REX |= 1 << 0; // set REX.B 1033 i = isTwoAddr ? 2 : 1; 1034 for (unsigned e = NumOps; i != e; ++i) { 1035 const MCOperand &MO = MI.getOperand(i); 1036 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg())) 1037 REX |= 1 << 2; // set REX.R 1038 } 1039 break; 1040 } 1041 return REX; 1042} 1043 1044/// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed 1045void X86MCCodeEmitter::EmitSegmentOverridePrefix(uint64_t TSFlags, 1046 unsigned &CurByte, int MemOperand, 1047 const MCInst &MI, 1048 raw_ostream &OS) const { 1049 switch (TSFlags & X86II::SegOvrMask) { 1050 default: llvm_unreachable("Invalid segment!"); 1051 case 0: 1052 // No segment override, check for explicit one on memory operand. 1053 if (MemOperand != -1) { // If the instruction has a memory operand. 1054 switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) { 1055 default: llvm_unreachable("Unknown segment register!"); 1056 case 0: break; 1057 case X86::CS: EmitByte(0x2E, CurByte, OS); break; 1058 case X86::SS: EmitByte(0x36, CurByte, OS); break; 1059 case X86::DS: EmitByte(0x3E, CurByte, OS); break; 1060 case X86::ES: EmitByte(0x26, CurByte, OS); break; 1061 case X86::FS: EmitByte(0x64, CurByte, OS); break; 1062 case X86::GS: EmitByte(0x65, CurByte, OS); break; 1063 } 1064 } 1065 break; 1066 case X86II::FS: 1067 EmitByte(0x64, CurByte, OS); 1068 break; 1069 case X86II::GS: 1070 EmitByte(0x65, CurByte, OS); 1071 break; 1072 } 1073} 1074 1075/// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode. 1076/// 1077/// MemOperand is the operand # of the start of a memory operand if present. If 1078/// Not present, it is -1. 1079void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, 1080 int MemOperand, const MCInst &MI, 1081 const MCInstrDesc &Desc, 1082 raw_ostream &OS) const { 1083 1084 // Emit the lock opcode prefix as needed. 1085 if (TSFlags & X86II::LOCK) 1086 EmitByte(0xF0, CurByte, OS); 1087 1088 // Emit segment override opcode prefix as needed. 1089 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS); 1090 1091 // Emit the repeat opcode prefix as needed. 1092 if ((TSFlags & X86II::Op0Mask) == X86II::REP) 1093 EmitByte(0xF3, CurByte, OS); 1094 1095 // Emit the address size opcode prefix as needed. 1096 bool need_address_override; 1097 if (TSFlags & X86II::AdSize) { 1098 need_address_override = true; 1099 } else if (MemOperand == -1) { 1100 need_address_override = false; 1101 } else if (is64BitMode()) { 1102 assert(!Is16BitMemOperand(MI, MemOperand)); 1103 need_address_override = Is32BitMemOperand(MI, MemOperand); 1104 } else if (is32BitMode()) { 1105 assert(!Is64BitMemOperand(MI, MemOperand)); 1106 need_address_override = Is16BitMemOperand(MI, MemOperand); 1107 } else { 1108 need_address_override = false; 1109 } 1110 1111 if (need_address_override) 1112 EmitByte(0x67, CurByte, OS); 1113 1114 // Emit the operand size opcode prefix as needed. 1115 if (TSFlags & X86II::OpSize) 1116 EmitByte(0x66, CurByte, OS); 1117 1118 bool Need0FPrefix = false; 1119 switch (TSFlags & X86II::Op0Mask) { 1120 default: llvm_unreachable("Invalid prefix!"); 1121 case 0: break; // No prefix! 1122 case X86II::REP: break; // already handled. 1123 case X86II::TB: // Two-byte opcode prefix 1124 case X86II::T8: // 0F 38 1125 case X86II::TA: // 0F 3A 1126 case X86II::A6: // 0F A6 1127 case X86II::A7: // 0F A7 1128 Need0FPrefix = true; 1129 break; 1130 case X86II::T8XS: // F3 0F 38 1131 EmitByte(0xF3, CurByte, OS); 1132 Need0FPrefix = true; 1133 break; 1134 case X86II::T8XD: // F2 0F 38 1135 EmitByte(0xF2, CurByte, OS); 1136 Need0FPrefix = true; 1137 break; 1138 case X86II::TAXD: // F2 0F 3A 1139 EmitByte(0xF2, CurByte, OS); 1140 Need0FPrefix = true; 1141 break; 1142 case X86II::XS: // F3 0F 1143 EmitByte(0xF3, CurByte, OS); 1144 Need0FPrefix = true; 1145 break; 1146 case X86II::XD: // F2 0F 1147 EmitByte(0xF2, CurByte, OS); 1148 Need0FPrefix = true; 1149 break; 1150 case X86II::D8: EmitByte(0xD8, CurByte, OS); break; 1151 case X86II::D9: EmitByte(0xD9, CurByte, OS); break; 1152 case X86II::DA: EmitByte(0xDA, CurByte, OS); break; 1153 case X86II::DB: EmitByte(0xDB, CurByte, OS); break; 1154 case X86II::DC: EmitByte(0xDC, CurByte, OS); break; 1155 case X86II::DD: EmitByte(0xDD, CurByte, OS); break; 1156 case X86II::DE: EmitByte(0xDE, CurByte, OS); break; 1157 case X86II::DF: EmitByte(0xDF, CurByte, OS); break; 1158 } 1159 1160 // Handle REX prefix. 1161 // FIXME: Can this come before F2 etc to simplify emission? 1162 if (is64BitMode()) { 1163 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc)) 1164 EmitByte(0x40 | REX, CurByte, OS); 1165 } 1166 1167 // 0x0F escape code must be emitted just before the opcode. 1168 if (Need0FPrefix) 1169 EmitByte(0x0F, CurByte, OS); 1170 1171 // FIXME: Pull this up into previous switch if REX can be moved earlier. 1172 switch (TSFlags & X86II::Op0Mask) { 1173 case X86II::T8XS: // F3 0F 38 1174 case X86II::T8XD: // F2 0F 38 1175 case X86II::T8: // 0F 38 1176 EmitByte(0x38, CurByte, OS); 1177 break; 1178 case X86II::TAXD: // F2 0F 3A 1179 case X86II::TA: // 0F 3A 1180 EmitByte(0x3A, CurByte, OS); 1181 break; 1182 case X86II::A6: // 0F A6 1183 EmitByte(0xA6, CurByte, OS); 1184 break; 1185 case X86II::A7: // 0F A7 1186 EmitByte(0xA7, CurByte, OS); 1187 break; 1188 } 1189} 1190 1191void X86MCCodeEmitter:: 1192EncodeInstruction(const MCInst &MI, raw_ostream &OS, 1193 SmallVectorImpl<MCFixup> &Fixups) const { 1194 unsigned Opcode = MI.getOpcode(); 1195 const MCInstrDesc &Desc = MCII.get(Opcode); 1196 uint64_t TSFlags = Desc.TSFlags; 1197 1198 // Pseudo instructions don't get encoded. 1199 if ((TSFlags & X86II::FormMask) == X86II::Pseudo) 1200 return; 1201 1202 unsigned NumOps = Desc.getNumOperands(); 1203 unsigned CurOp = X86II::getOperandBias(Desc); 1204 1205 // Keep track of the current byte being emitted. 1206 unsigned CurByte = 0; 1207 1208 // Is this instruction encoded using the AVX VEX prefix? 1209 bool HasVEXPrefix = (TSFlags >> X86II::VEXShift) & X86II::VEX; 1210 1211 // It uses the VEX.VVVV field? 1212 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V; 1213 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3; 1214 bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4; 1215 const unsigned MemOp4_I8IMMOperand = 2; 1216 1217 // It uses the EVEX.aaa field? 1218 bool HasEVEX = (TSFlags >> X86II::VEXShift) & X86II::EVEX; 1219 bool HasEVEX_K = HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_K); 1220 1221 // Determine where the memory operand starts, if present. 1222 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags, Opcode); 1223 if (MemoryOperand != -1) MemoryOperand += CurOp; 1224 1225 if (!HasVEXPrefix) 1226 EmitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS); 1227 else 1228 EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS); 1229 1230 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); 1231 1232 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode) 1233 BaseOpcode = 0x0F; // Weird 3DNow! encoding. 1234 1235 unsigned SrcRegNum = 0; 1236 switch (TSFlags & X86II::FormMask) { 1237 case X86II::MRMInitReg: 1238 llvm_unreachable("FIXME: Remove this form when the JIT moves to MCCodeEmitter!"); 1239 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n"; 1240 llvm_unreachable("Unknown FormMask value in X86MCCodeEmitter!"); 1241 case X86II::Pseudo: 1242 llvm_unreachable("Pseudo instruction shouldn't be emitted"); 1243 case X86II::RawFrm: 1244 EmitByte(BaseOpcode, CurByte, OS); 1245 break; 1246 case X86II::RawFrmImm8: 1247 EmitByte(BaseOpcode, CurByte, OS); 1248 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1249 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), 1250 CurByte, OS, Fixups); 1251 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1, FK_Data_1, CurByte, 1252 OS, Fixups); 1253 break; 1254 case X86II::RawFrmImm16: 1255 EmitByte(BaseOpcode, CurByte, OS); 1256 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1257 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), 1258 CurByte, OS, Fixups); 1259 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 2, FK_Data_2, CurByte, 1260 OS, Fixups); 1261 break; 1262 1263 case X86II::AddRegFrm: 1264 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS); 1265 break; 1266 1267 case X86II::MRMDestReg: 1268 EmitByte(BaseOpcode, CurByte, OS); 1269 SrcRegNum = CurOp + 1; 1270 1271 if (HasEVEX_K) // Skip writemask 1272 SrcRegNum++; 1273 1274 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1275 ++SrcRegNum; 1276 1277 EmitRegModRMByte(MI.getOperand(CurOp), 1278 GetX86RegNum(MI.getOperand(SrcRegNum)), CurByte, OS); 1279 CurOp = SrcRegNum + 1; 1280 break; 1281 1282 case X86II::MRMDestMem: 1283 EmitByte(BaseOpcode, CurByte, OS); 1284 SrcRegNum = CurOp + X86::AddrNumOperands; 1285 1286 if (HasEVEX_K) // Skip writemask 1287 SrcRegNum++; 1288 1289 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1290 ++SrcRegNum; 1291 1292 EmitMemModRMByte(MI, CurOp, 1293 GetX86RegNum(MI.getOperand(SrcRegNum)), 1294 TSFlags, CurByte, OS, Fixups); 1295 CurOp = SrcRegNum + 1; 1296 break; 1297 1298 case X86II::MRMSrcReg: 1299 EmitByte(BaseOpcode, CurByte, OS); 1300 SrcRegNum = CurOp + 1; 1301 1302 if (HasEVEX_K) // Skip writemask 1303 SrcRegNum++; 1304 1305 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1306 ++SrcRegNum; 1307 1308 if (HasMemOp4) // Skip 2nd src (which is encoded in I8IMM) 1309 ++SrcRegNum; 1310 1311 EmitRegModRMByte(MI.getOperand(SrcRegNum), 1312 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS); 1313 1314 // 2 operands skipped with HasMemOp4, compensate accordingly 1315 CurOp = HasMemOp4 ? SrcRegNum : SrcRegNum + 1; 1316 if (HasVEX_4VOp3) 1317 ++CurOp; 1318 break; 1319 1320 case X86II::MRMSrcMem: { 1321 int AddrOperands = X86::AddrNumOperands; 1322 unsigned FirstMemOp = CurOp+1; 1323 1324 if (HasEVEX_K) { // Skip writemask 1325 ++AddrOperands; 1326 ++FirstMemOp; 1327 } 1328 1329 if (HasVEX_4V) { 1330 ++AddrOperands; 1331 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV). 1332 } 1333 if (HasMemOp4) // Skip second register source (encoded in I8IMM) 1334 ++FirstMemOp; 1335 1336 EmitByte(BaseOpcode, CurByte, OS); 1337 1338 EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)), 1339 TSFlags, CurByte, OS, Fixups); 1340 CurOp += AddrOperands + 1; 1341 if (HasVEX_4VOp3) 1342 ++CurOp; 1343 break; 1344 } 1345 1346 case X86II::MRM0r: case X86II::MRM1r: 1347 case X86II::MRM2r: case X86II::MRM3r: 1348 case X86II::MRM4r: case X86II::MRM5r: 1349 case X86II::MRM6r: case X86II::MRM7r: 1350 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV). 1351 ++CurOp; 1352 EmitByte(BaseOpcode, CurByte, OS); 1353 EmitRegModRMByte(MI.getOperand(CurOp++), 1354 (TSFlags & X86II::FormMask)-X86II::MRM0r, 1355 CurByte, OS); 1356 break; 1357 case X86II::MRM0m: case X86II::MRM1m: 1358 case X86II::MRM2m: case X86II::MRM3m: 1359 case X86II::MRM4m: case X86II::MRM5m: 1360 case X86II::MRM6m: case X86II::MRM7m: 1361 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV). 1362 ++CurOp; 1363 EmitByte(BaseOpcode, CurByte, OS); 1364 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m, 1365 TSFlags, CurByte, OS, Fixups); 1366 CurOp += X86::AddrNumOperands; 1367 break; 1368 case X86II::MRM_C1: case X86II::MRM_C2: case X86II::MRM_C3: 1369 case X86II::MRM_C4: case X86II::MRM_C8: case X86II::MRM_C9: 1370 case X86II::MRM_CA: case X86II::MRM_CB: case X86II::MRM_D0: 1371 case X86II::MRM_D1: case X86II::MRM_D4: case X86II::MRM_D5: 1372 case X86II::MRM_D6: case X86II::MRM_D8: case X86II::MRM_D9: 1373 case X86II::MRM_DA: case X86II::MRM_DB: case X86II::MRM_DC: 1374 case X86II::MRM_DD: case X86II::MRM_DE: case X86II::MRM_DF: 1375 case X86II::MRM_E8: case X86II::MRM_F0: case X86II::MRM_F8: 1376 case X86II::MRM_F9: 1377 EmitByte(BaseOpcode, CurByte, OS); 1378 1379 unsigned char MRM; 1380 switch (TSFlags & X86II::FormMask) { 1381 default: llvm_unreachable("Invalid Form"); 1382 case X86II::MRM_C1: MRM = 0xC1; break; 1383 case X86II::MRM_C2: MRM = 0xC2; break; 1384 case X86II::MRM_C3: MRM = 0xC3; break; 1385 case X86II::MRM_C4: MRM = 0xC4; break; 1386 case X86II::MRM_C8: MRM = 0xC8; break; 1387 case X86II::MRM_C9: MRM = 0xC9; break; 1388 case X86II::MRM_CA: MRM = 0xCA; break; 1389 case X86II::MRM_CB: MRM = 0xCB; break; 1390 case X86II::MRM_D0: MRM = 0xD0; break; 1391 case X86II::MRM_D1: MRM = 0xD1; break; 1392 case X86II::MRM_D4: MRM = 0xD4; break; 1393 case X86II::MRM_D5: MRM = 0xD5; break; 1394 case X86II::MRM_D6: MRM = 0xD6; break; 1395 case X86II::MRM_D8: MRM = 0xD8; break; 1396 case X86II::MRM_D9: MRM = 0xD9; break; 1397 case X86II::MRM_DA: MRM = 0xDA; break; 1398 case X86II::MRM_DB: MRM = 0xDB; break; 1399 case X86II::MRM_DC: MRM = 0xDC; break; 1400 case X86II::MRM_DD: MRM = 0xDD; break; 1401 case X86II::MRM_DE: MRM = 0xDE; break; 1402 case X86II::MRM_DF: MRM = 0xDF; break; 1403 case X86II::MRM_E8: MRM = 0xE8; break; 1404 case X86II::MRM_F0: MRM = 0xF0; break; 1405 case X86II::MRM_F8: MRM = 0xF8; break; 1406 case X86II::MRM_F9: MRM = 0xF9; break; 1407 } 1408 EmitByte(MRM, CurByte, OS); 1409 break; 1410 } 1411 1412 // If there is a remaining operand, it must be a trailing immediate. Emit it 1413 // according to the right size for the instruction. Some instructions 1414 // (SSE4a extrq and insertq) have two trailing immediates. 1415 while (CurOp != NumOps && NumOps - CurOp <= 2) { 1416 // The last source register of a 4 operand instruction in AVX is encoded 1417 // in bits[7:4] of a immediate byte. 1418 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) { 1419 const MCOperand &MO = MI.getOperand(HasMemOp4 ? MemOp4_I8IMMOperand 1420 : CurOp); 1421 ++CurOp; 1422 unsigned RegNum = GetX86RegNum(MO) << 4; 1423 if (X86II::isX86_64ExtendedReg(MO.getReg())) 1424 RegNum |= 1 << 7; 1425 // If there is an additional 5th operand it must be an immediate, which 1426 // is encoded in bits[3:0] 1427 if (CurOp != NumOps) { 1428 const MCOperand &MIMM = MI.getOperand(CurOp++); 1429 if (MIMM.isImm()) { 1430 unsigned Val = MIMM.getImm(); 1431 assert(Val < 16 && "Immediate operand value out of range"); 1432 RegNum |= Val; 1433 } 1434 } 1435 EmitImmediate(MCOperand::CreateImm(RegNum), MI.getLoc(), 1, FK_Data_1, 1436 CurByte, OS, Fixups); 1437 } else { 1438 unsigned FixupKind; 1439 // FIXME: Is there a better way to know that we need a signed relocation? 1440 if (MI.getOpcode() == X86::ADD64ri32 || 1441 MI.getOpcode() == X86::MOV64ri32 || 1442 MI.getOpcode() == X86::MOV64mi32 || 1443 MI.getOpcode() == X86::PUSH64i32) 1444 FixupKind = X86::reloc_signed_4byte; 1445 else 1446 FixupKind = getImmFixupKind(TSFlags); 1447 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1448 X86II::getSizeOfImm(TSFlags), MCFixupKind(FixupKind), 1449 CurByte, OS, Fixups); 1450 } 1451 } 1452 1453 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode) 1454 EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS); 1455 1456#ifndef NDEBUG 1457 // FIXME: Verify. 1458 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) { 1459 errs() << "Cannot encode all operands of: "; 1460 MI.dump(); 1461 errs() << '\n'; 1462 abort(); 1463 } 1464#endif 1465} 1466