X86CodeEmitter.cpp revision 85bb54f96421461aaafcde83b6302530179337e9 
1//===-- X86/X86CodeEmitter.cpp - Convert X86 code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the X86 machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "x86-emitter"
16#include "X86InstrInfo.h"
17#include "X86JITInfo.h"
18#include "X86Subtarget.h"
19#include "X86TargetMachine.h"
20#include "X86Relocations.h"
21#include "X86.h"
22#include "llvm/LLVMContext.h"
23#include "llvm/PassManager.h"
24#include "llvm/CodeGen/JITCodeEmitter.h"
25#include "llvm/CodeGen/MachineFunctionPass.h"
26#include "llvm/CodeGen/MachineInstr.h"
27#include "llvm/CodeGen/MachineModuleInfo.h"
28#include "llvm/CodeGen/Passes.h"
29#include "llvm/Function.h"
30#include "llvm/ADT/Statistic.h"
31#include "llvm/MC/MCCodeEmitter.h"
32#include "llvm/MC/MCExpr.h"
33#include "llvm/MC/MCInst.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Support/ErrorHandling.h"
36#include "llvm/Support/raw_ostream.h"
37#include "llvm/Target/TargetOptions.h"
38using namespace llvm;
39
40STATISTIC(NumEmitted, "Number of machine instructions emitted");
41
42namespace {
43  template<class CodeEmitter>
44  class Emitter : public MachineFunctionPass {
45    const X86InstrInfo  *II;
46    const TargetData    *TD;
47    X86TargetMachine    &TM;
48    CodeEmitter         &MCE;
49    intptr_t PICBaseOffset;
50    bool Is64BitMode;
51    bool IsPIC;
52  public:
53    static char ID;
54    explicit Emitter(X86TargetMachine &tm, CodeEmitter &mce)
55      : MachineFunctionPass(&ID), II(0), TD(0), TM(tm),
56      MCE(mce), PICBaseOffset(0), Is64BitMode(false),
57      IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
58    Emitter(X86TargetMachine &tm, CodeEmitter &mce,
59            const X86InstrInfo &ii, const TargetData &td, bool is64)
60      : MachineFunctionPass(&ID), II(&ii), TD(&td), TM(tm),
61      MCE(mce), PICBaseOffset(0), Is64BitMode(is64),
62      IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
63
64    bool runOnMachineFunction(MachineFunction &MF);
65
66    virtual const char *getPassName() const {
67      return "X86 Machine Code Emitter";
68    }
69
70    void emitInstruction(const MachineInstr &MI,
71                         const TargetInstrDesc *Desc);
72
73    void getAnalysisUsage(AnalysisUsage &AU) const {
74      AU.setPreservesAll();
75      AU.addRequired<MachineModuleInfo>();
76      MachineFunctionPass::getAnalysisUsage(AU);
77    }
78
79  private:
80    void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
81    void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
82                           intptr_t Disp = 0, intptr_t PCAdj = 0,
83                           bool Indirect = false);
84    void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
85    void emitConstPoolAddress(unsigned CPI, unsigned Reloc, intptr_t Disp = 0,
86                              intptr_t PCAdj = 0);
87    void emitJumpTableAddress(unsigned JTI, unsigned Reloc,
88                              intptr_t PCAdj = 0);
89
90    void emitDisplacementField(const MachineOperand *RelocOp, int DispVal,
91                               intptr_t Adj = 0, bool IsPCRel = true);
92
93    void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
94    void emitRegModRMByte(unsigned RegOpcodeField);
95    void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
96    void emitConstant(uint64_t Val, unsigned Size);
97
98    void emitMemModRMByte(const MachineInstr &MI,
99                          unsigned Op, unsigned RegOpcodeField,
100                          intptr_t PCAdj = 0);
101
102    unsigned getX86RegNum(unsigned RegNo) const;
103  };
104
105template<class CodeEmitter>
106  char Emitter<CodeEmitter>::ID = 0;
107} // end anonymous namespace.
108
109/// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
110/// to the specified templated MachineCodeEmitter object.
111FunctionPass *llvm::createX86JITCodeEmitterPass(X86TargetMachine &TM,
112                                                JITCodeEmitter &JCE) {
113  return new Emitter<JITCodeEmitter>(TM, JCE);
114}
115
116template<class CodeEmitter>
117bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
118
119  MCE.setModuleInfo(&getAnalysis<MachineModuleInfo>());
120
121  II = TM.getInstrInfo();
122  TD = TM.getTargetData();
123  Is64BitMode = TM.getSubtarget<X86Subtarget>().is64Bit();
124  IsPIC = TM.getRelocationModel() == Reloc::PIC_;
125
126  do {
127    DEBUG(dbgs() << "JITTing function '"
128          << MF.getFunction()->getName() << "'\n");
129    MCE.startFunction(MF);
130    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
131         MBB != E; ++MBB) {
132      MCE.StartMachineBasicBlock(MBB);
133      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
134           I != E; ++I) {
135        const TargetInstrDesc &Desc = I->getDesc();
136        emitInstruction(*I, &Desc);
137        // MOVPC32r is basically a call plus a pop instruction.
138        if (Desc.getOpcode() == X86::MOVPC32r)
139          emitInstruction(*I, &II->get(X86::POP32r));
140        NumEmitted++;  // Keep track of the # of mi's emitted
141      }
142    }
143  } while (MCE.finishFunction(MF));
144
145  return false;
146}
147
148/// emitPCRelativeBlockAddress - This method keeps track of the information
149/// necessary to resolve the address of this block later and emits a dummy
150/// value.
151///
152template<class CodeEmitter>
153void Emitter<CodeEmitter>::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) {
154  // Remember where this reference was and where it is to so we can
155  // deal with it later.
156  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
157                                             X86::reloc_pcrel_word, MBB));
158  MCE.emitWordLE(0);
159}
160
161/// emitGlobalAddress - Emit the specified address to the code stream assuming
162/// this is part of a "take the address of a global" instruction.
163///
164template<class CodeEmitter>
165void Emitter<CodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
166                                intptr_t Disp /* = 0 */,
167                                intptr_t PCAdj /* = 0 */,
168                                bool Indirect /* = false */) {
169  intptr_t RelocCST = Disp;
170  if (Reloc == X86::reloc_picrel_word)
171    RelocCST = PICBaseOffset;
172  else if (Reloc == X86::reloc_pcrel_word)
173    RelocCST = PCAdj;
174  MachineRelocation MR = Indirect
175    ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
176                                           GV, RelocCST, false)
177    : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
178                               GV, RelocCST, false);
179  MCE.addRelocation(MR);
180  // The relocated value will be added to the displacement
181  if (Reloc == X86::reloc_absolute_dword)
182    MCE.emitDWordLE(Disp);
183  else
184    MCE.emitWordLE((int32_t)Disp);
185}
186
187/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
188/// be emitted to the current location in the function, and allow it to be PC
189/// relative.
190template<class CodeEmitter>
191void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES,
192                                                     unsigned Reloc) {
193  intptr_t RelocCST = (Reloc == X86::reloc_picrel_word) ? PICBaseOffset : 0;
194
195  // X86 never needs stubs because instruction selection will always pick
196  // an instruction sequence that is large enough to hold any address
197  // to a symbol.
198  // (see X86ISelLowering.cpp, near 2039: X86TargetLowering::LowerCall)
199  bool NeedStub = false;
200  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
201                                                 Reloc, ES, RelocCST,
202                                                 0, NeedStub));
203  if (Reloc == X86::reloc_absolute_dword)
204    MCE.emitDWordLE(0);
205  else
206    MCE.emitWordLE(0);
207}
208
209/// emitConstPoolAddress - Arrange for the address of an constant pool
210/// to be emitted to the current location in the function, and allow it to be PC
211/// relative.
212template<class CodeEmitter>
213void Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
214                                   intptr_t Disp /* = 0 */,
215                                   intptr_t PCAdj /* = 0 */) {
216  intptr_t RelocCST = 0;
217  if (Reloc == X86::reloc_picrel_word)
218    RelocCST = PICBaseOffset;
219  else if (Reloc == X86::reloc_pcrel_word)
220    RelocCST = PCAdj;
221  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
222                                                    Reloc, CPI, RelocCST));
223  // The relocated value will be added to the displacement
224  if (Reloc == X86::reloc_absolute_dword)
225    MCE.emitDWordLE(Disp);
226  else
227    MCE.emitWordLE((int32_t)Disp);
228}
229
230/// emitJumpTableAddress - Arrange for the address of a jump table to
231/// be emitted to the current location in the function, and allow it to be PC
232/// relative.
233template<class CodeEmitter>
234void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
235                                   intptr_t PCAdj /* = 0 */) {
236  intptr_t RelocCST = 0;
237  if (Reloc == X86::reloc_picrel_word)
238    RelocCST = PICBaseOffset;
239  else if (Reloc == X86::reloc_pcrel_word)
240    RelocCST = PCAdj;
241  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
242                                                    Reloc, JTI, RelocCST));
243  // The relocated value will be added to the displacement
244  if (Reloc == X86::reloc_absolute_dword)
245    MCE.emitDWordLE(0);
246  else
247    MCE.emitWordLE(0);
248}
249
250template<class CodeEmitter>
251unsigned Emitter<CodeEmitter>::getX86RegNum(unsigned RegNo) const {
252  return II->getRegisterInfo().getX86RegNum(RegNo);
253}
254
255inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
256                                      unsigned RM) {
257  assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
258  return RM | (RegOpcode << 3) | (Mod << 6);
259}
260
261template<class CodeEmitter>
262void Emitter<CodeEmitter>::emitRegModRMByte(unsigned ModRMReg,
263                                            unsigned RegOpcodeFld){
264  MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
265}
266
267template<class CodeEmitter>
268void Emitter<CodeEmitter>::emitRegModRMByte(unsigned RegOpcodeFld) {
269  MCE.emitByte(ModRMByte(3, RegOpcodeFld, 0));
270}
271
272template<class CodeEmitter>
273void Emitter<CodeEmitter>::emitSIBByte(unsigned SS,
274                                       unsigned Index,
275                                       unsigned Base) {
276  // SIB byte is in the same format as the ModRMByte...
277  MCE.emitByte(ModRMByte(SS, Index, Base));
278}
279
280template<class CodeEmitter>
281void Emitter<CodeEmitter>::emitConstant(uint64_t Val, unsigned Size) {
282  // Output the constant in little endian byte order...
283  for (unsigned i = 0; i != Size; ++i) {
284    MCE.emitByte(Val & 255);
285    Val >>= 8;
286  }
287}
288
289/// isDisp8 - Return true if this signed displacement fits in a 8-bit
290/// sign-extended field.
291static bool isDisp8(int Value) {
292  return Value == (signed char)Value;
293}
294
295static bool gvNeedsNonLazyPtr(const MachineOperand &GVOp,
296                              const TargetMachine &TM) {
297  // For Darwin-64, simulate the linktime GOT by using the same non-lazy-pointer
298  // mechanism as 32-bit mode.
299  if (TM.getSubtarget<X86Subtarget>().is64Bit() &&
300      !TM.getSubtarget<X86Subtarget>().isTargetDarwin())
301    return false;
302
303  // Return true if this is a reference to a stub containing the address of the
304  // global, not the global itself.
305  return isGlobalStubReference(GVOp.getTargetFlags());
306}
307
308template<class CodeEmitter>
309void Emitter<CodeEmitter>::emitDisplacementField(const MachineOperand *RelocOp,
310                                                 int DispVal,
311                                                 intptr_t Adj /* = 0 */,
312                                                 bool IsPCRel /* = true */) {
313  // If this is a simple integer displacement that doesn't require a relocation,
314  // emit it now.
315  if (!RelocOp) {
316    emitConstant(DispVal, 4);
317    return;
318  }
319
320  // Otherwise, this is something that requires a relocation.  Emit it as such
321  // now.
322  unsigned RelocType = Is64BitMode ?
323    (IsPCRel ? X86::reloc_pcrel_word : X86::reloc_absolute_word_sext)
324    : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
325  if (RelocOp->isGlobal()) {
326    // In 64-bit static small code model, we could potentially emit absolute.
327    // But it's probably not beneficial. If the MCE supports using RIP directly
328    // do it, otherwise fallback to absolute (this is determined by IsPCRel).
329    //  89 05 00 00 00 00     mov    %eax,0(%rip)  # PC-relative
330    //  89 04 25 00 00 00 00  mov    %eax,0x0      # Absolute
331    bool Indirect = gvNeedsNonLazyPtr(*RelocOp, TM);
332    emitGlobalAddress(RelocOp->getGlobal(), RelocType, RelocOp->getOffset(),
333                      Adj, Indirect);
334  } else if (RelocOp->isSymbol()) {
335    emitExternalSymbolAddress(RelocOp->getSymbolName(), RelocType);
336  } else if (RelocOp->isCPI()) {
337    emitConstPoolAddress(RelocOp->getIndex(), RelocType,
338                         RelocOp->getOffset(), Adj);
339  } else {
340    assert(RelocOp->isJTI() && "Unexpected machine operand!");
341    emitJumpTableAddress(RelocOp->getIndex(), RelocType, Adj);
342  }
343}
344
345template<class CodeEmitter>
346void Emitter<CodeEmitter>::emitMemModRMByte(const MachineInstr &MI,
347                                            unsigned Op,unsigned RegOpcodeField,
348                                            intptr_t PCAdj) {
349  const MachineOperand &Op3 = MI.getOperand(Op+3);
350  int DispVal = 0;
351  const MachineOperand *DispForReloc = 0;
352
353  // Figure out what sort of displacement we have to handle here.
354  if (Op3.isGlobal()) {
355    DispForReloc = &Op3;
356  } else if (Op3.isSymbol()) {
357    DispForReloc = &Op3;
358  } else if (Op3.isCPI()) {
359    if (!MCE.earlyResolveAddresses() || Is64BitMode || IsPIC) {
360      DispForReloc = &Op3;
361    } else {
362      DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex());
363      DispVal += Op3.getOffset();
364    }
365  } else if (Op3.isJTI()) {
366    if (!MCE.earlyResolveAddresses() || Is64BitMode || IsPIC) {
367      DispForReloc = &Op3;
368    } else {
369      DispVal += MCE.getJumpTableEntryAddress(Op3.getIndex());
370    }
371  } else {
372    DispVal = Op3.getImm();
373  }
374
375  const MachineOperand &Base     = MI.getOperand(Op);
376  const MachineOperand &Scale    = MI.getOperand(Op+1);
377  const MachineOperand &IndexReg = MI.getOperand(Op+2);
378
379  unsigned BaseReg = Base.getReg();
380
381  // Indicate that the displacement will use an pcrel or absolute reference
382  // by default. MCEs able to resolve addresses on-the-fly use pcrel by default
383  // while others, unless explicit asked to use RIP, use absolute references.
384  bool IsPCRel = MCE.earlyResolveAddresses() ? true : false;
385
386  // Is a SIB byte needed?
387  // If no BaseReg, issue a RIP relative instruction only if the MCE can
388  // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
389  // 2-7) and absolute references.
390  if ((!Is64BitMode || DispForReloc || BaseReg != 0) &&
391      IndexReg.getReg() == 0 &&
392      ((BaseReg == 0 && MCE.earlyResolveAddresses()) || BaseReg == X86::RIP ||
393       (BaseReg != 0 && getX86RegNum(BaseReg) != N86::ESP))) {
394    if (BaseReg == 0 || BaseReg == X86::RIP) {  // Just a displacement?
395      // Emit special case [disp32] encoding
396      MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
397      emitDisplacementField(DispForReloc, DispVal, PCAdj, true);
398    } else {
399      unsigned BaseRegNo = getX86RegNum(BaseReg);
400      if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
401        // Emit simple indirect register encoding... [EAX] f.e.
402        MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
403      } else if (!DispForReloc && isDisp8(DispVal)) {
404        // Emit the disp8 encoding... [REG+disp8]
405        MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
406        emitConstant(DispVal, 1);
407      } else {
408        // Emit the most general non-SIB encoding: [REG+disp32]
409        MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
410        emitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel);
411      }
412    }
413
414  } else {  // We need a SIB byte, so start by outputting the ModR/M byte first
415    assert(IndexReg.getReg() != X86::ESP &&
416           IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
417
418    bool ForceDisp32 = false;
419    bool ForceDisp8  = false;
420    if (BaseReg == 0) {
421      // If there is no base register, we emit the special case SIB byte with
422      // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
423      MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
424      ForceDisp32 = true;
425    } else if (DispForReloc) {
426      // Emit the normal disp32 encoding.
427      MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
428      ForceDisp32 = true;
429    } else if (DispVal == 0 && getX86RegNum(BaseReg) != N86::EBP) {
430      // Emit no displacement ModR/M byte
431      MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
432    } else if (isDisp8(DispVal)) {
433      // Emit the disp8 encoding...
434      MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
435      ForceDisp8 = true;           // Make sure to force 8 bit disp if Base=EBP
436    } else {
437      // Emit the normal disp32 encoding...
438      MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
439    }
440
441    // Calculate what the SS field value should be...
442    static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
443    unsigned SS = SSTable[Scale.getImm()];
444
445    if (BaseReg == 0) {
446      // Handle the SIB byte for the case where there is no base, see Intel
447      // Manual 2A, table 2-7. The displacement has already been output.
448      unsigned IndexRegNo;
449      if (IndexReg.getReg())
450        IndexRegNo = getX86RegNum(IndexReg.getReg());
451      else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
452        IndexRegNo = 4;
453      emitSIBByte(SS, IndexRegNo, 5);
454    } else {
455      unsigned BaseRegNo = getX86RegNum(BaseReg);
456      unsigned IndexRegNo;
457      if (IndexReg.getReg())
458        IndexRegNo = getX86RegNum(IndexReg.getReg());
459      else
460        IndexRegNo = 4;   // For example [ESP+1*<noreg>+4]
461      emitSIBByte(SS, IndexRegNo, BaseRegNo);
462    }
463
464    // Do we need to output a displacement?
465    if (ForceDisp8) {
466      emitConstant(DispVal, 1);
467    } else if (DispVal != 0 || ForceDisp32) {
468      emitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel);
469    }
470  }
471}
472
473template<class CodeEmitter>
474void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI,
475                                           const TargetInstrDesc *Desc) {
476  DEBUG(dbgs() << MI);
477
478  MCE.processDebugLoc(MI.getDebugLoc(), true);
479
480  unsigned Opcode = Desc->Opcode;
481
482  // Emit the lock opcode prefix as needed.
483  if (Desc->TSFlags & X86II::LOCK)
484    MCE.emitByte(0xF0);
485
486  // Emit segment override opcode prefix as needed.
487  switch (Desc->TSFlags & X86II::SegOvrMask) {
488  case X86II::FS:
489    MCE.emitByte(0x64);
490    break;
491  case X86II::GS:
492    MCE.emitByte(0x65);
493    break;
494  default: llvm_unreachable("Invalid segment!");
495  case 0: break;  // No segment override!
496  }
497
498  // Emit the repeat opcode prefix as needed.
499  if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP)
500    MCE.emitByte(0xF3);
501
502  // Emit the operand size opcode prefix as needed.
503  if (Desc->TSFlags & X86II::OpSize)
504    MCE.emitByte(0x66);
505
506  // Emit the address size opcode prefix as needed.
507  if (Desc->TSFlags & X86II::AdSize)
508    MCE.emitByte(0x67);
509
510  bool Need0FPrefix = false;
511  switch (Desc->TSFlags & X86II::Op0Mask) {
512  case X86II::TB:  // Two-byte opcode prefix
513  case X86II::T8:  // 0F 38
514  case X86II::TA:  // 0F 3A
515    Need0FPrefix = true;
516    break;
517  case X86II::TF: // F2 0F 38
518    MCE.emitByte(0xF2);
519    Need0FPrefix = true;
520    break;
521  case X86II::REP: break; // already handled.
522  case X86II::XS:   // F3 0F
523    MCE.emitByte(0xF3);
524    Need0FPrefix = true;
525    break;
526  case X86II::XD:   // F2 0F
527    MCE.emitByte(0xF2);
528    Need0FPrefix = true;
529    break;
530  case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
531  case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
532    MCE.emitByte(0xD8+
533                 (((Desc->TSFlags & X86II::Op0Mask)-X86II::D8)
534                                   >> X86II::Op0Shift));
535    break; // Two-byte opcode prefix
536  default: llvm_unreachable("Invalid prefix!");
537  case 0: break;  // No prefix!
538  }
539
540  // Handle REX prefix.
541  if (Is64BitMode) {
542    if (unsigned REX = X86InstrInfo::determineREX(MI))
543      MCE.emitByte(0x40 | REX);
544  }
545
546  // 0x0F escape code must be emitted just before the opcode.
547  if (Need0FPrefix)
548    MCE.emitByte(0x0F);
549
550  switch (Desc->TSFlags & X86II::Op0Mask) {
551  case X86II::TF:    // F2 0F 38
552  case X86II::T8:    // 0F 38
553    MCE.emitByte(0x38);
554    break;
555  case X86II::TA:    // 0F 3A
556    MCE.emitByte(0x3A);
557    break;
558  }
559
560  // If this is a two-address instruction, skip one of the register operands.
561  unsigned NumOps = Desc->getNumOperands();
562  unsigned CurOp = 0;
563  if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
564    ++CurOp;
565  else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
566    // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
567    --NumOps;
568
569  unsigned char BaseOpcode = X86InstrInfo::getBaseOpcodeFor(*Desc);
570  switch (Desc->TSFlags & X86II::FormMask) {
571  default:
572    llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
573  case X86II::Pseudo:
574    // Remember the current PC offset, this is the PIC relocation
575    // base address.
576    switch (Opcode) {
577    default:
578      llvm_unreachable("psuedo instructions should be removed before code"
579                       " emission");
580      break;
581    case TargetInstrInfo::INLINEASM:
582      // We allow inline assembler nodes with empty bodies - they can
583      // implicitly define registers, which is ok for JIT.
584      if (MI.getOperand(0).getSymbolName()[0])
585        llvm_report_error("JIT does not support inline asm!");
586      break;
587    case TargetInstrInfo::DBG_LABEL:
588    case TargetInstrInfo::EH_LABEL:
589    case TargetInstrInfo::GC_LABEL:
590      MCE.emitLabel(MI.getOperand(0).getImm());
591      break;
592    case TargetInstrInfo::IMPLICIT_DEF:
593    case TargetInstrInfo::KILL:
594    case X86::FP_REG_KILL:
595      break;
596    case X86::MOVPC32r: {
597      // This emits the "call" portion of this pseudo instruction.
598      MCE.emitByte(BaseOpcode);
599      emitConstant(0, X86InstrInfo::sizeOfImm(Desc));
600      // Remember PIC base.
601      PICBaseOffset = (intptr_t) MCE.getCurrentPCOffset();
602      X86JITInfo *JTI = TM.getJITInfo();
603      JTI->setPICBase(MCE.getCurrentPCValue());
604      break;
605    }
606    }
607    CurOp = NumOps;
608    break;
609  case X86II::RawFrm: {
610    MCE.emitByte(BaseOpcode);
611
612    if (CurOp == NumOps)
613      break;
614
615    const MachineOperand &MO = MI.getOperand(CurOp++);
616
617    DEBUG(dbgs() << "RawFrm CurOp " << CurOp << "\n");
618    DEBUG(dbgs() << "isMBB " << MO.isMBB() << "\n");
619    DEBUG(dbgs() << "isGlobal " << MO.isGlobal() << "\n");
620    DEBUG(dbgs() << "isSymbol " << MO.isSymbol() << "\n");
621    DEBUG(dbgs() << "isImm " << MO.isImm() << "\n");
622
623    if (MO.isMBB()) {
624      emitPCRelativeBlockAddress(MO.getMBB());
625      break;
626    }
627
628    if (MO.isGlobal()) {
629      emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word,
630                        MO.getOffset(), 0);
631      break;
632    }
633
634    if (MO.isSymbol()) {
635      emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
636      break;
637    }
638
639    assert(MO.isImm() && "Unknown RawFrm operand!");
640    if (Opcode == X86::CALLpcrel32 || Opcode == X86::CALL64pcrel32) {
641      // Fix up immediate operand for pc relative calls.
642      intptr_t Imm = (intptr_t)MO.getImm();
643      Imm = Imm - MCE.getCurrentPCValue() - 4;
644      emitConstant(Imm, X86InstrInfo::sizeOfImm(Desc));
645    } else
646      emitConstant(MO.getImm(), X86InstrInfo::sizeOfImm(Desc));
647    break;
648  }
649
650  case X86II::AddRegFrm: {
651    MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
652
653    if (CurOp == NumOps)
654      break;
655
656    const MachineOperand &MO1 = MI.getOperand(CurOp++);
657    unsigned Size = X86InstrInfo::sizeOfImm(Desc);
658    if (MO1.isImm()) {
659      emitConstant(MO1.getImm(), Size);
660      break;
661    }
662
663    unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
664      : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
665    if (Opcode == X86::MOV64ri64i32)
666      rt = X86::reloc_absolute_word;  // FIXME: add X86II flag?
667    // This should not occur on Darwin for relocatable objects.
668    if (Opcode == X86::MOV64ri)
669      rt = X86::reloc_absolute_dword;  // FIXME: add X86II flag?
670    if (MO1.isGlobal()) {
671      bool Indirect = gvNeedsNonLazyPtr(MO1, TM);
672      emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
673                        Indirect);
674    } else if (MO1.isSymbol())
675      emitExternalSymbolAddress(MO1.getSymbolName(), rt);
676    else if (MO1.isCPI())
677      emitConstPoolAddress(MO1.getIndex(), rt);
678    else if (MO1.isJTI())
679      emitJumpTableAddress(MO1.getIndex(), rt);
680    break;
681  }
682
683  case X86II::MRMDestReg: {
684    MCE.emitByte(BaseOpcode);
685    emitRegModRMByte(MI.getOperand(CurOp).getReg(),
686                     getX86RegNum(MI.getOperand(CurOp+1).getReg()));
687    CurOp += 2;
688    if (CurOp != NumOps)
689      emitConstant(MI.getOperand(CurOp++).getImm(),
690                   X86InstrInfo::sizeOfImm(Desc));
691    break;
692  }
693  case X86II::MRMDestMem: {
694    MCE.emitByte(BaseOpcode);
695    emitMemModRMByte(MI, CurOp,
696                     getX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands)
697                                  .getReg()));
698    CurOp +=  X86AddrNumOperands + 1;
699    if (CurOp != NumOps)
700      emitConstant(MI.getOperand(CurOp++).getImm(),
701                   X86InstrInfo::sizeOfImm(Desc));
702    break;
703  }
704
705  case X86II::MRMSrcReg:
706    MCE.emitByte(BaseOpcode);
707    emitRegModRMByte(MI.getOperand(CurOp+1).getReg(),
708                     getX86RegNum(MI.getOperand(CurOp).getReg()));
709    CurOp += 2;
710    if (CurOp != NumOps)
711      emitConstant(MI.getOperand(CurOp++).getImm(),
712                   X86InstrInfo::sizeOfImm(Desc));
713    break;
714
715  case X86II::MRMSrcMem: {
716    // FIXME: Maybe lea should have its own form?
717    int AddrOperands;
718    if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
719        Opcode == X86::LEA16r || Opcode == X86::LEA32r)
720      AddrOperands = X86AddrNumOperands - 1; // No segment register
721    else
722      AddrOperands = X86AddrNumOperands;
723
724    intptr_t PCAdj = (CurOp + AddrOperands + 1 != NumOps) ?
725      X86InstrInfo::sizeOfImm(Desc) : 0;
726
727    MCE.emitByte(BaseOpcode);
728    emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
729                     PCAdj);
730    CurOp += AddrOperands + 1;
731    if (CurOp != NumOps)
732      emitConstant(MI.getOperand(CurOp++).getImm(),
733                   X86InstrInfo::sizeOfImm(Desc));
734    break;
735  }
736
737  case X86II::MRM0r: case X86II::MRM1r:
738  case X86II::MRM2r: case X86II::MRM3r:
739  case X86II::MRM4r: case X86II::MRM5r:
740  case X86II::MRM6r: case X86II::MRM7r: {
741    MCE.emitByte(BaseOpcode);
742
743    // Special handling of lfence, mfence, monitor, and mwait.
744    if (Desc->getOpcode() == X86::LFENCE ||
745        Desc->getOpcode() == X86::MFENCE ||
746        Desc->getOpcode() == X86::MONITOR ||
747        Desc->getOpcode() == X86::MWAIT) {
748      emitRegModRMByte((Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
749
750      switch (Desc->getOpcode()) {
751      default: break;
752      case X86::MONITOR:
753        MCE.emitByte(0xC8);
754        break;
755      case X86::MWAIT:
756        MCE.emitByte(0xC9);
757        break;
758      }
759    } else {
760      emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
761                       (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
762    }
763
764    if (CurOp == NumOps)
765      break;
766
767    const MachineOperand &MO1 = MI.getOperand(CurOp++);
768    unsigned Size = X86InstrInfo::sizeOfImm(Desc);
769    if (MO1.isImm()) {
770      emitConstant(MO1.getImm(), Size);
771      break;
772    }
773
774    unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
775      : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
776    if (Opcode == X86::MOV64ri32)
777      rt = X86::reloc_absolute_word_sext;  // FIXME: add X86II flag?
778    if (MO1.isGlobal()) {
779      bool Indirect = gvNeedsNonLazyPtr(MO1, TM);
780      emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
781                        Indirect);
782    } else if (MO1.isSymbol())
783      emitExternalSymbolAddress(MO1.getSymbolName(), rt);
784    else if (MO1.isCPI())
785      emitConstPoolAddress(MO1.getIndex(), rt);
786    else if (MO1.isJTI())
787      emitJumpTableAddress(MO1.getIndex(), rt);
788    break;
789  }
790
791  case X86II::MRM0m: case X86II::MRM1m:
792  case X86II::MRM2m: case X86II::MRM3m:
793  case X86II::MRM4m: case X86II::MRM5m:
794  case X86II::MRM6m: case X86II::MRM7m: {
795    intptr_t PCAdj = (CurOp + X86AddrNumOperands != NumOps) ?
796      (MI.getOperand(CurOp+X86AddrNumOperands).isImm() ?
797          X86InstrInfo::sizeOfImm(Desc) : 4) : 0;
798
799    MCE.emitByte(BaseOpcode);
800    emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
801                     PCAdj);
802    CurOp += X86AddrNumOperands;
803
804    if (CurOp == NumOps)
805      break;
806
807    const MachineOperand &MO = MI.getOperand(CurOp++);
808    unsigned Size = X86InstrInfo::sizeOfImm(Desc);
809    if (MO.isImm()) {
810      emitConstant(MO.getImm(), Size);
811      break;
812    }
813
814    unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
815      : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
816    if (Opcode == X86::MOV64mi32)
817      rt = X86::reloc_absolute_word_sext;  // FIXME: add X86II flag?
818    if (MO.isGlobal()) {
819      bool Indirect = gvNeedsNonLazyPtr(MO, TM);
820      emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0,
821                        Indirect);
822    } else if (MO.isSymbol())
823      emitExternalSymbolAddress(MO.getSymbolName(), rt);
824    else if (MO.isCPI())
825      emitConstPoolAddress(MO.getIndex(), rt);
826    else if (MO.isJTI())
827      emitJumpTableAddress(MO.getIndex(), rt);
828    break;
829  }
830
831  case X86II::MRMInitReg:
832    MCE.emitByte(BaseOpcode);
833    // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
834    emitRegModRMByte(MI.getOperand(CurOp).getReg(),
835                     getX86RegNum(MI.getOperand(CurOp).getReg()));
836    ++CurOp;
837    break;
838  }
839
840  if (!Desc->isVariadic() && CurOp != NumOps) {
841#ifndef NDEBUG
842    dbgs() << "Cannot encode all operands of: " << MI << "\n";
843#endif
844    llvm_unreachable(0);
845  }
846
847  MCE.processDebugLoc(MI.getDebugLoc(), false);
848}
849
850// Adapt the Emitter / CodeEmitter interfaces to MCCodeEmitter.
851//
852// FIXME: This is a total hack designed to allow work on llvm-mc to proceed
853// without being blocked on various cleanups needed to support a clean interface
854// to instruction encoding.
855//
856// Look away!
857
858#include "llvm/DerivedTypes.h"
859
860namespace {
861class MCSingleInstructionCodeEmitter : public MachineCodeEmitter {
862  uint8_t Data[256];
863
864public:
865  MCSingleInstructionCodeEmitter() { reset(); }
866
867  void reset() {
868    BufferBegin = Data;
869    BufferEnd = array_endof(Data);
870    CurBufferPtr = Data;
871  }
872
873  StringRef str() {
874    return StringRef(reinterpret_cast<char*>(BufferBegin),
875                     CurBufferPtr - BufferBegin);
876  }
877
878  virtual void startFunction(MachineFunction &F) {}
879  virtual bool finishFunction(MachineFunction &F) { return false; }
880  virtual void emitLabel(uint64_t LabelID) {}
881  virtual void StartMachineBasicBlock(MachineBasicBlock *MBB) {}
882  virtual bool earlyResolveAddresses() const { return false; }
883  virtual void addRelocation(const MachineRelocation &MR) { }
884  virtual uintptr_t getConstantPoolEntryAddress(unsigned Index) const {
885    return 0;
886  }
887  virtual uintptr_t getJumpTableEntryAddress(unsigned Index) const {
888    return 0;
889  }
890  virtual uintptr_t getMachineBasicBlockAddress(MachineBasicBlock *MBB) const {
891    return 0;
892  }
893  virtual uintptr_t getLabelAddress(uint64_t LabelID) const {
894    return 0;
895  }
896  virtual void setModuleInfo(MachineModuleInfo* Info) {}
897};
898
899class X86MCCodeEmitter : public MCCodeEmitter {
900  X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
901  void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
902
903private:
904  X86TargetMachine &TM;
905  llvm::Function *DummyF;
906  TargetData *DummyTD;
907  mutable llvm::MachineFunction *DummyMF;
908  llvm::MachineBasicBlock *DummyMBB;
909
910  MCSingleInstructionCodeEmitter *InstrEmitter;
911  Emitter<MachineCodeEmitter> *Emit;
912
913public:
914  X86MCCodeEmitter(X86TargetMachine &_TM) : TM(_TM) {
915    // Verily, thou shouldst avert thine eyes.
916    const llvm::FunctionType *FTy =
917      FunctionType::get(llvm::Type::getVoidTy(getGlobalContext()), false);
918    DummyF = Function::Create(FTy, GlobalValue::InternalLinkage);
919    DummyTD = new TargetData("");
920    DummyMF = new MachineFunction(DummyF, TM, 0);
921    DummyMBB = DummyMF->CreateMachineBasicBlock();
922
923    InstrEmitter = new MCSingleInstructionCodeEmitter();
924    Emit = new Emitter<MachineCodeEmitter>(TM, *InstrEmitter,
925                                           *TM.getInstrInfo(),
926                                           *DummyTD, false);
927  }
928  ~X86MCCodeEmitter() {
929    delete Emit;
930    delete InstrEmitter;
931    delete DummyMF;
932    delete DummyF;
933  }
934
935  bool AddRegToInstr(const MCInst &MI, MachineInstr *Instr,
936                     unsigned Start) const {
937    if (Start + 1 > MI.getNumOperands())
938      return false;
939
940    const MCOperand &Op = MI.getOperand(Start);
941    if (!Op.isReg()) return false;
942
943    Instr->addOperand(MachineOperand::CreateReg(Op.getReg(), false));
944    return true;
945  }
946
947  bool AddImmToInstr(const MCInst &MI, MachineInstr *Instr,
948                     unsigned Start) const {
949    if (Start + 1 > MI.getNumOperands())
950      return false;
951
952    const MCOperand &Op = MI.getOperand(Start);
953    if (Op.isImm()) {
954      Instr->addOperand(MachineOperand::CreateImm(Op.getImm()));
955      return true;
956    }
957    if (!Op.isExpr())
958      return false;
959
960    const MCExpr *Expr = Op.getExpr();
961    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) {
962      Instr->addOperand(MachineOperand::CreateImm(CE->getValue()));
963      return true;
964    }
965
966    // FIXME: Relocation / fixup.
967    Instr->addOperand(MachineOperand::CreateImm(0));
968    return true;
969  }
970
971  bool AddLMemToInstr(const MCInst &MI, MachineInstr *Instr,
972                     unsigned Start) const {
973    return (AddRegToInstr(MI, Instr, Start + 0) &&
974            AddImmToInstr(MI, Instr, Start + 1) &&
975            AddRegToInstr(MI, Instr, Start + 2) &&
976            AddImmToInstr(MI, Instr, Start + 3));
977  }
978
979  bool AddMemToInstr(const MCInst &MI, MachineInstr *Instr,
980                     unsigned Start) const {
981    return (AddRegToInstr(MI, Instr, Start + 0) &&
982            AddImmToInstr(MI, Instr, Start + 1) &&
983            AddRegToInstr(MI, Instr, Start + 2) &&
984            AddImmToInstr(MI, Instr, Start + 3) &&
985            AddRegToInstr(MI, Instr, Start + 4));
986  }
987
988  void EncodeInstruction(const MCInst &MI, raw_ostream &OS) const {
989    // Don't look yet!
990
991    // Convert the MCInst to a MachineInstr so we can (ab)use the regular
992    // emitter.
993    const X86InstrInfo &II = *TM.getInstrInfo();
994    const TargetInstrDesc &Desc = II.get(MI.getOpcode());
995    MachineInstr *Instr = DummyMF->CreateMachineInstr(Desc, DebugLoc());
996    DummyMBB->push_back(Instr);
997
998    unsigned Opcode = MI.getOpcode();
999    unsigned NumOps = MI.getNumOperands();
1000    unsigned CurOp = 0;
1001    bool AddTied = false;
1002    if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1)
1003      AddTied = true;
1004    else if (NumOps > 2 &&
1005             Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
1006      // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
1007      --NumOps;
1008
1009    bool OK = true;
1010    switch (Desc.TSFlags & X86II::FormMask) {
1011    case X86II::MRMDestReg:
1012    case X86II::MRMSrcReg:
1013      // Matching doesn't fill this in completely, we have to choose operand 0
1014      // for a tied register.
1015      OK &= AddRegToInstr(MI, Instr, CurOp++);
1016      if (AddTied)
1017        OK &= AddRegToInstr(MI, Instr, CurOp++ - 1);
1018      OK &= AddRegToInstr(MI, Instr, CurOp++);
1019      if (CurOp < NumOps)
1020        OK &= AddImmToInstr(MI, Instr, CurOp);
1021      break;
1022
1023    case X86II::RawFrm:
1024      if (CurOp < NumOps) {
1025        // Hack to make branches work.
1026        if (!(Desc.TSFlags & X86II::ImmMask) &&
1027            MI.getOperand(0).isExpr() &&
1028            isa<MCSymbolRefExpr>(MI.getOperand(0).getExpr()))
1029          Instr->addOperand(MachineOperand::CreateMBB(DummyMBB));
1030        else
1031          OK &= AddImmToInstr(MI, Instr, CurOp);
1032      }
1033      break;
1034
1035    case X86II::AddRegFrm:
1036      // Matching doesn't fill this in completely, we have to choose operand 0
1037      // for a tied register.
1038      OK &= AddRegToInstr(MI, Instr, CurOp++);
1039      if (AddTied)
1040        OK &= AddRegToInstr(MI, Instr, CurOp++ - 1);
1041      if (CurOp < NumOps)
1042        OK &= AddImmToInstr(MI, Instr, CurOp);
1043      break;
1044
1045    case X86II::MRM0r: case X86II::MRM1r:
1046    case X86II::MRM2r: case X86II::MRM3r:
1047    case X86II::MRM4r: case X86II::MRM5r:
1048    case X86II::MRM6r: case X86II::MRM7r:
1049      // Matching doesn't fill this in completely, we have to choose operand 0
1050      // for a tied register.
1051      OK &= AddRegToInstr(MI, Instr, CurOp++);
1052      if (AddTied)
1053        OK &= AddRegToInstr(MI, Instr, CurOp++ - 1);
1054      if (CurOp < NumOps)
1055        OK &= AddImmToInstr(MI, Instr, CurOp);
1056      break;
1057
1058    case X86II::MRM0m: case X86II::MRM1m:
1059    case X86II::MRM2m: case X86II::MRM3m:
1060    case X86II::MRM4m: case X86II::MRM5m:
1061    case X86II::MRM6m: case X86II::MRM7m:
1062      OK &= AddMemToInstr(MI, Instr, CurOp); CurOp += 5;
1063      if (CurOp < NumOps)
1064        OK &= AddImmToInstr(MI, Instr, CurOp);
1065      break;
1066
1067    case X86II::MRMSrcMem:
1068      // Matching doesn't fill this in completely, we have to choose operand 0
1069      // for a tied register.
1070      OK &= AddRegToInstr(MI, Instr, CurOp++);
1071      if (AddTied)
1072        OK &= AddRegToInstr(MI, Instr, CurOp++ - 1);
1073      if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
1074          Opcode == X86::LEA16r || Opcode == X86::LEA32r)
1075        OK &= AddLMemToInstr(MI, Instr, CurOp);
1076      else
1077        OK &= AddMemToInstr(MI, Instr, CurOp);
1078      break;
1079
1080    case X86II::MRMDestMem:
1081      OK &= AddMemToInstr(MI, Instr, CurOp); CurOp += 5;
1082      OK &= AddRegToInstr(MI, Instr, CurOp);
1083      break;
1084
1085    default:
1086    case X86II::MRMInitReg:
1087    case X86II::Pseudo:
1088      OK = false;
1089      break;
1090    }
1091
1092    if (!OK) {
1093      dbgs() << "couldn't convert inst '";
1094      MI.dump();
1095      dbgs() << "' to machine instr:\n";
1096      Instr->dump();
1097    }
1098
1099    InstrEmitter->reset();
1100    if (OK)
1101      Emit->emitInstruction(*Instr, &Desc);
1102    OS << InstrEmitter->str();
1103
1104    Instr->eraseFromParent();
1105  }
1106};
1107}
1108
1109#include "llvm/Support/CommandLine.h"
1110
1111static cl::opt<bool> EnableNewEncoder("enable-new-x86-encoder",
1112                                      cl::ReallyHidden);
1113
1114
1115// Ok, now you can look.
1116MCCodeEmitter *llvm::createHeinousX86MCCodeEmitter(const Target &T,
1117                                                   TargetMachine &TM) {
1118
1119  // FIXME: Remove the heinous one when the new one works.
1120  if (EnableNewEncoder)
1121    return createX86MCCodeEmitter(T, TM);
1122
1123  return new X86MCCodeEmitter(static_cast<X86TargetMachine&>(TM));
1124}
1125