X86CodeEmitter.cpp revision d3f0aefc33965d3d0ca6f92af4ebaea354b063c4 
1//===-- X86/X86CodeEmitter.cpp - Convert X86 code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the X86 machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#include "X86TargetMachine.h"
16#include "X86Relocations.h"
17#include "X86.h"
18#include "llvm/PassManager.h"
19#include "llvm/CodeGen/MachineCodeEmitter.h"
20#include "llvm/CodeGen/MachineFunctionPass.h"
21#include "llvm/CodeGen/MachineInstr.h"
22#include "llvm/CodeGen/Passes.h"
23#include "llvm/Function.h"
24#include "llvm/ADT/Statistic.h"
25#include "llvm/Target/TargetOptions.h"
26#include <iostream>
27using namespace llvm;
28
29namespace {
30  Statistic<>
31  NumEmitted("x86-emitter", "Number of machine instructions emitted");
32}
33
34namespace {
35  class Emitter : public MachineFunctionPass {
36    const X86InstrInfo  *II;
37    MachineCodeEmitter  &MCE;
38    std::map<MachineBasicBlock*, uint64_t> BasicBlockAddrs;
39    std::vector<std::pair<MachineBasicBlock *, unsigned> > BBRefs;
40  public:
41    explicit Emitter(MachineCodeEmitter &mce) : II(0), MCE(mce) {}
42    Emitter(MachineCodeEmitter &mce, const X86InstrInfo& ii)
43        : II(&ii), MCE(mce) {}
44
45    bool runOnMachineFunction(MachineFunction &MF);
46
47    virtual const char *getPassName() const {
48      return "X86 Machine Code Emitter";
49    }
50
51    void emitInstruction(const MachineInstr &MI);
52
53  private:
54    void emitBasicBlock(MachineBasicBlock &MBB);
55    void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
56    void emitPCRelativeValue(unsigned Address);
57    void emitGlobalAddressForCall(GlobalValue *GV, bool isTailCall);
58    void emitGlobalAddressForPtr(GlobalValue *GV, int Disp = 0);
59    void emitExternalSymbolAddress(const char *ES, bool isPCRelative,
60                                   bool isTailCall);
61
62    void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
63    void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
64    void emitConstant(unsigned Val, unsigned Size);
65
66    void emitMemModRMByte(const MachineInstr &MI,
67                          unsigned Op, unsigned RegOpcodeField);
68
69  };
70}
71
72/// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
73/// to the specified MCE object.
74FunctionPass *llvm::createX86CodeEmitterPass(MachineCodeEmitter &MCE) {
75  return new Emitter(MCE);
76}
77
78bool Emitter::runOnMachineFunction(MachineFunction &MF) {
79  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
80          MF.getTarget().getRelocationModel() != Reloc::Static) &&
81         "JIT relocation model must be set to static or default!");
82  II = ((X86TargetMachine&)MF.getTarget()).getInstrInfo();
83
84  do {
85    BBRefs.clear();
86    BasicBlockAddrs.clear();
87
88    MCE.startFunction(MF);
89    MCE.emitConstantPool(MF.getConstantPool());
90    MCE.initJumpTableInfo(MF.getJumpTableInfo());
91    for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
92      emitBasicBlock(*I);
93    MCE.emitJumpTableInfo(MF.getJumpTableInfo(), BasicBlockAddrs);
94  } while (MCE.finishFunction(MF));
95
96  // Resolve all forward branches now.
97  for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) {
98    unsigned Location = BasicBlockAddrs[BBRefs[i].first];
99    unsigned Ref = BBRefs[i].second;
100    *((unsigned*)(intptr_t)Ref) = Location-Ref-4;
101  }
102  BBRefs.clear();
103  BasicBlockAddrs.clear();
104  return false;
105}
106
107void Emitter::emitBasicBlock(MachineBasicBlock &MBB) {
108  if (uint64_t Addr = MCE.getCurrentPCValue())
109    BasicBlockAddrs[&MBB] = Addr;
110
111  for (MachineBasicBlock::const_iterator I = MBB.begin(), E = MBB.end();
112       I != E; ++I)
113    emitInstruction(*I);
114}
115
116/// emitPCRelativeValue - Emit a 32-bit PC relative address.
117///
118void Emitter::emitPCRelativeValue(unsigned Address) {
119  MCE.emitWordLE(Address-MCE.getCurrentPCValue()-4);
120}
121
122/// emitPCRelativeBlockAddress - This method emits the PC relative address of
123/// the specified basic block, or if the basic block hasn't been emitted yet
124/// (because this is a forward branch), it keeps track of the information
125/// necessary to resolve this address later (and emits a dummy value).
126///
127void Emitter::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) {
128  // If this is a backwards branch, we already know the address of the target,
129  // so just emit the value.
130  std::map<MachineBasicBlock*,uint64_t>::iterator I = BasicBlockAddrs.find(MBB);
131  if (I != BasicBlockAddrs.end()) {
132    emitPCRelativeValue(I->second);
133  } else {
134    // Otherwise, remember where this reference was and where it is to so we can
135    // deal with it later.
136    BBRefs.push_back(std::make_pair(MBB, MCE.getCurrentPCValue()));
137    MCE.emitWordLE(0);
138  }
139}
140
141/// emitGlobalAddressForCall - Emit the specified address to the code stream
142/// assuming this is part of a function call, which is PC relative.
143///
144void Emitter::emitGlobalAddressForCall(GlobalValue *GV, bool isTailCall) {
145  MCE.addRelocation(MachineRelocation(MCE.getCurrentPCOffset(),
146                                      X86::reloc_pcrel_word, GV, 0,
147                                      !isTailCall /*Doesn'tNeedStub*/));
148  MCE.emitWordLE(0);
149}
150
151/// emitGlobalAddress - Emit the specified address to the code stream assuming
152/// this is part of a "take the address of a global" instruction, which is not
153/// PC relative.
154///
155void Emitter::emitGlobalAddressForPtr(GlobalValue *GV, int Disp /* = 0 */) {
156  MCE.addRelocation(MachineRelocation(MCE.getCurrentPCOffset(),
157                                      X86::reloc_absolute_word, GV));
158  MCE.emitWordLE(Disp); // The relocated value will be added to the displacement
159}
160
161/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
162/// be emitted to the current location in the function, and allow it to be PC
163/// relative.
164void Emitter::emitExternalSymbolAddress(const char *ES, bool isPCRelative,
165                                        bool isTailCall) {
166  MCE.addRelocation(MachineRelocation(MCE.getCurrentPCOffset(),
167          isPCRelative ? X86::reloc_pcrel_word : X86::reloc_absolute_word, ES));
168  MCE.emitWordLE(0);
169}
170
171/// N86 namespace - Native X86 Register numbers... used by X86 backend.
172///
173namespace N86 {
174  enum {
175    EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
176  };
177}
178
179
180// getX86RegNum - This function maps LLVM register identifiers to their X86
181// specific numbering, which is used in various places encoding instructions.
182//
183static unsigned getX86RegNum(unsigned RegNo) {
184  switch(RegNo) {
185  case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
186  case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
187  case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
188  case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
189  case X86::ESP: case X86::SP: case X86::AH: return N86::ESP;
190  case X86::EBP: case X86::BP: case X86::CH: return N86::EBP;
191  case X86::ESI: case X86::SI: case X86::DH: return N86::ESI;
192  case X86::EDI: case X86::DI: case X86::BH: return N86::EDI;
193
194  case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
195  case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
196    return RegNo-X86::ST0;
197
198  case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
199  case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7:
200    return RegNo-X86::XMM0;
201
202  default:
203    assert(MRegisterInfo::isVirtualRegister(RegNo) &&
204           "Unknown physical register!");
205    assert(0 && "Register allocator hasn't allocated reg correctly yet!");
206    return 0;
207  }
208}
209
210inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
211                                      unsigned RM) {
212  assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
213  return RM | (RegOpcode << 3) | (Mod << 6);
214}
215
216void Emitter::emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeFld){
217  MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
218}
219
220void Emitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base) {
221  // SIB byte is in the same format as the ModRMByte...
222  MCE.emitByte(ModRMByte(SS, Index, Base));
223}
224
225void Emitter::emitConstant(unsigned Val, unsigned Size) {
226  // Output the constant in little endian byte order...
227  for (unsigned i = 0; i != Size; ++i) {
228    MCE.emitByte(Val & 255);
229    Val >>= 8;
230  }
231}
232
233static bool isDisp8(int Value) {
234  return Value == (signed char)Value;
235}
236
237void Emitter::emitMemModRMByte(const MachineInstr &MI,
238                               unsigned Op, unsigned RegOpcodeField) {
239  const MachineOperand &Op3 = MI.getOperand(Op+3);
240  GlobalValue *GV = 0;
241  int DispVal = 0;
242
243  if (Op3.isGlobalAddress()) {
244    GV = Op3.getGlobal();
245    DispVal = Op3.getOffset();
246  } else if (Op3.isConstantPoolIndex()) {
247    DispVal += MCE.getConstantPoolEntryAddress(Op3.getConstantPoolIndex());
248    DispVal += Op3.getOffset();
249  } else if (Op3.isJumpTableIndex()) {
250    DispVal += MCE.getJumpTableEntryAddress(Op3.getJumpTableIndex());
251  } else {
252    DispVal = Op3.getImmedValue();
253  }
254
255  const MachineOperand &Base     = MI.getOperand(Op);
256  const MachineOperand &Scale    = MI.getOperand(Op+1);
257  const MachineOperand &IndexReg = MI.getOperand(Op+2);
258
259  unsigned BaseReg = Base.getReg();
260
261  // Is a SIB byte needed?
262  if (IndexReg.getReg() == 0 && BaseReg != X86::ESP) {
263    if (BaseReg == 0) {  // Just a displacement?
264      // Emit special case [disp32] encoding
265      MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
266      if (GV)
267        emitGlobalAddressForPtr(GV, DispVal);
268      else
269        emitConstant(DispVal, 4);
270    } else {
271      unsigned BaseRegNo = getX86RegNum(BaseReg);
272      if (GV) {
273        // Emit the most general non-SIB encoding: [REG+disp32]
274        MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
275        emitGlobalAddressForPtr(GV, DispVal);
276      } else if (DispVal == 0 && BaseRegNo != N86::EBP) {
277        // Emit simple indirect register encoding... [EAX] f.e.
278        MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
279      } else if (isDisp8(DispVal)) {
280        // Emit the disp8 encoding... [REG+disp8]
281        MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
282        emitConstant(DispVal, 1);
283      } else {
284        // Emit the most general non-SIB encoding: [REG+disp32]
285        MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
286        emitConstant(DispVal, 4);
287      }
288    }
289
290  } else {  // We need a SIB byte, so start by outputting the ModR/M byte first
291    assert(IndexReg.getReg() != X86::ESP && "Cannot use ESP as index reg!");
292
293    bool ForceDisp32 = false;
294    bool ForceDisp8  = false;
295    if (BaseReg == 0) {
296      // If there is no base register, we emit the special case SIB byte with
297      // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
298      MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
299      ForceDisp32 = true;
300    } else if (GV) {
301      // Emit the normal disp32 encoding...
302      MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
303      ForceDisp32 = true;
304    } else if (DispVal == 0 && BaseReg != X86::EBP) {
305      // Emit no displacement ModR/M byte
306      MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
307    } else if (isDisp8(DispVal)) {
308      // Emit the disp8 encoding...
309      MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
310      ForceDisp8 = true;           // Make sure to force 8 bit disp if Base=EBP
311    } else {
312      // Emit the normal disp32 encoding...
313      MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
314    }
315
316    // Calculate what the SS field value should be...
317    static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
318    unsigned SS = SSTable[Scale.getImmedValue()];
319
320    if (BaseReg == 0) {
321      // Handle the SIB byte for the case where there is no base.  The
322      // displacement has already been output.
323      assert(IndexReg.getReg() && "Index register must be specified!");
324      emitSIBByte(SS, getX86RegNum(IndexReg.getReg()), 5);
325    } else {
326      unsigned BaseRegNo = getX86RegNum(BaseReg);
327      unsigned IndexRegNo;
328      if (IndexReg.getReg())
329        IndexRegNo = getX86RegNum(IndexReg.getReg());
330      else
331        IndexRegNo = 4;   // For example [ESP+1*<noreg>+4]
332      emitSIBByte(SS, IndexRegNo, BaseRegNo);
333    }
334
335    // Do we need to output a displacement?
336    if (DispVal != 0 || ForceDisp32 || ForceDisp8) {
337      if (!ForceDisp32 && isDisp8(DispVal))
338        emitConstant(DispVal, 1);
339      else if (GV)
340        emitGlobalAddressForPtr(GV, DispVal);
341      else
342        emitConstant(DispVal, 4);
343    }
344  }
345}
346
347static unsigned sizeOfImm(const TargetInstrDescriptor &Desc) {
348  switch (Desc.TSFlags & X86II::ImmMask) {
349  case X86II::Imm8:   return 1;
350  case X86II::Imm16:  return 2;
351  case X86II::Imm32:  return 4;
352  default: assert(0 && "Immediate size not set!");
353    return 0;
354  }
355}
356
357void Emitter::emitInstruction(const MachineInstr &MI) {
358  NumEmitted++;  // Keep track of the # of mi's emitted
359
360  unsigned Opcode = MI.getOpcode();
361  const TargetInstrDescriptor &Desc = II->get(Opcode);
362
363  // Emit the repeat opcode prefix as needed.
364  if ((Desc.TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);
365
366  // Emit the operand size opcode prefix as needed.
367  if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);
368
369  switch (Desc.TSFlags & X86II::Op0Mask) {
370  case X86II::TB:
371    MCE.emitByte(0x0F);   // Two-byte opcode prefix
372    break;
373  case X86II::REP: break; // already handled.
374  case X86II::XS:   // F3 0F
375    MCE.emitByte(0xF3);
376    MCE.emitByte(0x0F);
377    break;
378  case X86II::XD:   // F2 0F
379    MCE.emitByte(0xF2);
380    MCE.emitByte(0x0F);
381    break;
382  case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
383  case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
384    MCE.emitByte(0xD8+
385                 (((Desc.TSFlags & X86II::Op0Mask)-X86II::D8)
386                                   >> X86II::Op0Shift));
387    break; // Two-byte opcode prefix
388  default: assert(0 && "Invalid prefix!");
389  case 0: break;  // No prefix!
390  }
391
392  unsigned char BaseOpcode = II->getBaseOpcodeFor(Opcode);
393  switch (Desc.TSFlags & X86II::FormMask) {
394  default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
395  case X86II::Pseudo:
396#ifndef NDEBUG
397    switch (Opcode) {
398    default:
399      assert(0 && "psuedo instructions should be removed before code emission");
400    case X86::IMPLICIT_USE:
401    case X86::IMPLICIT_DEF:
402    case X86::IMPLICIT_DEF_R8:
403    case X86::IMPLICIT_DEF_R16:
404    case X86::IMPLICIT_DEF_R32:
405    case X86::IMPLICIT_DEF_FR32:
406    case X86::IMPLICIT_DEF_FR64:
407    case X86::IMPLICIT_DEF_VR64:
408    case X86::IMPLICIT_DEF_VR128:
409    case X86::FP_REG_KILL:
410      break;
411    }
412#endif
413    break;
414
415  case X86II::RawFrm:
416    MCE.emitByte(BaseOpcode);
417    if (MI.getNumOperands() == 1) {
418      const MachineOperand &MO = MI.getOperand(0);
419      if (MO.isMachineBasicBlock()) {
420        emitPCRelativeBlockAddress(MO.getMachineBasicBlock());
421      } else if (MO.isGlobalAddress()) {
422        bool isTailCall = Opcode == X86::TAILJMPd ||
423                          Opcode == X86::TAILJMPr || Opcode == X86::TAILJMPm;
424        emitGlobalAddressForCall(MO.getGlobal(), isTailCall);
425      } else if (MO.isExternalSymbol()) {
426        bool isTailCall = Opcode == X86::TAILJMPd ||
427                          Opcode == X86::TAILJMPr || Opcode == X86::TAILJMPm;
428        emitExternalSymbolAddress(MO.getSymbolName(), true, isTailCall);
429      } else if (MO.isImmediate()) {
430        emitConstant(MO.getImmedValue(), sizeOfImm(Desc));
431      } else {
432        assert(0 && "Unknown RawFrm operand!");
433      }
434    }
435    break;
436
437  case X86II::AddRegFrm:
438    MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(0).getReg()));
439    if (MI.getNumOperands() == 2) {
440      const MachineOperand &MO1 = MI.getOperand(1);
441      if (Value *V = MO1.getVRegValueOrNull()) {
442        assert(sizeOfImm(Desc) == 4 &&
443               "Don't know how to emit non-pointer values!");
444        emitGlobalAddressForPtr(cast<GlobalValue>(V));
445      } else if (MO1.isGlobalAddress()) {
446        assert(sizeOfImm(Desc) == 4 &&
447               "Don't know how to emit non-pointer values!");
448        assert(!MO1.isPCRelative() && "Function pointer ref is PC relative?");
449        emitGlobalAddressForPtr(MO1.getGlobal(), MO1.getOffset());
450      } else if (MO1.isExternalSymbol()) {
451        assert(sizeOfImm(Desc) == 4 &&
452               "Don't know how to emit non-pointer values!");
453        emitExternalSymbolAddress(MO1.getSymbolName(), false, false);
454      } else if (MO1.isJumpTableIndex()) {
455        assert(sizeOfImm(Desc) == 4 &&
456               "Don't know how to emit non-pointer values!");
457        emitConstant(MCE.getJumpTableEntryAddress(MO1.getJumpTableIndex()), 4);
458      } else {
459        emitConstant(MO1.getImmedValue(), sizeOfImm(Desc));
460      }
461    }
462    break;
463
464  case X86II::MRMDestReg: {
465    MCE.emitByte(BaseOpcode);
466    emitRegModRMByte(MI.getOperand(0).getReg(),
467                     getX86RegNum(MI.getOperand(1).getReg()));
468    if (MI.getNumOperands() == 3)
469      emitConstant(MI.getOperand(2).getImmedValue(), sizeOfImm(Desc));
470    break;
471  }
472  case X86II::MRMDestMem:
473    MCE.emitByte(BaseOpcode);
474    emitMemModRMByte(MI, 0, getX86RegNum(MI.getOperand(4).getReg()));
475    if (MI.getNumOperands() == 6)
476      emitConstant(MI.getOperand(5).getImmedValue(), sizeOfImm(Desc));
477    break;
478
479  case X86II::MRMSrcReg:
480    MCE.emitByte(BaseOpcode);
481    emitRegModRMByte(MI.getOperand(1).getReg(),
482                     getX86RegNum(MI.getOperand(0).getReg()));
483    if (MI.getNumOperands() == 3)
484      emitConstant(MI.getOperand(2).getImmedValue(), sizeOfImm(Desc));
485    break;
486
487  case X86II::MRMSrcMem:
488    MCE.emitByte(BaseOpcode);
489    emitMemModRMByte(MI, 1, getX86RegNum(MI.getOperand(0).getReg()));
490    if (MI.getNumOperands() == 2+4)
491      emitConstant(MI.getOperand(5).getImmedValue(), sizeOfImm(Desc));
492    break;
493
494  case X86II::MRM0r: case X86II::MRM1r:
495  case X86II::MRM2r: case X86II::MRM3r:
496  case X86II::MRM4r: case X86II::MRM5r:
497  case X86II::MRM6r: case X86II::MRM7r:
498    MCE.emitByte(BaseOpcode);
499    emitRegModRMByte(MI.getOperand(0).getReg(),
500                     (Desc.TSFlags & X86II::FormMask)-X86II::MRM0r);
501
502    if (MI.getOperand(MI.getNumOperands()-1).isImmediate()) {
503      emitConstant(MI.getOperand(MI.getNumOperands()-1).getImmedValue(),
504                   sizeOfImm(Desc));
505    }
506    break;
507
508  case X86II::MRM0m: case X86II::MRM1m:
509  case X86II::MRM2m: case X86II::MRM3m:
510  case X86II::MRM4m: case X86II::MRM5m:
511  case X86II::MRM6m: case X86II::MRM7m:
512    MCE.emitByte(BaseOpcode);
513    emitMemModRMByte(MI, 0, (Desc.TSFlags & X86II::FormMask)-X86II::MRM0m);
514
515    if (MI.getNumOperands() == 5) {
516      if (MI.getOperand(4).isImmediate())
517        emitConstant(MI.getOperand(4).getImmedValue(), sizeOfImm(Desc));
518      else if (MI.getOperand(4).isGlobalAddress())
519        emitGlobalAddressForPtr(MI.getOperand(4).getGlobal(),
520                                MI.getOperand(4).getOffset());
521      else
522        assert(0 && "Unknown operand!");
523    }
524    break;
525
526  case X86II::MRMInitReg:
527    MCE.emitByte(BaseOpcode);
528    emitRegModRMByte(MI.getOperand(0).getReg(),
529                     getX86RegNum(MI.getOperand(0).getReg()));
530    break;
531  }
532}
533