X86CodeEmitter.cpp revision dabbc983966594a004b99c257fe2a776bef0bd18 
1//===-- X86/X86CodeEmitter.cpp - Convert X86 code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the X86 machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#include "X86TargetMachine.h"
16#include "X86Relocations.h"
17#include "X86.h"
18#include "llvm/PassManager.h"
19#include "llvm/CodeGen/MachineCodeEmitter.h"
20#include "llvm/CodeGen/MachineFunctionPass.h"
21#include "llvm/CodeGen/MachineInstr.h"
22#include "llvm/CodeGen/Passes.h"
23#include "llvm/Function.h"
24#include "llvm/ADT/Statistic.h"
25#include <iostream>
26using namespace llvm;
27
28namespace {
29  Statistic<>
30  NumEmitted("x86-emitter", "Number of machine instructions emitted");
31}
32
33namespace {
34  class Emitter : public MachineFunctionPass {
35    const X86InstrInfo  *II;
36    MachineCodeEmitter  &MCE;
37    std::map<const MachineBasicBlock*, unsigned> BasicBlockAddrs;
38    std::vector<std::pair<const MachineBasicBlock *, unsigned> > BBRefs;
39  public:
40    explicit Emitter(MachineCodeEmitter &mce) : II(0), MCE(mce) {}
41    Emitter(MachineCodeEmitter &mce, const X86InstrInfo& ii)
42        : II(&ii), MCE(mce) {}
43
44    bool runOnMachineFunction(MachineFunction &MF);
45
46    virtual const char *getPassName() const {
47      return "X86 Machine Code Emitter";
48    }
49
50    void emitInstruction(const MachineInstr &MI);
51
52  private:
53    void emitBasicBlock(const MachineBasicBlock &MBB);
54
55    void emitPCRelativeBlockAddress(const MachineBasicBlock *BB);
56    void emitPCRelativeValue(unsigned Address);
57    void emitGlobalAddressForCall(GlobalValue *GV, bool isTailCall);
58    void emitGlobalAddressForPtr(GlobalValue *GV, int Disp = 0);
59    void emitExternalSymbolAddress(const char *ES, bool isPCRelative,
60                                   bool isTailCall);
61
62    void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
63    void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
64    void emitConstant(unsigned Val, unsigned Size);
65
66    void emitMemModRMByte(const MachineInstr &MI,
67                          unsigned Op, unsigned RegOpcodeField);
68
69  };
70}
71
72/// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
73/// to the specified MCE object.
74FunctionPass *llvm::createX86CodeEmitterPass(MachineCodeEmitter &MCE) {
75  return new Emitter(MCE);
76}
77
78bool Emitter::runOnMachineFunction(MachineFunction &MF) {
79  II = ((X86TargetMachine&)MF.getTarget()).getInstrInfo();
80
81  MCE.startFunction(MF);
82  MCE.emitConstantPool(MF.getConstantPool());
83  for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
84    emitBasicBlock(*I);
85  MCE.finishFunction(MF);
86
87  // Resolve all forward branches now...
88  for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) {
89    unsigned Location = BasicBlockAddrs[BBRefs[i].first];
90    unsigned Ref = BBRefs[i].second;
91    MCE.emitWordAt(Location-Ref-4, (unsigned*)(intptr_t)Ref);
92  }
93  BBRefs.clear();
94  BasicBlockAddrs.clear();
95  return false;
96}
97
98void Emitter::emitBasicBlock(const MachineBasicBlock &MBB) {
99  if (uint64_t Addr = MCE.getCurrentPCValue())
100    BasicBlockAddrs[&MBB] = Addr;
101
102  for (MachineBasicBlock::const_iterator I = MBB.begin(), E = MBB.end();
103       I != E; ++I)
104    emitInstruction(*I);
105}
106
107/// emitPCRelativeValue - Emit a 32-bit PC relative address.
108///
109void Emitter::emitPCRelativeValue(unsigned Address) {
110  MCE.emitWord(Address-MCE.getCurrentPCValue()-4);
111}
112
113/// emitPCRelativeBlockAddress - This method emits the PC relative address of
114/// the specified basic block, or if the basic block hasn't been emitted yet
115/// (because this is a forward branch), it keeps track of the information
116/// necessary to resolve this address later (and emits a dummy value).
117///
118void Emitter::emitPCRelativeBlockAddress(const MachineBasicBlock *MBB) {
119  // If this is a backwards branch, we already know the address of the target,
120  // so just emit the value.
121  std::map<const MachineBasicBlock*, unsigned>::iterator I =
122    BasicBlockAddrs.find(MBB);
123  if (I != BasicBlockAddrs.end()) {
124    emitPCRelativeValue(I->second);
125  } else {
126    // Otherwise, remember where this reference was and where it is to so we can
127    // deal with it later.
128    BBRefs.push_back(std::make_pair(MBB, MCE.getCurrentPCValue()));
129    MCE.emitWord(0);
130  }
131}
132
133/// emitGlobalAddressForCall - Emit the specified address to the code stream
134/// assuming this is part of a function call, which is PC relative.
135///
136void Emitter::emitGlobalAddressForCall(GlobalValue *GV, bool isTailCall) {
137  MCE.addRelocation(MachineRelocation(MCE.getCurrentPCOffset(),
138                                      X86::reloc_pcrel_word, GV, 0,
139                                      !isTailCall /*Doesn'tNeedStub*/));
140  MCE.emitWord(0);
141}
142
143/// emitGlobalAddress - Emit the specified address to the code stream assuming
144/// this is part of a "take the address of a global" instruction, which is not
145/// PC relative.
146///
147void Emitter::emitGlobalAddressForPtr(GlobalValue *GV, int Disp /* = 0 */) {
148  MCE.addRelocation(MachineRelocation(MCE.getCurrentPCOffset(),
149                                      X86::reloc_absolute_word, GV));
150  MCE.emitWord(Disp);   // The relocated value will be added to the displacement
151}
152
153/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
154/// be emitted to the current location in the function, and allow it to be PC
155/// relative.
156void Emitter::emitExternalSymbolAddress(const char *ES, bool isPCRelative,
157                                        bool isTailCall) {
158  MCE.addRelocation(MachineRelocation(MCE.getCurrentPCOffset(),
159          isPCRelative ? X86::reloc_pcrel_word : X86::reloc_absolute_word, ES));
160  MCE.emitWord(0);
161}
162
163/// N86 namespace - Native X86 Register numbers... used by X86 backend.
164///
165namespace N86 {
166  enum {
167    EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
168  };
169}
170
171
172// getX86RegNum - This function maps LLVM register identifiers to their X86
173// specific numbering, which is used in various places encoding instructions.
174//
175static unsigned getX86RegNum(unsigned RegNo) {
176  switch(RegNo) {
177  case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
178  case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
179  case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
180  case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
181  case X86::ESP: case X86::SP: case X86::AH: return N86::ESP;
182  case X86::EBP: case X86::BP: case X86::CH: return N86::EBP;
183  case X86::ESI: case X86::SI: case X86::DH: return N86::ESI;
184  case X86::EDI: case X86::DI: case X86::BH: return N86::EDI;
185
186  case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
187  case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
188    return RegNo-X86::ST0;
189  default:
190    assert(MRegisterInfo::isVirtualRegister(RegNo) &&
191           "Unknown physical register!");
192    assert(0 && "Register allocator hasn't allocated reg correctly yet!");
193    return 0;
194  }
195}
196
197inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
198                                      unsigned RM) {
199  assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
200  return RM | (RegOpcode << 3) | (Mod << 6);
201}
202
203void Emitter::emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeFld){
204  MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
205}
206
207void Emitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base) {
208  // SIB byte is in the same format as the ModRMByte...
209  MCE.emitByte(ModRMByte(SS, Index, Base));
210}
211
212void Emitter::emitConstant(unsigned Val, unsigned Size) {
213  // Output the constant in little endian byte order...
214  for (unsigned i = 0; i != Size; ++i) {
215    MCE.emitByte(Val & 255);
216    Val >>= 8;
217  }
218}
219
220static bool isDisp8(int Value) {
221  return Value == (signed char)Value;
222}
223
224void Emitter::emitMemModRMByte(const MachineInstr &MI,
225                               unsigned Op, unsigned RegOpcodeField) {
226  const MachineOperand &Op3 = MI.getOperand(Op+3);
227  GlobalValue *GV = 0;
228  int DispVal = 0;
229
230  if (Op3.isGlobalAddress()) {
231    GV = Op3.getGlobal();
232    DispVal = Op3.getOffset();
233  } else {
234    DispVal = Op3.getImmedValue();
235  }
236
237  const MachineOperand &Base     = MI.getOperand(Op);
238  const MachineOperand &Scale    = MI.getOperand(Op+1);
239  const MachineOperand &IndexReg = MI.getOperand(Op+2);
240
241  unsigned BaseReg = 0;
242
243  if (Base.isConstantPoolIndex()) {
244    // Emit a direct address reference [disp32] where the displacement of the
245    // constant pool entry is controlled by the MCE.
246    assert(!GV && "Constant Pool reference cannot be relative to global!");
247    DispVal += MCE.getConstantPoolEntryAddress(Base.getConstantPoolIndex());
248  } else {
249    BaseReg = Base.getReg();
250  }
251
252  // Is a SIB byte needed?
253  if (IndexReg.getReg() == 0 && BaseReg != X86::ESP) {
254    if (BaseReg == 0) {  // Just a displacement?
255      // Emit special case [disp32] encoding
256      MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
257      if (GV)
258        emitGlobalAddressForPtr(GV, DispVal);
259      else
260        emitConstant(DispVal, 4);
261    } else {
262      unsigned BaseRegNo = getX86RegNum(BaseReg);
263      if (GV) {
264        // Emit the most general non-SIB encoding: [REG+disp32]
265        MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
266        emitGlobalAddressForPtr(GV, DispVal);
267      } else if (DispVal == 0 && BaseRegNo != N86::EBP) {
268        // Emit simple indirect register encoding... [EAX] f.e.
269        MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
270      } else if (isDisp8(DispVal)) {
271        // Emit the disp8 encoding... [REG+disp8]
272        MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
273        emitConstant(DispVal, 1);
274      } else {
275        // Emit the most general non-SIB encoding: [REG+disp32]
276        MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
277        emitConstant(DispVal, 4);
278      }
279    }
280
281  } else {  // We need a SIB byte, so start by outputting the ModR/M byte first
282    assert(IndexReg.getReg() != X86::ESP && "Cannot use ESP as index reg!");
283
284    bool ForceDisp32 = false;
285    bool ForceDisp8  = false;
286    if (BaseReg == 0) {
287      // If there is no base register, we emit the special case SIB byte with
288      // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
289      MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
290      ForceDisp32 = true;
291    } else if (GV) {
292      // Emit the normal disp32 encoding...
293      MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
294      ForceDisp32 = true;
295    } else if (DispVal == 0 && BaseReg != X86::EBP) {
296      // Emit no displacement ModR/M byte
297      MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
298    } else if (isDisp8(DispVal)) {
299      // Emit the disp8 encoding...
300      MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
301      ForceDisp8 = true;           // Make sure to force 8 bit disp if Base=EBP
302    } else {
303      // Emit the normal disp32 encoding...
304      MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
305    }
306
307    // Calculate what the SS field value should be...
308    static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
309    unsigned SS = SSTable[Scale.getImmedValue()];
310
311    if (BaseReg == 0) {
312      // Handle the SIB byte for the case where there is no base.  The
313      // displacement has already been output.
314      assert(IndexReg.getReg() && "Index register must be specified!");
315      emitSIBByte(SS, getX86RegNum(IndexReg.getReg()), 5);
316    } else {
317      unsigned BaseRegNo = getX86RegNum(BaseReg);
318      unsigned IndexRegNo;
319      if (IndexReg.getReg())
320        IndexRegNo = getX86RegNum(IndexReg.getReg());
321      else
322        IndexRegNo = 4;   // For example [ESP+1*<noreg>+4]
323      emitSIBByte(SS, IndexRegNo, BaseRegNo);
324    }
325
326    // Do we need to output a displacement?
327    if (DispVal != 0 || ForceDisp32 || ForceDisp8) {
328      if (!ForceDisp32 && isDisp8(DispVal))
329        emitConstant(DispVal, 1);
330      else if (GV)
331        emitGlobalAddressForPtr(GV, DispVal);
332      else
333        emitConstant(DispVal, 4);
334    }
335  }
336}
337
338static unsigned sizeOfImm(const TargetInstrDescriptor &Desc) {
339  switch (Desc.TSFlags & X86II::ImmMask) {
340  case X86II::Imm8:   return 1;
341  case X86II::Imm16:  return 2;
342  case X86II::Imm32:  return 4;
343  default: assert(0 && "Immediate size not set!");
344    return 0;
345  }
346}
347
348void Emitter::emitInstruction(const MachineInstr &MI) {
349  NumEmitted++;  // Keep track of the # of mi's emitted
350
351  unsigned Opcode = MI.getOpcode();
352  const TargetInstrDescriptor &Desc = II->get(Opcode);
353
354  // Emit the repeat opcode prefix as needed.
355  if ((Desc.TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);
356
357  // Emit the operand size opcode prefix as needed.
358  if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);
359
360  // Emit the double precision sse fp opcode prefix as needed.
361  if ((Desc.TSFlags & X86II::Op0Mask) == X86II::XD) {
362    MCE.emitByte(0xF2); MCE.emitByte(0x0F);
363  }
364
365  // Emit the double precision sse fp opcode prefix as needed.
366  if ((Desc.TSFlags & X86II::Op0Mask) == X86II::XS) {
367    MCE.emitByte(0xF3); MCE.emitByte(0x0F);
368  }
369
370  switch (Desc.TSFlags & X86II::Op0Mask) {
371  case X86II::TB:
372    MCE.emitByte(0x0F);   // Two-byte opcode prefix
373    break;
374  case X86II::REP: break; // already handled.
375  case X86II::XS:   // F3 0F
376    MCE.emitByte(0xF3);
377    MCE.emitByte(0x0F);
378    break;
379  case X86II::XD:   // F2 0F
380    MCE.emitByte(0xF2);
381    MCE.emitByte(0x0F);
382    break;
383  case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
384  case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
385    MCE.emitByte(0xD8+
386                 (((Desc.TSFlags & X86II::Op0Mask)-X86II::D8)
387                                   >> X86II::Op0Shift));
388    break; // Two-byte opcode prefix
389  default: assert(0 && "Invalid prefix!");
390  case 0: break;  // No prefix!
391  }
392
393  unsigned char BaseOpcode = II->getBaseOpcodeFor(Opcode);
394  switch (Desc.TSFlags & X86II::FormMask) {
395  default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
396  case X86II::Pseudo:
397#ifndef NDEBUG
398    switch (Opcode) {
399    default:
400      assert(0 && "psuedo instructions should be removed before code emission");
401    case X86::IMPLICIT_USE:
402    case X86::IMPLICIT_DEF:
403    case X86::IMPLICIT_DEF_R8:
404    case X86::IMPLICIT_DEF_R16:
405    case X86::IMPLICIT_DEF_R32:
406    case X86::IMPLICIT_DEF_FR32:
407    case X86::IMPLICIT_DEF_FR64:
408    case X86::FP_REG_KILL:
409      break;
410    }
411#endif
412    break;
413
414  case X86II::RawFrm:
415    MCE.emitByte(BaseOpcode);
416    if (MI.getNumOperands() == 1) {
417      const MachineOperand &MO = MI.getOperand(0);
418      if (MO.isMachineBasicBlock()) {
419        emitPCRelativeBlockAddress(MO.getMachineBasicBlock());
420      } else if (MO.isGlobalAddress()) {
421        bool isTailCall = Opcode == X86::TAILJMPd ||
422                          Opcode == X86::TAILJMPr || Opcode == X86::TAILJMPm;
423        emitGlobalAddressForCall(MO.getGlobal(), isTailCall);
424      } else if (MO.isExternalSymbol()) {
425        bool isTailCall = Opcode == X86::TAILJMPd ||
426                          Opcode == X86::TAILJMPr || Opcode == X86::TAILJMPm;
427        emitExternalSymbolAddress(MO.getSymbolName(), true, isTailCall);
428      } else if (MO.isImmediate()) {
429        emitConstant(MO.getImmedValue(), sizeOfImm(Desc));
430      } else {
431        assert(0 && "Unknown RawFrm operand!");
432      }
433    }
434    break;
435
436  case X86II::AddRegFrm:
437    MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(0).getReg()));
438    if (MI.getNumOperands() == 2) {
439      const MachineOperand &MO1 = MI.getOperand(1);
440      if (Value *V = MO1.getVRegValueOrNull()) {
441        assert(sizeOfImm(Desc) == 4 &&
442               "Don't know how to emit non-pointer values!");
443        emitGlobalAddressForPtr(cast<GlobalValue>(V));
444      } else if (MO1.isGlobalAddress()) {
445        assert(sizeOfImm(Desc) == 4 &&
446               "Don't know how to emit non-pointer values!");
447        assert(!MO1.isPCRelative() && "Function pointer ref is PC relative?");
448        emitGlobalAddressForPtr(MO1.getGlobal(), MO1.getOffset());
449      } else if (MO1.isExternalSymbol()) {
450        assert(sizeOfImm(Desc) == 4 &&
451               "Don't know how to emit non-pointer values!");
452        emitExternalSymbolAddress(MO1.getSymbolName(), false, false);
453      } else {
454        emitConstant(MO1.getImmedValue(), sizeOfImm(Desc));
455      }
456    }
457    break;
458
459  case X86II::MRMDestReg: {
460    MCE.emitByte(BaseOpcode);
461    emitRegModRMByte(MI.getOperand(0).getReg(),
462                     getX86RegNum(MI.getOperand(1).getReg()));
463    if (MI.getNumOperands() == 3)
464      emitConstant(MI.getOperand(2).getImmedValue(), sizeOfImm(Desc));
465    break;
466  }
467  case X86II::MRMDestMem:
468    MCE.emitByte(BaseOpcode);
469    emitMemModRMByte(MI, 0, getX86RegNum(MI.getOperand(4).getReg()));
470    if (MI.getNumOperands() == 6)
471      emitConstant(MI.getOperand(5).getImmedValue(), sizeOfImm(Desc));
472    break;
473
474  case X86II::MRMSrcReg:
475    MCE.emitByte(BaseOpcode);
476
477    emitRegModRMByte(MI.getOperand(1).getReg(),
478                     getX86RegNum(MI.getOperand(0).getReg()));
479    if (MI.getNumOperands() == 3)
480      emitConstant(MI.getOperand(2).getImmedValue(), sizeOfImm(Desc));
481    break;
482
483  case X86II::MRMSrcMem:
484    MCE.emitByte(BaseOpcode);
485    emitMemModRMByte(MI, 1, getX86RegNum(MI.getOperand(0).getReg()));
486    if (MI.getNumOperands() == 2+4)
487      emitConstant(MI.getOperand(5).getImmedValue(), sizeOfImm(Desc));
488    break;
489
490  case X86II::MRM0r: case X86II::MRM1r:
491  case X86II::MRM2r: case X86II::MRM3r:
492  case X86II::MRM4r: case X86II::MRM5r:
493  case X86II::MRM6r: case X86II::MRM7r:
494    MCE.emitByte(BaseOpcode);
495    emitRegModRMByte(MI.getOperand(0).getReg(),
496                     (Desc.TSFlags & X86II::FormMask)-X86II::MRM0r);
497
498    if (MI.getOperand(MI.getNumOperands()-1).isImmediate()) {
499      emitConstant(MI.getOperand(MI.getNumOperands()-1).getImmedValue(),
500                   sizeOfImm(Desc));
501    }
502    break;
503
504  case X86II::MRM0m: case X86II::MRM1m:
505  case X86II::MRM2m: case X86II::MRM3m:
506  case X86II::MRM4m: case X86II::MRM5m:
507  case X86II::MRM6m: case X86II::MRM7m:
508    MCE.emitByte(BaseOpcode);
509    emitMemModRMByte(MI, 0, (Desc.TSFlags & X86II::FormMask)-X86II::MRM0m);
510
511    if (MI.getNumOperands() == 5) {
512      if (MI.getOperand(4).isImmediate())
513        emitConstant(MI.getOperand(4).getImmedValue(), sizeOfImm(Desc));
514      else if (MI.getOperand(4).isGlobalAddress())
515        emitGlobalAddressForPtr(MI.getOperand(4).getGlobal(),
516                                MI.getOperand(4).getOffset());
517      else
518        assert(0 && "Unknown operand!");
519    }
520    break;
521  }
522}
523