X86FastISel.cpp revision 12513889fdeebc5d835aa6a46f75c73ea8ba1ba3
1//===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the X86-specific support for the FastISel class. Much 11// of the target-specific code is generated by tablegen in the file 12// X86GenFastISel.inc, which is #included here. 13// 14//===----------------------------------------------------------------------===// 15 16#include "X86.h" 17#include "X86InstrBuilder.h" 18#include "X86ISelLowering.h" 19#include "X86RegisterInfo.h" 20#include "X86Subtarget.h" 21#include "X86TargetMachine.h" 22#include "llvm/CallingConv.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/GlobalVariable.h" 25#include "llvm/Instructions.h" 26#include "llvm/IntrinsicInst.h" 27#include "llvm/CodeGen/FastISel.h" 28#include "llvm/CodeGen/MachineConstantPool.h" 29#include "llvm/CodeGen/MachineFrameInfo.h" 30#include "llvm/CodeGen/MachineRegisterInfo.h" 31#include "llvm/Support/CallSite.h" 32#include "llvm/Support/GetElementPtrTypeIterator.h" 33#include "llvm/Target/TargetOptions.h" 34using namespace llvm; 35 36namespace { 37 38class X86FastISel : public FastISel { 39 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can 40 /// make the right decision when generating code for different targets. 41 const X86Subtarget *Subtarget; 42 43 /// StackPtr - Register used as the stack pointer. 44 /// 45 unsigned StackPtr; 46 47 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87 48 /// floating point ops. 49 /// When SSE is available, use it for f32 operations. 50 /// When SSE2 is available, use it for f64 operations. 51 bool X86ScalarSSEf64; 52 bool X86ScalarSSEf32; 53 54public: 55 explicit X86FastISel(MachineFunction &mf, 56 MachineModuleInfo *mmi, 57 DwarfWriter *dw, 58 DenseMap<const Value *, unsigned> &vm, 59 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 60 DenseMap<const AllocaInst *, int> &am 61#ifndef NDEBUG 62 , SmallSet<Instruction*, 8> &cil 63#endif 64 ) 65 : FastISel(mf, mmi, dw, vm, bm, am 66#ifndef NDEBUG 67 , cil 68#endif 69 ) { 70 Subtarget = &TM.getSubtarget<X86Subtarget>(); 71 StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 72 X86ScalarSSEf64 = Subtarget->hasSSE2(); 73 X86ScalarSSEf32 = Subtarget->hasSSE1(); 74 } 75 76 virtual bool TargetSelectInstruction(Instruction *I); 77 78#include "X86GenFastISel.inc" 79 80private: 81 bool X86FastEmitCompare(Value *LHS, Value *RHS, MVT VT); 82 83 bool X86FastEmitLoad(MVT VT, const X86AddressMode &AM, unsigned &RR); 84 85 bool X86FastEmitStore(MVT VT, Value *Val, 86 const X86AddressMode &AM); 87 bool X86FastEmitStore(MVT VT, unsigned Val, 88 const X86AddressMode &AM); 89 90 bool X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT, unsigned Src, MVT SrcVT, 91 unsigned &ResultReg); 92 93 bool X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall); 94 95 bool X86SelectLoad(Instruction *I); 96 97 bool X86SelectStore(Instruction *I); 98 99 bool X86SelectCmp(Instruction *I); 100 101 bool X86SelectZExt(Instruction *I); 102 103 bool X86SelectBranch(Instruction *I); 104 105 bool X86SelectShift(Instruction *I); 106 107 bool X86SelectSelect(Instruction *I); 108 109 bool X86SelectTrunc(Instruction *I); 110 111 bool X86SelectFPExt(Instruction *I); 112 bool X86SelectFPTrunc(Instruction *I); 113 114 bool X86SelectExtractValue(Instruction *I); 115 116 bool X86VisitIntrinsicCall(IntrinsicInst &I); 117 bool X86SelectCall(Instruction *I); 118 119 CCAssignFn *CCAssignFnForCall(unsigned CC, bool isTailCall = false); 120 121 const X86InstrInfo *getInstrInfo() const { 122 return getTargetMachine()->getInstrInfo(); 123 } 124 const X86TargetMachine *getTargetMachine() const { 125 return static_cast<const X86TargetMachine *>(&TM); 126 } 127 128 unsigned TargetMaterializeConstant(Constant *C); 129 130 unsigned TargetMaterializeAlloca(AllocaInst *C); 131 132 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is 133 /// computed in an SSE register, not on the X87 floating point stack. 134 bool isScalarFPTypeInSSEReg(MVT VT) const { 135 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 136 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 137 } 138 139 bool isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1 = false); 140}; 141 142} // end anonymous namespace. 143 144bool X86FastISel::isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1) { 145 VT = TLI.getValueType(Ty, /*HandleUnknown=*/true); 146 if (VT == MVT::Other || !VT.isSimple()) 147 // Unhandled type. Halt "fast" selection and bail. 148 return false; 149 150 // For now, require SSE/SSE2 for performing floating-point operations, 151 // since x87 requires additional work. 152 if (VT == MVT::f64 && !X86ScalarSSEf64) 153 return false; 154 if (VT == MVT::f32 && !X86ScalarSSEf32) 155 return false; 156 // Similarly, no f80 support yet. 157 if (VT == MVT::f80) 158 return false; 159 // We only handle legal types. For example, on x86-32 the instruction 160 // selector contains all of the 64-bit instructions from x86-64, 161 // under the assumption that i64 won't be used if the target doesn't 162 // support it. 163 return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT); 164} 165 166#include "X86GenCallingConv.inc" 167 168/// CCAssignFnForCall - Selects the correct CCAssignFn for a given calling 169/// convention. 170CCAssignFn *X86FastISel::CCAssignFnForCall(unsigned CC, bool isTaillCall) { 171 if (Subtarget->is64Bit()) { 172 if (Subtarget->isTargetWin64()) 173 return CC_X86_Win64_C; 174 else if (CC == CallingConv::Fast && isTaillCall) 175 return CC_X86_64_TailCall; 176 else 177 return CC_X86_64_C; 178 } 179 180 if (CC == CallingConv::X86_FastCall) 181 return CC_X86_32_FastCall; 182 else if (CC == CallingConv::Fast) 183 return CC_X86_32_FastCC; 184 else 185 return CC_X86_32_C; 186} 187 188/// X86FastEmitLoad - Emit a machine instruction to load a value of type VT. 189/// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV. 190/// Return true and the result register by reference if it is possible. 191bool X86FastISel::X86FastEmitLoad(MVT VT, const X86AddressMode &AM, 192 unsigned &ResultReg) { 193 // Get opcode and regclass of the output for the given load instruction. 194 unsigned Opc = 0; 195 const TargetRegisterClass *RC = NULL; 196 switch (VT.getSimpleVT()) { 197 default: return false; 198 case MVT::i8: 199 Opc = X86::MOV8rm; 200 RC = X86::GR8RegisterClass; 201 break; 202 case MVT::i16: 203 Opc = X86::MOV16rm; 204 RC = X86::GR16RegisterClass; 205 break; 206 case MVT::i32: 207 Opc = X86::MOV32rm; 208 RC = X86::GR32RegisterClass; 209 break; 210 case MVT::i64: 211 // Must be in x86-64 mode. 212 Opc = X86::MOV64rm; 213 RC = X86::GR64RegisterClass; 214 break; 215 case MVT::f32: 216 if (Subtarget->hasSSE1()) { 217 Opc = X86::MOVSSrm; 218 RC = X86::FR32RegisterClass; 219 } else { 220 Opc = X86::LD_Fp32m; 221 RC = X86::RFP32RegisterClass; 222 } 223 break; 224 case MVT::f64: 225 if (Subtarget->hasSSE2()) { 226 Opc = X86::MOVSDrm; 227 RC = X86::FR64RegisterClass; 228 } else { 229 Opc = X86::LD_Fp64m; 230 RC = X86::RFP64RegisterClass; 231 } 232 break; 233 case MVT::f80: 234 // No f80 support yet. 235 return false; 236 } 237 238 ResultReg = createResultReg(RC); 239 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM); 240 return true; 241} 242 243/// X86FastEmitStore - Emit a machine instruction to store a value Val of 244/// type VT. The address is either pre-computed, consisted of a base ptr, Ptr 245/// and a displacement offset, or a GlobalAddress, 246/// i.e. V. Return true if it is possible. 247bool 248X86FastISel::X86FastEmitStore(MVT VT, unsigned Val, 249 const X86AddressMode &AM) { 250 // Get opcode and regclass of the output for the given store instruction. 251 unsigned Opc = 0; 252 switch (VT.getSimpleVT()) { 253 case MVT::f80: // No f80 support yet. 254 default: return false; 255 case MVT::i8: Opc = X86::MOV8mr; break; 256 case MVT::i16: Opc = X86::MOV16mr; break; 257 case MVT::i32: Opc = X86::MOV32mr; break; 258 case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode. 259 case MVT::f32: 260 Opc = Subtarget->hasSSE1() ? X86::MOVSSmr : X86::ST_Fp32m; 261 break; 262 case MVT::f64: 263 Opc = Subtarget->hasSSE2() ? X86::MOVSDmr : X86::ST_Fp64m; 264 break; 265 } 266 267 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM).addReg(Val); 268 return true; 269} 270 271bool X86FastISel::X86FastEmitStore(MVT VT, Value *Val, 272 const X86AddressMode &AM) { 273 // Handle 'null' like i32/i64 0. 274 if (isa<ConstantPointerNull>(Val)) 275 Val = Constant::getNullValue(TD.getIntPtrType()); 276 277 // If this is a store of a simple constant, fold the constant into the store. 278 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) { 279 unsigned Opc = 0; 280 switch (VT.getSimpleVT()) { 281 default: break; 282 case MVT::i8: Opc = X86::MOV8mi; break; 283 case MVT::i16: Opc = X86::MOV16mi; break; 284 case MVT::i32: Opc = X86::MOV32mi; break; 285 case MVT::i64: 286 // Must be a 32-bit sign extended value. 287 if ((int)CI->getSExtValue() == CI->getSExtValue()) 288 Opc = X86::MOV64mi32; 289 break; 290 } 291 292 if (Opc) { 293 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM) 294 .addImm(CI->getSExtValue()); 295 return true; 296 } 297 } 298 299 unsigned ValReg = getRegForValue(Val); 300 if (ValReg == 0) 301 return false; 302 303 return X86FastEmitStore(VT, ValReg, AM); 304} 305 306/// X86FastEmitExtend - Emit a machine instruction to extend a value Src of 307/// type SrcVT to type DstVT using the specified extension opcode Opc (e.g. 308/// ISD::SIGN_EXTEND). 309bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT, 310 unsigned Src, MVT SrcVT, 311 unsigned &ResultReg) { 312 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src); 313 314 if (RR != 0) { 315 ResultReg = RR; 316 return true; 317 } else 318 return false; 319} 320 321/// X86SelectAddress - Attempt to fill in an address from the given value. 322/// 323bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall) { 324 User *U = NULL; 325 unsigned Opcode = Instruction::UserOp1; 326 if (Instruction *I = dyn_cast<Instruction>(V)) { 327 Opcode = I->getOpcode(); 328 U = I; 329 } else if (ConstantExpr *C = dyn_cast<ConstantExpr>(V)) { 330 Opcode = C->getOpcode(); 331 U = C; 332 } 333 334 switch (Opcode) { 335 default: break; 336 case Instruction::BitCast: 337 // Look past bitcasts. 338 return X86SelectAddress(U->getOperand(0), AM, isCall); 339 340 case Instruction::IntToPtr: 341 // Look past no-op inttoptrs. 342 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy()) 343 return X86SelectAddress(U->getOperand(0), AM, isCall); 344 break; 345 346 case Instruction::PtrToInt: 347 // Look past no-op ptrtoints. 348 if (TLI.getValueType(U->getType()) == TLI.getPointerTy()) 349 return X86SelectAddress(U->getOperand(0), AM, isCall); 350 break; 351 352 case Instruction::Alloca: { 353 if (isCall) break; 354 // Do static allocas. 355 const AllocaInst *A = cast<AllocaInst>(V); 356 DenseMap<const AllocaInst*, int>::iterator SI = StaticAllocaMap.find(A); 357 if (SI != StaticAllocaMap.end()) { 358 AM.BaseType = X86AddressMode::FrameIndexBase; 359 AM.Base.FrameIndex = SI->second; 360 return true; 361 } 362 break; 363 } 364 365 case Instruction::Add: { 366 if (isCall) break; 367 // Adds of constants are common and easy enough. 368 if (ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) { 369 uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue(); 370 // They have to fit in the 32-bit signed displacement field though. 371 if (isInt32(Disp)) { 372 AM.Disp = (uint32_t)Disp; 373 return X86SelectAddress(U->getOperand(0), AM, isCall); 374 } 375 } 376 break; 377 } 378 379 case Instruction::GetElementPtr: { 380 if (isCall) break; 381 // Pattern-match simple GEPs. 382 uint64_t Disp = (int32_t)AM.Disp; 383 unsigned IndexReg = AM.IndexReg; 384 unsigned Scale = AM.Scale; 385 gep_type_iterator GTI = gep_type_begin(U); 386 // Iterate through the indices, folding what we can. Constants can be 387 // folded, and one dynamic index can be handled, if the scale is supported. 388 for (User::op_iterator i = U->op_begin() + 1, e = U->op_end(); 389 i != e; ++i, ++GTI) { 390 Value *Op = *i; 391 if (const StructType *STy = dyn_cast<StructType>(*GTI)) { 392 const StructLayout *SL = TD.getStructLayout(STy); 393 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue(); 394 Disp += SL->getElementOffset(Idx); 395 } else { 396 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType()); 397 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op)) { 398 // Constant-offset addressing. 399 Disp += CI->getSExtValue() * S; 400 } else if (IndexReg == 0 && 401 (!AM.GV || 402 !getTargetMachine()->symbolicAddressesAreRIPRel()) && 403 (S == 1 || S == 2 || S == 4 || S == 8)) { 404 // Scaled-index addressing. 405 Scale = S; 406 IndexReg = getRegForGEPIndex(Op); 407 if (IndexReg == 0) 408 return false; 409 } else 410 // Unsupported. 411 goto unsupported_gep; 412 } 413 } 414 // Check for displacement overflow. 415 if (!isInt32(Disp)) 416 break; 417 // Ok, the GEP indices were covered by constant-offset and scaled-index 418 // addressing. Update the address state and move on to examining the base. 419 AM.IndexReg = IndexReg; 420 AM.Scale = Scale; 421 AM.Disp = (uint32_t)Disp; 422 return X86SelectAddress(U->getOperand(0), AM, isCall); 423 unsupported_gep: 424 // Ok, the GEP indices weren't all covered. 425 break; 426 } 427 } 428 429 // Handle constant address. 430 if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) { 431 // Can't handle alternate code models yet. 432 if (TM.getCodeModel() != CodeModel::Default && 433 TM.getCodeModel() != CodeModel::Small) 434 return false; 435 436 // RIP-relative addresses can't have additional register operands. 437 if (getTargetMachine()->symbolicAddressesAreRIPRel() && 438 (AM.Base.Reg != 0 || AM.IndexReg != 0)) 439 return false; 440 441 // Can't handle TLS yet. 442 if (GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV)) 443 if (GVar->isThreadLocal()) 444 return false; 445 446 // Set up the basic address. 447 AM.GV = GV; 448 if (!isCall && 449 TM.getRelocationModel() == Reloc::PIC_ && 450 !Subtarget->is64Bit()) 451 AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(&MF); 452 453 // Emit an extra load if the ABI requires it. 454 if (Subtarget->GVRequiresExtraLoad(GV, TM, isCall)) { 455 // Check to see if we've already materialized this 456 // value in a register in this block. 457 if (unsigned Reg = LocalValueMap[V]) { 458 AM.Base.Reg = Reg; 459 AM.GV = 0; 460 return true; 461 } 462 // Issue load from stub if necessary. 463 unsigned Opc = 0; 464 const TargetRegisterClass *RC = NULL; 465 if (TLI.getPointerTy() == MVT::i32) { 466 Opc = X86::MOV32rm; 467 RC = X86::GR32RegisterClass; 468 } else { 469 Opc = X86::MOV64rm; 470 RC = X86::GR64RegisterClass; 471 } 472 473 X86AddressMode StubAM; 474 StubAM.Base.Reg = AM.Base.Reg; 475 StubAM.GV = AM.GV; 476 unsigned ResultReg = createResultReg(RC); 477 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), StubAM); 478 479 // Now construct the final address. Note that the Disp, Scale, 480 // and Index values may already be set here. 481 AM.Base.Reg = ResultReg; 482 AM.GV = 0; 483 484 // Prevent loading GV stub multiple times in same MBB. 485 LocalValueMap[V] = AM.Base.Reg; 486 } 487 return true; 488 } 489 490 // If all else fails, try to materialize the value in a register. 491 if (!AM.GV || !getTargetMachine()->symbolicAddressesAreRIPRel()) { 492 if (AM.Base.Reg == 0) { 493 AM.Base.Reg = getRegForValue(V); 494 return AM.Base.Reg != 0; 495 } 496 if (AM.IndexReg == 0) { 497 assert(AM.Scale == 1 && "Scale with no index!"); 498 AM.IndexReg = getRegForValue(V); 499 return AM.IndexReg != 0; 500 } 501 } 502 503 return false; 504} 505 506/// X86SelectStore - Select and emit code to implement store instructions. 507bool X86FastISel::X86SelectStore(Instruction* I) { 508 MVT VT; 509 if (!isTypeLegal(I->getOperand(0)->getType(), VT)) 510 return false; 511 512 X86AddressMode AM; 513 if (!X86SelectAddress(I->getOperand(1), AM, false)) 514 return false; 515 516 return X86FastEmitStore(VT, I->getOperand(0), AM); 517} 518 519/// X86SelectLoad - Select and emit code to implement load instructions. 520/// 521bool X86FastISel::X86SelectLoad(Instruction *I) { 522 MVT VT; 523 if (!isTypeLegal(I->getType(), VT)) 524 return false; 525 526 X86AddressMode AM; 527 if (!X86SelectAddress(I->getOperand(0), AM, false)) 528 return false; 529 530 unsigned ResultReg = 0; 531 if (X86FastEmitLoad(VT, AM, ResultReg)) { 532 UpdateValueMap(I, ResultReg); 533 return true; 534 } 535 return false; 536} 537 538static unsigned X86ChooseCmpOpcode(MVT VT) { 539 switch (VT.getSimpleVT()) { 540 default: return 0; 541 case MVT::i8: return X86::CMP8rr; 542 case MVT::i16: return X86::CMP16rr; 543 case MVT::i32: return X86::CMP32rr; 544 case MVT::i64: return X86::CMP64rr; 545 case MVT::f32: return X86::UCOMISSrr; 546 case MVT::f64: return X86::UCOMISDrr; 547 } 548} 549 550/// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS 551/// of the comparison, return an opcode that works for the compare (e.g. 552/// CMP32ri) otherwise return 0. 553static unsigned X86ChooseCmpImmediateOpcode(MVT VT, ConstantInt *RHSC) { 554 switch (VT.getSimpleVT()) { 555 // Otherwise, we can't fold the immediate into this comparison. 556 default: return 0; 557 case MVT::i8: return X86::CMP8ri; 558 case MVT::i16: return X86::CMP16ri; 559 case MVT::i32: return X86::CMP32ri; 560 case MVT::i64: 561 // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext 562 // field. 563 if ((int)RHSC->getSExtValue() == RHSC->getSExtValue()) 564 return X86::CMP64ri32; 565 return 0; 566 } 567} 568 569bool X86FastISel::X86FastEmitCompare(Value *Op0, Value *Op1, MVT VT) { 570 unsigned Op0Reg = getRegForValue(Op0); 571 if (Op0Reg == 0) return false; 572 573 // Handle 'null' like i32/i64 0. 574 if (isa<ConstantPointerNull>(Op1)) 575 Op1 = Constant::getNullValue(TD.getIntPtrType()); 576 577 // We have two options: compare with register or immediate. If the RHS of 578 // the compare is an immediate that we can fold into this compare, use 579 // CMPri, otherwise use CMPrr. 580 if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) { 581 if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) { 582 BuildMI(MBB, DL, TII.get(CompareImmOpc)).addReg(Op0Reg) 583 .addImm(Op1C->getSExtValue()); 584 return true; 585 } 586 } 587 588 unsigned CompareOpc = X86ChooseCmpOpcode(VT); 589 if (CompareOpc == 0) return false; 590 591 unsigned Op1Reg = getRegForValue(Op1); 592 if (Op1Reg == 0) return false; 593 BuildMI(MBB, DL, TII.get(CompareOpc)).addReg(Op0Reg).addReg(Op1Reg); 594 595 return true; 596} 597 598bool X86FastISel::X86SelectCmp(Instruction *I) { 599 CmpInst *CI = cast<CmpInst>(I); 600 601 MVT VT; 602 if (!isTypeLegal(I->getOperand(0)->getType(), VT)) 603 return false; 604 605 unsigned ResultReg = createResultReg(&X86::GR8RegClass); 606 unsigned SetCCOpc; 607 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0. 608 switch (CI->getPredicate()) { 609 case CmpInst::FCMP_OEQ: { 610 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT)) 611 return false; 612 613 unsigned EReg = createResultReg(&X86::GR8RegClass); 614 unsigned NPReg = createResultReg(&X86::GR8RegClass); 615 BuildMI(MBB, DL, TII.get(X86::SETEr), EReg); 616 BuildMI(MBB, DL, TII.get(X86::SETNPr), NPReg); 617 BuildMI(MBB, DL, 618 TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg); 619 UpdateValueMap(I, ResultReg); 620 return true; 621 } 622 case CmpInst::FCMP_UNE: { 623 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT)) 624 return false; 625 626 unsigned NEReg = createResultReg(&X86::GR8RegClass); 627 unsigned PReg = createResultReg(&X86::GR8RegClass); 628 BuildMI(MBB, DL, TII.get(X86::SETNEr), NEReg); 629 BuildMI(MBB, DL, TII.get(X86::SETPr), PReg); 630 BuildMI(MBB, DL, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg); 631 UpdateValueMap(I, ResultReg); 632 return true; 633 } 634 case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break; 635 case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break; 636 case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break; 637 case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break; 638 case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break; 639 case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break; 640 case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break; 641 case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break; 642 case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break; 643 case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break; 644 case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break; 645 case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break; 646 647 case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break; 648 case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break; 649 case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break; 650 case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break; 651 case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break; 652 case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break; 653 case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break; 654 case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break; 655 case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break; 656 case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break; 657 default: 658 return false; 659 } 660 661 Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1); 662 if (SwapArgs) 663 std::swap(Op0, Op1); 664 665 // Emit a compare of Op0/Op1. 666 if (!X86FastEmitCompare(Op0, Op1, VT)) 667 return false; 668 669 BuildMI(MBB, DL, TII.get(SetCCOpc), ResultReg); 670 UpdateValueMap(I, ResultReg); 671 return true; 672} 673 674bool X86FastISel::X86SelectZExt(Instruction *I) { 675 // Handle zero-extension from i1 to i8, which is common. 676 if (I->getType() == Type::Int8Ty && 677 I->getOperand(0)->getType() == Type::Int1Ty) { 678 unsigned ResultReg = getRegForValue(I->getOperand(0)); 679 if (ResultReg == 0) return false; 680 // Set the high bits to zero. 681 ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg); 682 if (ResultReg == 0) return false; 683 UpdateValueMap(I, ResultReg); 684 return true; 685 } 686 687 return false; 688} 689 690 691bool X86FastISel::X86SelectBranch(Instruction *I) { 692 // Unconditional branches are selected by tablegen-generated code. 693 // Handle a conditional branch. 694 BranchInst *BI = cast<BranchInst>(I); 695 MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)]; 696 MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)]; 697 698 // Fold the common case of a conditional branch with a comparison. 699 if (CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) { 700 if (CI->hasOneUse()) { 701 MVT VT = TLI.getValueType(CI->getOperand(0)->getType()); 702 703 // Try to take advantage of fallthrough opportunities. 704 CmpInst::Predicate Predicate = CI->getPredicate(); 705 if (MBB->isLayoutSuccessor(TrueMBB)) { 706 std::swap(TrueMBB, FalseMBB); 707 Predicate = CmpInst::getInversePredicate(Predicate); 708 } 709 710 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0. 711 unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA" 712 713 switch (Predicate) { 714 case CmpInst::FCMP_OEQ: 715 std::swap(TrueMBB, FalseMBB); 716 Predicate = CmpInst::FCMP_UNE; 717 // FALL THROUGH 718 case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE; break; 719 case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA; break; 720 case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE; break; 721 case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA; break; 722 case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE; break; 723 case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE; break; 724 case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP; break; 725 case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP; break; 726 case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE; break; 727 case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB; break; 728 case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE; break; 729 case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB; break; 730 case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE; break; 731 732 case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE; break; 733 case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE; break; 734 case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA; break; 735 case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE; break; 736 case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB; break; 737 case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE; break; 738 case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG; break; 739 case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE; break; 740 case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL; break; 741 case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE; break; 742 default: 743 return false; 744 } 745 746 Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1); 747 if (SwapArgs) 748 std::swap(Op0, Op1); 749 750 // Emit a compare of the LHS and RHS, setting the flags. 751 if (!X86FastEmitCompare(Op0, Op1, VT)) 752 return false; 753 754 BuildMI(MBB, DL, TII.get(BranchOpc)).addMBB(TrueMBB); 755 756 if (Predicate == CmpInst::FCMP_UNE) { 757 // X86 requires a second branch to handle UNE (and OEQ, 758 // which is mapped to UNE above). 759 BuildMI(MBB, DL, TII.get(X86::JP)).addMBB(TrueMBB); 760 } 761 762 FastEmitBranch(FalseMBB); 763 MBB->addSuccessor(TrueMBB); 764 return true; 765 } 766 } else if (ExtractValueInst *EI = 767 dyn_cast<ExtractValueInst>(BI->getCondition())) { 768 // Check to see if the branch instruction is from an "arithmetic with 769 // overflow" intrinsic. The main way these intrinsics are used is: 770 // 771 // %t = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2) 772 // %sum = extractvalue { i32, i1 } %t, 0 773 // %obit = extractvalue { i32, i1 } %t, 1 774 // br i1 %obit, label %overflow, label %normal 775 // 776 // The %sum and %obit are converted in an ADD and a SETO/SETB before 777 // reaching the branch. Therefore, we search backwards through the MBB 778 // looking for the SETO/SETB instruction. If an instruction modifies the 779 // EFLAGS register before we reach the SETO/SETB instruction, then we can't 780 // convert the branch into a JO/JB instruction. 781 if (IntrinsicInst *CI = dyn_cast<IntrinsicInst>(EI->getAggregateOperand())){ 782 if (CI->getIntrinsicID() == Intrinsic::sadd_with_overflow || 783 CI->getIntrinsicID() == Intrinsic::uadd_with_overflow) { 784 const MachineInstr *SetMI = 0; 785 unsigned Reg = lookUpRegForValue(EI); 786 787 for (MachineBasicBlock::const_reverse_iterator 788 RI = MBB->rbegin(), RE = MBB->rend(); RI != RE; ++RI) { 789 const MachineInstr &MI = *RI; 790 791 if (MI.modifiesRegister(Reg)) { 792 unsigned Src, Dst, SrcSR, DstSR; 793 794 if (getInstrInfo()->isMoveInstr(MI, Src, Dst, SrcSR, DstSR)) { 795 Reg = Src; 796 continue; 797 } 798 799 SetMI = &MI; 800 break; 801 } 802 803 const TargetInstrDesc &TID = MI.getDesc(); 804 if (TID.hasUnmodeledSideEffects() || 805 TID.hasImplicitDefOfPhysReg(X86::EFLAGS)) 806 break; 807 } 808 809 if (SetMI) { 810 unsigned OpCode = SetMI->getOpcode(); 811 812 if (OpCode == X86::SETOr || OpCode == X86::SETBr) { 813 BuildMI(MBB, DL, TII.get(OpCode == X86::SETOr ? X86::JO : X86::JB)) 814 .addMBB(TrueMBB); 815 FastEmitBranch(FalseMBB); 816 MBB->addSuccessor(TrueMBB); 817 return true; 818 } 819 } 820 } 821 } 822 } 823 824 // Otherwise do a clumsy setcc and re-test it. 825 unsigned OpReg = getRegForValue(BI->getCondition()); 826 if (OpReg == 0) return false; 827 828 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg); 829 BuildMI(MBB, DL, TII.get(X86::JNE)).addMBB(TrueMBB); 830 FastEmitBranch(FalseMBB); 831 MBB->addSuccessor(TrueMBB); 832 return true; 833} 834 835bool X86FastISel::X86SelectShift(Instruction *I) { 836 unsigned CReg = 0, OpReg = 0, OpImm = 0; 837 const TargetRegisterClass *RC = NULL; 838 if (I->getType() == Type::Int8Ty) { 839 CReg = X86::CL; 840 RC = &X86::GR8RegClass; 841 switch (I->getOpcode()) { 842 case Instruction::LShr: OpReg = X86::SHR8rCL; OpImm = X86::SHR8ri; break; 843 case Instruction::AShr: OpReg = X86::SAR8rCL; OpImm = X86::SAR8ri; break; 844 case Instruction::Shl: OpReg = X86::SHL8rCL; OpImm = X86::SHL8ri; break; 845 default: return false; 846 } 847 } else if (I->getType() == Type::Int16Ty) { 848 CReg = X86::CX; 849 RC = &X86::GR16RegClass; 850 switch (I->getOpcode()) { 851 case Instruction::LShr: OpReg = X86::SHR16rCL; OpImm = X86::SHR16ri; break; 852 case Instruction::AShr: OpReg = X86::SAR16rCL; OpImm = X86::SAR16ri; break; 853 case Instruction::Shl: OpReg = X86::SHL16rCL; OpImm = X86::SHL16ri; break; 854 default: return false; 855 } 856 } else if (I->getType() == Type::Int32Ty) { 857 CReg = X86::ECX; 858 RC = &X86::GR32RegClass; 859 switch (I->getOpcode()) { 860 case Instruction::LShr: OpReg = X86::SHR32rCL; OpImm = X86::SHR32ri; break; 861 case Instruction::AShr: OpReg = X86::SAR32rCL; OpImm = X86::SAR32ri; break; 862 case Instruction::Shl: OpReg = X86::SHL32rCL; OpImm = X86::SHL32ri; break; 863 default: return false; 864 } 865 } else if (I->getType() == Type::Int64Ty) { 866 CReg = X86::RCX; 867 RC = &X86::GR64RegClass; 868 switch (I->getOpcode()) { 869 case Instruction::LShr: OpReg = X86::SHR64rCL; OpImm = X86::SHR64ri; break; 870 case Instruction::AShr: OpReg = X86::SAR64rCL; OpImm = X86::SAR64ri; break; 871 case Instruction::Shl: OpReg = X86::SHL64rCL; OpImm = X86::SHL64ri; break; 872 default: return false; 873 } 874 } else { 875 return false; 876 } 877 878 MVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true); 879 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT)) 880 return false; 881 882 unsigned Op0Reg = getRegForValue(I->getOperand(0)); 883 if (Op0Reg == 0) return false; 884 885 // Fold immediate in shl(x,3). 886 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 887 unsigned ResultReg = createResultReg(RC); 888 BuildMI(MBB, DL, TII.get(OpImm), 889 ResultReg).addReg(Op0Reg).addImm(CI->getZExtValue() & 0xff); 890 UpdateValueMap(I, ResultReg); 891 return true; 892 } 893 894 unsigned Op1Reg = getRegForValue(I->getOperand(1)); 895 if (Op1Reg == 0) return false; 896 TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC); 897 898 // The shift instruction uses X86::CL. If we defined a super-register 899 // of X86::CL, emit an EXTRACT_SUBREG to precisely describe what 900 // we're doing here. 901 if (CReg != X86::CL) 902 BuildMI(MBB, DL, TII.get(TargetInstrInfo::EXTRACT_SUBREG), X86::CL) 903 .addReg(CReg).addImm(X86::SUBREG_8BIT); 904 905 unsigned ResultReg = createResultReg(RC); 906 BuildMI(MBB, DL, TII.get(OpReg), ResultReg).addReg(Op0Reg); 907 UpdateValueMap(I, ResultReg); 908 return true; 909} 910 911bool X86FastISel::X86SelectSelect(Instruction *I) { 912 MVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true); 913 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT)) 914 return false; 915 916 unsigned Opc = 0; 917 const TargetRegisterClass *RC = NULL; 918 if (VT.getSimpleVT() == MVT::i16) { 919 Opc = X86::CMOVE16rr; 920 RC = &X86::GR16RegClass; 921 } else if (VT.getSimpleVT() == MVT::i32) { 922 Opc = X86::CMOVE32rr; 923 RC = &X86::GR32RegClass; 924 } else if (VT.getSimpleVT() == MVT::i64) { 925 Opc = X86::CMOVE64rr; 926 RC = &X86::GR64RegClass; 927 } else { 928 return false; 929 } 930 931 unsigned Op0Reg = getRegForValue(I->getOperand(0)); 932 if (Op0Reg == 0) return false; 933 unsigned Op1Reg = getRegForValue(I->getOperand(1)); 934 if (Op1Reg == 0) return false; 935 unsigned Op2Reg = getRegForValue(I->getOperand(2)); 936 if (Op2Reg == 0) return false; 937 938 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(Op0Reg).addReg(Op0Reg); 939 unsigned ResultReg = createResultReg(RC); 940 BuildMI(MBB, DL, TII.get(Opc), ResultReg).addReg(Op1Reg).addReg(Op2Reg); 941 UpdateValueMap(I, ResultReg); 942 return true; 943} 944 945bool X86FastISel::X86SelectFPExt(Instruction *I) { 946 // fpext from float to double. 947 if (Subtarget->hasSSE2() && I->getType() == Type::DoubleTy) { 948 Value *V = I->getOperand(0); 949 if (V->getType() == Type::FloatTy) { 950 unsigned OpReg = getRegForValue(V); 951 if (OpReg == 0) return false; 952 unsigned ResultReg = createResultReg(X86::FR64RegisterClass); 953 BuildMI(MBB, DL, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg); 954 UpdateValueMap(I, ResultReg); 955 return true; 956 } 957 } 958 959 return false; 960} 961 962bool X86FastISel::X86SelectFPTrunc(Instruction *I) { 963 if (Subtarget->hasSSE2()) { 964 if (I->getType() == Type::FloatTy) { 965 Value *V = I->getOperand(0); 966 if (V->getType() == Type::DoubleTy) { 967 unsigned OpReg = getRegForValue(V); 968 if (OpReg == 0) return false; 969 unsigned ResultReg = createResultReg(X86::FR32RegisterClass); 970 BuildMI(MBB, DL, TII.get(X86::CVTSD2SSrr), ResultReg).addReg(OpReg); 971 UpdateValueMap(I, ResultReg); 972 return true; 973 } 974 } 975 } 976 977 return false; 978} 979 980bool X86FastISel::X86SelectTrunc(Instruction *I) { 981 if (Subtarget->is64Bit()) 982 // All other cases should be handled by the tblgen generated code. 983 return false; 984 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 985 MVT DstVT = TLI.getValueType(I->getType()); 986 987 // This code only handles truncation to byte right now. 988 if (DstVT != MVT::i8 && DstVT != MVT::i1) 989 // All other cases should be handled by the tblgen generated code. 990 return false; 991 if (SrcVT != MVT::i16 && SrcVT != MVT::i32) 992 // All other cases should be handled by the tblgen generated code. 993 return false; 994 995 unsigned InputReg = getRegForValue(I->getOperand(0)); 996 if (!InputReg) 997 // Unhandled operand. Halt "fast" selection and bail. 998 return false; 999 1000 // First issue a copy to GR16_ABCD or GR32_ABCD. 1001 unsigned CopyOpc = (SrcVT == MVT::i16) ? X86::MOV16rr : X86::MOV32rr; 1002 const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16) 1003 ? X86::GR16_ABCDRegisterClass : X86::GR32_ABCDRegisterClass; 1004 unsigned CopyReg = createResultReg(CopyRC); 1005 BuildMI(MBB, DL, TII.get(CopyOpc), CopyReg).addReg(InputReg); 1006 1007 // Then issue an extract_subreg. 1008 unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8, 1009 CopyReg, X86::SUBREG_8BIT); 1010 if (!ResultReg) 1011 return false; 1012 1013 UpdateValueMap(I, ResultReg); 1014 return true; 1015} 1016 1017bool X86FastISel::X86SelectExtractValue(Instruction *I) { 1018 ExtractValueInst *EI = cast<ExtractValueInst>(I); 1019 Value *Agg = EI->getAggregateOperand(); 1020 1021 if (IntrinsicInst *CI = dyn_cast<IntrinsicInst>(Agg)) { 1022 switch (CI->getIntrinsicID()) { 1023 default: break; 1024 case Intrinsic::sadd_with_overflow: 1025 case Intrinsic::uadd_with_overflow: 1026 // Cheat a little. We know that the registers for "add" and "seto" are 1027 // allocated sequentially. However, we only keep track of the register 1028 // for "add" in the value map. Use extractvalue's index to get the 1029 // correct register for "seto". 1030 UpdateValueMap(I, lookUpRegForValue(Agg) + *EI->idx_begin()); 1031 return true; 1032 } 1033 } 1034 1035 return false; 1036} 1037 1038bool X86FastISel::X86VisitIntrinsicCall(IntrinsicInst &I) { 1039 // FIXME: Handle more intrinsics. 1040 switch (I.getIntrinsicID()) { 1041 default: return false; 1042 case Intrinsic::sadd_with_overflow: 1043 case Intrinsic::uadd_with_overflow: { 1044 // Replace "add with overflow" intrinsics with an "add" instruction followed 1045 // by a seto/setc instruction. Later on, when the "extractvalue" 1046 // instructions are encountered, we use the fact that two registers were 1047 // created sequentially to get the correct registers for the "sum" and the 1048 // "overflow bit". 1049 const Function *Callee = I.getCalledFunction(); 1050 const Type *RetTy = 1051 cast<StructType>(Callee->getReturnType())->getTypeAtIndex(unsigned(0)); 1052 1053 MVT VT; 1054 if (!isTypeLegal(RetTy, VT)) 1055 return false; 1056 1057 Value *Op1 = I.getOperand(1); 1058 Value *Op2 = I.getOperand(2); 1059 unsigned Reg1 = getRegForValue(Op1); 1060 unsigned Reg2 = getRegForValue(Op2); 1061 1062 if (Reg1 == 0 || Reg2 == 0) 1063 // FIXME: Handle values *not* in registers. 1064 return false; 1065 1066 unsigned OpC = 0; 1067 if (VT == MVT::i32) 1068 OpC = X86::ADD32rr; 1069 else if (VT == MVT::i64) 1070 OpC = X86::ADD64rr; 1071 else 1072 return false; 1073 1074 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); 1075 BuildMI(MBB, DL, TII.get(OpC), ResultReg).addReg(Reg1).addReg(Reg2); 1076 unsigned DestReg1 = UpdateValueMap(&I, ResultReg); 1077 1078 // If the add with overflow is an intra-block value then we just want to 1079 // create temporaries for it like normal. If it is a cross-block value then 1080 // UpdateValueMap will return the cross-block register used. Since we 1081 // *really* want the value to be live in the register pair known by 1082 // UpdateValueMap, we have to use DestReg1+1 as the destination register in 1083 // the cross block case. In the non-cross-block case, we should just make 1084 // another register for the value. 1085 if (DestReg1 != ResultReg) 1086 ResultReg = DestReg1+1; 1087 else 1088 ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8)); 1089 1090 unsigned Opc = X86::SETBr; 1091 if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow) 1092 Opc = X86::SETOr; 1093 BuildMI(MBB, DL, TII.get(Opc), ResultReg); 1094 return true; 1095 } 1096 } 1097} 1098 1099bool X86FastISel::X86SelectCall(Instruction *I) { 1100 CallInst *CI = cast<CallInst>(I); 1101 Value *Callee = I->getOperand(0); 1102 1103 // Can't handle inline asm yet. 1104 if (isa<InlineAsm>(Callee)) 1105 return false; 1106 1107 // Handle intrinsic calls. 1108 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(CI)) 1109 return X86VisitIntrinsicCall(*II); 1110 1111 // Handle only C and fastcc calling conventions for now. 1112 CallSite CS(CI); 1113 unsigned CC = CS.getCallingConv(); 1114 if (CC != CallingConv::C && 1115 CC != CallingConv::Fast && 1116 CC != CallingConv::X86_FastCall) 1117 return false; 1118 1119 // On X86, -tailcallopt changes the fastcc ABI. FastISel doesn't 1120 // handle this for now. 1121 if (CC == CallingConv::Fast && PerformTailCallOpt) 1122 return false; 1123 1124 // Let SDISel handle vararg functions. 1125 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 1126 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 1127 if (FTy->isVarArg()) 1128 return false; 1129 1130 // Handle *simple* calls for now. 1131 const Type *RetTy = CS.getType(); 1132 MVT RetVT; 1133 if (RetTy == Type::VoidTy) 1134 RetVT = MVT::isVoid; 1135 else if (!isTypeLegal(RetTy, RetVT, true)) 1136 return false; 1137 1138 // Materialize callee address in a register. FIXME: GV address can be 1139 // handled with a CALLpcrel32 instead. 1140 X86AddressMode CalleeAM; 1141 if (!X86SelectAddress(Callee, CalleeAM, true)) 1142 return false; 1143 unsigned CalleeOp = 0; 1144 GlobalValue *GV = 0; 1145 if (CalleeAM.Base.Reg != 0) { 1146 assert(CalleeAM.GV == 0); 1147 CalleeOp = CalleeAM.Base.Reg; 1148 } else if (CalleeAM.GV != 0) { 1149 assert(CalleeAM.GV != 0); 1150 GV = CalleeAM.GV; 1151 } else 1152 return false; 1153 1154 // Allow calls which produce i1 results. 1155 bool AndToI1 = false; 1156 if (RetVT == MVT::i1) { 1157 RetVT = MVT::i8; 1158 AndToI1 = true; 1159 } 1160 1161 // Deal with call operands first. 1162 SmallVector<Value*, 8> ArgVals; 1163 SmallVector<unsigned, 8> Args; 1164 SmallVector<MVT, 8> ArgVTs; 1165 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags; 1166 Args.reserve(CS.arg_size()); 1167 ArgVals.reserve(CS.arg_size()); 1168 ArgVTs.reserve(CS.arg_size()); 1169 ArgFlags.reserve(CS.arg_size()); 1170 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 1171 i != e; ++i) { 1172 unsigned Arg = getRegForValue(*i); 1173 if (Arg == 0) 1174 return false; 1175 ISD::ArgFlagsTy Flags; 1176 unsigned AttrInd = i - CS.arg_begin() + 1; 1177 if (CS.paramHasAttr(AttrInd, Attribute::SExt)) 1178 Flags.setSExt(); 1179 if (CS.paramHasAttr(AttrInd, Attribute::ZExt)) 1180 Flags.setZExt(); 1181 1182 // FIXME: Only handle *easy* calls for now. 1183 if (CS.paramHasAttr(AttrInd, Attribute::InReg) || 1184 CS.paramHasAttr(AttrInd, Attribute::StructRet) || 1185 CS.paramHasAttr(AttrInd, Attribute::Nest) || 1186 CS.paramHasAttr(AttrInd, Attribute::ByVal)) 1187 return false; 1188 1189 const Type *ArgTy = (*i)->getType(); 1190 MVT ArgVT; 1191 if (!isTypeLegal(ArgTy, ArgVT)) 1192 return false; 1193 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy); 1194 Flags.setOrigAlign(OriginalAlignment); 1195 1196 Args.push_back(Arg); 1197 ArgVals.push_back(*i); 1198 ArgVTs.push_back(ArgVT); 1199 ArgFlags.push_back(Flags); 1200 } 1201 1202 // Analyze operands of the call, assigning locations to each operand. 1203 SmallVector<CCValAssign, 16> ArgLocs; 1204 CCState CCInfo(CC, false, TM, ArgLocs); 1205 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC)); 1206 1207 // Get a count of how many bytes are to be pushed on the stack. 1208 unsigned NumBytes = CCInfo.getNextStackOffset(); 1209 1210 // Issue CALLSEQ_START 1211 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode(); 1212 BuildMI(MBB, DL, TII.get(AdjStackDown)).addImm(NumBytes); 1213 1214 // Process argument: walk the register/memloc assignments, inserting 1215 // copies / loads. 1216 SmallVector<unsigned, 4> RegArgs; 1217 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1218 CCValAssign &VA = ArgLocs[i]; 1219 unsigned Arg = Args[VA.getValNo()]; 1220 MVT ArgVT = ArgVTs[VA.getValNo()]; 1221 1222 // Promote the value if needed. 1223 switch (VA.getLocInfo()) { 1224 default: assert(0 && "Unknown loc info!"); 1225 case CCValAssign::Full: break; 1226 case CCValAssign::SExt: { 1227 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), 1228 Arg, ArgVT, Arg); 1229 assert(Emitted && "Failed to emit a sext!"); Emitted=Emitted; 1230 Emitted = true; 1231 ArgVT = VA.getLocVT(); 1232 break; 1233 } 1234 case CCValAssign::ZExt: { 1235 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), 1236 Arg, ArgVT, Arg); 1237 assert(Emitted && "Failed to emit a zext!"); Emitted=Emitted; 1238 Emitted = true; 1239 ArgVT = VA.getLocVT(); 1240 break; 1241 } 1242 case CCValAssign::AExt: { 1243 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(), 1244 Arg, ArgVT, Arg); 1245 if (!Emitted) 1246 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), 1247 Arg, ArgVT, Arg); 1248 if (!Emitted) 1249 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), 1250 Arg, ArgVT, Arg); 1251 1252 assert(Emitted && "Failed to emit a aext!"); Emitted=Emitted; 1253 ArgVT = VA.getLocVT(); 1254 break; 1255 } 1256 } 1257 1258 if (VA.isRegLoc()) { 1259 TargetRegisterClass* RC = TLI.getRegClassFor(ArgVT); 1260 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), VA.getLocReg(), 1261 Arg, RC, RC); 1262 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted; 1263 Emitted = true; 1264 RegArgs.push_back(VA.getLocReg()); 1265 } else { 1266 unsigned LocMemOffset = VA.getLocMemOffset(); 1267 X86AddressMode AM; 1268 AM.Base.Reg = StackPtr; 1269 AM.Disp = LocMemOffset; 1270 Value *ArgVal = ArgVals[VA.getValNo()]; 1271 1272 // If this is a really simple value, emit this with the Value* version of 1273 // X86FastEmitStore. If it isn't simple, we don't want to do this, as it 1274 // can cause us to reevaluate the argument. 1275 if (isa<ConstantInt>(ArgVal) || isa<ConstantPointerNull>(ArgVal)) 1276 X86FastEmitStore(ArgVT, ArgVal, AM); 1277 else 1278 X86FastEmitStore(ArgVT, Arg, AM); 1279 } 1280 } 1281 1282 // ELF / PIC requires GOT in the EBX register before function calls via PLT 1283 // GOT pointer. 1284 if (!Subtarget->is64Bit() && 1285 TM.getRelocationModel() == Reloc::PIC_ && 1286 Subtarget->isPICStyleGOT()) { 1287 TargetRegisterClass *RC = X86::GR32RegisterClass; 1288 unsigned Base = getInstrInfo()->getGlobalBaseReg(&MF); 1289 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC); 1290 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted; 1291 Emitted = true; 1292 } 1293 1294 // Issue the call. 1295 unsigned CallOpc = CalleeOp 1296 ? (Subtarget->is64Bit() ? X86::CALL64r : X86::CALL32r) 1297 : (Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32); 1298 MachineInstrBuilder MIB = CalleeOp 1299 ? BuildMI(MBB, DL, TII.get(CallOpc)).addReg(CalleeOp) 1300 : BuildMI(MBB, DL, TII.get(CallOpc)).addGlobalAddress(GV); 1301 1302 // Add an implicit use GOT pointer in EBX. 1303 if (!Subtarget->is64Bit() && 1304 TM.getRelocationModel() == Reloc::PIC_ && 1305 Subtarget->isPICStyleGOT()) 1306 MIB.addReg(X86::EBX); 1307 1308 // Add implicit physical register uses to the call. 1309 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i) 1310 MIB.addReg(RegArgs[i]); 1311 1312 // Issue CALLSEQ_END 1313 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode(); 1314 BuildMI(MBB, DL, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0); 1315 1316 // Now handle call return value (if any). 1317 if (RetVT.getSimpleVT() != MVT::isVoid) { 1318 SmallVector<CCValAssign, 16> RVLocs; 1319 CCState CCInfo(CC, false, TM, RVLocs); 1320 CCInfo.AnalyzeCallResult(RetVT, RetCC_X86); 1321 1322 // Copy all of the result registers out of their specified physreg. 1323 assert(RVLocs.size() == 1 && "Can't handle multi-value calls!"); 1324 MVT CopyVT = RVLocs[0].getValVT(); 1325 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT); 1326 TargetRegisterClass *SrcRC = DstRC; 1327 1328 // If this is a call to a function that returns an fp value on the x87 fp 1329 // stack, but where we prefer to use the value in xmm registers, copy it 1330 // out as F80 and use a truncate to move it from fp stack reg to xmm reg. 1331 if ((RVLocs[0].getLocReg() == X86::ST0 || 1332 RVLocs[0].getLocReg() == X86::ST1) && 1333 isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) { 1334 CopyVT = MVT::f80; 1335 SrcRC = X86::RSTRegisterClass; 1336 DstRC = X86::RFP80RegisterClass; 1337 } 1338 1339 unsigned ResultReg = createResultReg(DstRC); 1340 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 1341 RVLocs[0].getLocReg(), DstRC, SrcRC); 1342 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted; 1343 Emitted = true; 1344 if (CopyVT != RVLocs[0].getValVT()) { 1345 // Round the F80 the right size, which also moves to the appropriate xmm 1346 // register. This is accomplished by storing the F80 value in memory and 1347 // then loading it back. Ewww... 1348 MVT ResVT = RVLocs[0].getValVT(); 1349 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; 1350 unsigned MemSize = ResVT.getSizeInBits()/8; 1351 int FI = MFI.CreateStackObject(MemSize, MemSize); 1352 addFrameReference(BuildMI(MBB, DL, TII.get(Opc)), FI).addReg(ResultReg); 1353 DstRC = ResVT == MVT::f32 1354 ? X86::FR32RegisterClass : X86::FR64RegisterClass; 1355 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm; 1356 ResultReg = createResultReg(DstRC); 1357 addFrameReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), FI); 1358 } 1359 1360 if (AndToI1) { 1361 // Mask out all but lowest bit for some call which produces an i1. 1362 unsigned AndResult = createResultReg(X86::GR8RegisterClass); 1363 BuildMI(MBB, DL, 1364 TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1); 1365 ResultReg = AndResult; 1366 } 1367 1368 UpdateValueMap(I, ResultReg); 1369 } 1370 1371 return true; 1372} 1373 1374 1375bool 1376X86FastISel::TargetSelectInstruction(Instruction *I) { 1377 switch (I->getOpcode()) { 1378 default: break; 1379 case Instruction::Load: 1380 return X86SelectLoad(I); 1381 case Instruction::Store: 1382 return X86SelectStore(I); 1383 case Instruction::ICmp: 1384 case Instruction::FCmp: 1385 return X86SelectCmp(I); 1386 case Instruction::ZExt: 1387 return X86SelectZExt(I); 1388 case Instruction::Br: 1389 return X86SelectBranch(I); 1390 case Instruction::Call: 1391 return X86SelectCall(I); 1392 case Instruction::LShr: 1393 case Instruction::AShr: 1394 case Instruction::Shl: 1395 return X86SelectShift(I); 1396 case Instruction::Select: 1397 return X86SelectSelect(I); 1398 case Instruction::Trunc: 1399 return X86SelectTrunc(I); 1400 case Instruction::FPExt: 1401 return X86SelectFPExt(I); 1402 case Instruction::FPTrunc: 1403 return X86SelectFPTrunc(I); 1404 case Instruction::ExtractValue: 1405 return X86SelectExtractValue(I); 1406 case Instruction::IntToPtr: // Deliberate fall-through. 1407 case Instruction::PtrToInt: { 1408 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 1409 MVT DstVT = TLI.getValueType(I->getType()); 1410 if (DstVT.bitsGT(SrcVT)) 1411 return X86SelectZExt(I); 1412 if (DstVT.bitsLT(SrcVT)) 1413 return X86SelectTrunc(I); 1414 unsigned Reg = getRegForValue(I->getOperand(0)); 1415 if (Reg == 0) return false; 1416 UpdateValueMap(I, Reg); 1417 return true; 1418 } 1419 } 1420 1421 return false; 1422} 1423 1424unsigned X86FastISel::TargetMaterializeConstant(Constant *C) { 1425 MVT VT; 1426 if (!isTypeLegal(C->getType(), VT)) 1427 return false; 1428 1429 // Get opcode and regclass of the output for the given load instruction. 1430 unsigned Opc = 0; 1431 const TargetRegisterClass *RC = NULL; 1432 switch (VT.getSimpleVT()) { 1433 default: return false; 1434 case MVT::i8: 1435 Opc = X86::MOV8rm; 1436 RC = X86::GR8RegisterClass; 1437 break; 1438 case MVT::i16: 1439 Opc = X86::MOV16rm; 1440 RC = X86::GR16RegisterClass; 1441 break; 1442 case MVT::i32: 1443 Opc = X86::MOV32rm; 1444 RC = X86::GR32RegisterClass; 1445 break; 1446 case MVT::i64: 1447 // Must be in x86-64 mode. 1448 Opc = X86::MOV64rm; 1449 RC = X86::GR64RegisterClass; 1450 break; 1451 case MVT::f32: 1452 if (Subtarget->hasSSE1()) { 1453 Opc = X86::MOVSSrm; 1454 RC = X86::FR32RegisterClass; 1455 } else { 1456 Opc = X86::LD_Fp32m; 1457 RC = X86::RFP32RegisterClass; 1458 } 1459 break; 1460 case MVT::f64: 1461 if (Subtarget->hasSSE2()) { 1462 Opc = X86::MOVSDrm; 1463 RC = X86::FR64RegisterClass; 1464 } else { 1465 Opc = X86::LD_Fp64m; 1466 RC = X86::RFP64RegisterClass; 1467 } 1468 break; 1469 case MVT::f80: 1470 // No f80 support yet. 1471 return false; 1472 } 1473 1474 // Materialize addresses with LEA instructions. 1475 if (isa<GlobalValue>(C)) { 1476 X86AddressMode AM; 1477 if (X86SelectAddress(C, AM, false)) { 1478 if (TLI.getPointerTy() == MVT::i32) 1479 Opc = X86::LEA32r; 1480 else 1481 Opc = X86::LEA64r; 1482 unsigned ResultReg = createResultReg(RC); 1483 addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM); 1484 return ResultReg; 1485 } 1486 return 0; 1487 } 1488 1489 // MachineConstantPool wants an explicit alignment. 1490 unsigned Align = TD.getPrefTypeAlignment(C->getType()); 1491 if (Align == 0) { 1492 // Alignment of vector types. FIXME! 1493 Align = TD.getTypeAllocSize(C->getType()); 1494 } 1495 1496 // x86-32 PIC requires a PIC base register for constant pools. 1497 unsigned PICBase = 0; 1498 if (TM.getRelocationModel() == Reloc::PIC_ && 1499 !Subtarget->is64Bit()) 1500 PICBase = getInstrInfo()->getGlobalBaseReg(&MF); 1501 1502 // Create the load from the constant pool. 1503 unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align); 1504 unsigned ResultReg = createResultReg(RC); 1505 addConstantPoolReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), MCPOffset, 1506 PICBase); 1507 1508 return ResultReg; 1509} 1510 1511unsigned X86FastISel::TargetMaterializeAlloca(AllocaInst *C) { 1512 // Fail on dynamic allocas. At this point, getRegForValue has already 1513 // checked its CSE maps, so if we're here trying to handle a dynamic 1514 // alloca, we're not going to succeed. X86SelectAddress has a 1515 // check for dynamic allocas, because it's called directly from 1516 // various places, but TargetMaterializeAlloca also needs a check 1517 // in order to avoid recursion between getRegForValue, 1518 // X86SelectAddrss, and TargetMaterializeAlloca. 1519 if (!StaticAllocaMap.count(C)) 1520 return 0; 1521 1522 X86AddressMode AM; 1523 if (!X86SelectAddress(C, AM, false)) 1524 return 0; 1525 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 1526 TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy()); 1527 unsigned ResultReg = createResultReg(RC); 1528 addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM); 1529 return ResultReg; 1530} 1531 1532namespace llvm { 1533 llvm::FastISel *X86::createFastISel(MachineFunction &mf, 1534 MachineModuleInfo *mmi, 1535 DwarfWriter *dw, 1536 DenseMap<const Value *, unsigned> &vm, 1537 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 1538 DenseMap<const AllocaInst *, int> &am 1539#ifndef NDEBUG 1540 , SmallSet<Instruction*, 8> &cil 1541#endif 1542 ) { 1543 return new X86FastISel(mf, mmi, dw, vm, bm, am 1544#ifndef NDEBUG 1545 , cil 1546#endif 1547 ); 1548 } 1549} 1550