X86FastISel.cpp revision eaf77254d4d6dd8dfc461c3e6078f44da881291c
1//===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the X86-specific support for the FastISel class. Much 11// of the target-specific code is generated by tablegen in the file 12// X86GenFastISel.inc, which is #included here. 13// 14//===----------------------------------------------------------------------===// 15 16#include "X86.h" 17#include "X86InstrBuilder.h" 18#include "X86ISelLowering.h" 19#include "X86RegisterInfo.h" 20#include "X86Subtarget.h" 21#include "X86TargetMachine.h" 22#include "llvm/CallingConv.h" 23#include "llvm/DerivedTypes.h" 24#include "llvm/GlobalVariable.h" 25#include "llvm/GlobalAlias.h" 26#include "llvm/Instructions.h" 27#include "llvm/IntrinsicInst.h" 28#include "llvm/Operator.h" 29#include "llvm/CodeGen/Analysis.h" 30#include "llvm/CodeGen/FastISel.h" 31#include "llvm/CodeGen/FunctionLoweringInfo.h" 32#include "llvm/CodeGen/MachineConstantPool.h" 33#include "llvm/CodeGen/MachineFrameInfo.h" 34#include "llvm/CodeGen/MachineRegisterInfo.h" 35#include "llvm/Support/CallSite.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/GetElementPtrTypeIterator.h" 38#include "llvm/Target/TargetOptions.h" 39using namespace llvm; 40 41namespace { 42 43class X86FastISel : public FastISel { 44 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can 45 /// make the right decision when generating code for different targets. 46 const X86Subtarget *Subtarget; 47 48 /// RegInfo - X86 register info. 49 /// 50 const X86RegisterInfo *RegInfo; 51 52 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87 53 /// floating point ops. 54 /// When SSE is available, use it for f32 operations. 55 /// When SSE2 is available, use it for f64 operations. 56 bool X86ScalarSSEf64; 57 bool X86ScalarSSEf32; 58 59public: 60 explicit X86FastISel(FunctionLoweringInfo &funcInfo, 61 const TargetLibraryInfo *libInfo) 62 : FastISel(funcInfo, libInfo) { 63 Subtarget = &TM.getSubtarget<X86Subtarget>(); 64 X86ScalarSSEf64 = Subtarget->hasSSE2(); 65 X86ScalarSSEf32 = Subtarget->hasSSE1(); 66 RegInfo = static_cast<const X86RegisterInfo*>(TM.getRegisterInfo()); 67 } 68 69 virtual bool TargetSelectInstruction(const Instruction *I); 70 71 /// TryToFoldLoad - The specified machine instr operand is a vreg, and that 72 /// vreg is being provided by the specified load instruction. If possible, 73 /// try to fold the load as an operand to the instruction, returning true if 74 /// possible. 75 virtual bool TryToFoldLoad(MachineInstr *MI, unsigned OpNo, 76 const LoadInst *LI); 77 78#include "X86GenFastISel.inc" 79 80private: 81 bool X86FastEmitCompare(const Value *LHS, const Value *RHS, EVT VT); 82 83 bool X86FastEmitLoad(EVT VT, const X86AddressMode &AM, unsigned &RR); 84 85 bool X86FastEmitStore(EVT VT, const Value *Val, const X86AddressMode &AM); 86 bool X86FastEmitStore(EVT VT, unsigned Val, const X86AddressMode &AM); 87 88 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, 89 unsigned &ResultReg); 90 91 bool X86SelectAddress(const Value *V, X86AddressMode &AM); 92 bool X86SelectCallAddress(const Value *V, X86AddressMode &AM); 93 94 bool X86SelectLoad(const Instruction *I); 95 96 bool X86SelectStore(const Instruction *I); 97 98 bool X86SelectRet(const Instruction *I); 99 100 bool X86SelectCmp(const Instruction *I); 101 102 bool X86SelectZExt(const Instruction *I); 103 104 bool X86SelectBranch(const Instruction *I); 105 106 bool X86SelectShift(const Instruction *I); 107 108 bool X86SelectSelect(const Instruction *I); 109 110 bool X86SelectTrunc(const Instruction *I); 111 112 bool X86SelectFPExt(const Instruction *I); 113 bool X86SelectFPTrunc(const Instruction *I); 114 115 bool X86VisitIntrinsicCall(const IntrinsicInst &I); 116 bool X86SelectCall(const Instruction *I); 117 118 bool DoSelectCall(const Instruction *I, const char *MemIntName); 119 120 const X86InstrInfo *getInstrInfo() const { 121 return getTargetMachine()->getInstrInfo(); 122 } 123 const X86TargetMachine *getTargetMachine() const { 124 return static_cast<const X86TargetMachine *>(&TM); 125 } 126 127 unsigned TargetMaterializeConstant(const Constant *C); 128 129 unsigned TargetMaterializeAlloca(const AllocaInst *C); 130 131 unsigned TargetMaterializeFloatZero(const ConstantFP *CF); 132 133 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is 134 /// computed in an SSE register, not on the X87 floating point stack. 135 bool isScalarFPTypeInSSEReg(EVT VT) const { 136 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 137 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 138 } 139 140 bool isTypeLegal(Type *Ty, MVT &VT, bool AllowI1 = false); 141 142 bool IsMemcpySmall(uint64_t Len); 143 144 bool TryEmitSmallMemcpy(X86AddressMode DestAM, 145 X86AddressMode SrcAM, uint64_t Len); 146}; 147 148} // end anonymous namespace. 149 150bool X86FastISel::isTypeLegal(Type *Ty, MVT &VT, bool AllowI1) { 151 EVT evt = TLI.getValueType(Ty, /*HandleUnknown=*/true); 152 if (evt == MVT::Other || !evt.isSimple()) 153 // Unhandled type. Halt "fast" selection and bail. 154 return false; 155 156 VT = evt.getSimpleVT(); 157 // For now, require SSE/SSE2 for performing floating-point operations, 158 // since x87 requires additional work. 159 if (VT == MVT::f64 && !X86ScalarSSEf64) 160 return false; 161 if (VT == MVT::f32 && !X86ScalarSSEf32) 162 return false; 163 // Similarly, no f80 support yet. 164 if (VT == MVT::f80) 165 return false; 166 // We only handle legal types. For example, on x86-32 the instruction 167 // selector contains all of the 64-bit instructions from x86-64, 168 // under the assumption that i64 won't be used if the target doesn't 169 // support it. 170 return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT); 171} 172 173#include "X86GenCallingConv.inc" 174 175/// X86FastEmitLoad - Emit a machine instruction to load a value of type VT. 176/// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV. 177/// Return true and the result register by reference if it is possible. 178bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM, 179 unsigned &ResultReg) { 180 // Get opcode and regclass of the output for the given load instruction. 181 unsigned Opc = 0; 182 const TargetRegisterClass *RC = NULL; 183 switch (VT.getSimpleVT().SimpleTy) { 184 default: return false; 185 case MVT::i1: 186 case MVT::i8: 187 Opc = X86::MOV8rm; 188 RC = &X86::GR8RegClass; 189 break; 190 case MVT::i16: 191 Opc = X86::MOV16rm; 192 RC = &X86::GR16RegClass; 193 break; 194 case MVT::i32: 195 Opc = X86::MOV32rm; 196 RC = &X86::GR32RegClass; 197 break; 198 case MVT::i64: 199 // Must be in x86-64 mode. 200 Opc = X86::MOV64rm; 201 RC = &X86::GR64RegClass; 202 break; 203 case MVT::f32: 204 if (X86ScalarSSEf32) { 205 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm; 206 RC = &X86::FR32RegClass; 207 } else { 208 Opc = X86::LD_Fp32m; 209 RC = &X86::RFP32RegClass; 210 } 211 break; 212 case MVT::f64: 213 if (X86ScalarSSEf64) { 214 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm; 215 RC = &X86::FR64RegClass; 216 } else { 217 Opc = X86::LD_Fp64m; 218 RC = &X86::RFP64RegClass; 219 } 220 break; 221 case MVT::f80: 222 // No f80 support yet. 223 return false; 224 } 225 226 ResultReg = createResultReg(RC); 227 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, 228 DL, TII.get(Opc), ResultReg), AM); 229 return true; 230} 231 232/// X86FastEmitStore - Emit a machine instruction to store a value Val of 233/// type VT. The address is either pre-computed, consisted of a base ptr, Ptr 234/// and a displacement offset, or a GlobalAddress, 235/// i.e. V. Return true if it is possible. 236bool 237X86FastISel::X86FastEmitStore(EVT VT, unsigned Val, const X86AddressMode &AM) { 238 // Get opcode and regclass of the output for the given store instruction. 239 unsigned Opc = 0; 240 switch (VT.getSimpleVT().SimpleTy) { 241 case MVT::f80: // No f80 support yet. 242 default: return false; 243 case MVT::i1: { 244 // Mask out all but lowest bit. 245 unsigned AndResult = createResultReg(&X86::GR8RegClass); 246 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 247 TII.get(X86::AND8ri), AndResult).addReg(Val).addImm(1); 248 Val = AndResult; 249 } 250 // FALLTHROUGH, handling i1 as i8. 251 case MVT::i8: Opc = X86::MOV8mr; break; 252 case MVT::i16: Opc = X86::MOV16mr; break; 253 case MVT::i32: Opc = X86::MOV32mr; break; 254 case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode. 255 case MVT::f32: 256 Opc = X86ScalarSSEf32 ? 257 (Subtarget->hasAVX() ? X86::VMOVSSmr : X86::MOVSSmr) : X86::ST_Fp32m; 258 break; 259 case MVT::f64: 260 Opc = X86ScalarSSEf64 ? 261 (Subtarget->hasAVX() ? X86::VMOVSDmr : X86::MOVSDmr) : X86::ST_Fp64m; 262 break; 263 case MVT::v4f32: 264 Opc = X86::MOVAPSmr; 265 break; 266 case MVT::v2f64: 267 Opc = X86::MOVAPDmr; 268 break; 269 case MVT::v4i32: 270 case MVT::v2i64: 271 case MVT::v8i16: 272 case MVT::v16i8: 273 Opc = X86::MOVDQAmr; 274 break; 275 } 276 277 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, 278 DL, TII.get(Opc)), AM).addReg(Val); 279 return true; 280} 281 282bool X86FastISel::X86FastEmitStore(EVT VT, const Value *Val, 283 const X86AddressMode &AM) { 284 // Handle 'null' like i32/i64 0. 285 if (isa<ConstantPointerNull>(Val)) 286 Val = Constant::getNullValue(TD.getIntPtrType(Val->getContext())); 287 288 // If this is a store of a simple constant, fold the constant into the store. 289 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Val)) { 290 unsigned Opc = 0; 291 bool Signed = true; 292 switch (VT.getSimpleVT().SimpleTy) { 293 default: break; 294 case MVT::i1: Signed = false; // FALLTHROUGH to handle as i8. 295 case MVT::i8: Opc = X86::MOV8mi; break; 296 case MVT::i16: Opc = X86::MOV16mi; break; 297 case MVT::i32: Opc = X86::MOV32mi; break; 298 case MVT::i64: 299 // Must be a 32-bit sign extended value. 300 if (isInt<32>(CI->getSExtValue())) 301 Opc = X86::MOV64mi32; 302 break; 303 } 304 305 if (Opc) { 306 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, 307 DL, TII.get(Opc)), AM) 308 .addImm(Signed ? (uint64_t) CI->getSExtValue() : 309 CI->getZExtValue()); 310 return true; 311 } 312 } 313 314 unsigned ValReg = getRegForValue(Val); 315 if (ValReg == 0) 316 return false; 317 318 return X86FastEmitStore(VT, ValReg, AM); 319} 320 321/// X86FastEmitExtend - Emit a machine instruction to extend a value Src of 322/// type SrcVT to type DstVT using the specified extension opcode Opc (e.g. 323/// ISD::SIGN_EXTEND). 324bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, 325 unsigned Src, EVT SrcVT, 326 unsigned &ResultReg) { 327 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, 328 Src, /*TODO: Kill=*/false); 329 330 if (RR != 0) { 331 ResultReg = RR; 332 return true; 333 } else 334 return false; 335} 336 337/// X86SelectAddress - Attempt to fill in an address from the given value. 338/// 339bool X86FastISel::X86SelectAddress(const Value *V, X86AddressMode &AM) { 340 const User *U = NULL; 341 unsigned Opcode = Instruction::UserOp1; 342 if (const Instruction *I = dyn_cast<Instruction>(V)) { 343 // Don't walk into other basic blocks; it's possible we haven't 344 // visited them yet, so the instructions may not yet be assigned 345 // virtual registers. 346 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(V)) || 347 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) { 348 Opcode = I->getOpcode(); 349 U = I; 350 } 351 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(V)) { 352 Opcode = C->getOpcode(); 353 U = C; 354 } 355 356 if (PointerType *Ty = dyn_cast<PointerType>(V->getType())) 357 if (Ty->getAddressSpace() > 255) 358 // Fast instruction selection doesn't support the special 359 // address spaces. 360 return false; 361 362 switch (Opcode) { 363 default: break; 364 case Instruction::BitCast: 365 // Look past bitcasts. 366 return X86SelectAddress(U->getOperand(0), AM); 367 368 case Instruction::IntToPtr: 369 // Look past no-op inttoptrs. 370 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy()) 371 return X86SelectAddress(U->getOperand(0), AM); 372 break; 373 374 case Instruction::PtrToInt: 375 // Look past no-op ptrtoints. 376 if (TLI.getValueType(U->getType()) == TLI.getPointerTy()) 377 return X86SelectAddress(U->getOperand(0), AM); 378 break; 379 380 case Instruction::Alloca: { 381 // Do static allocas. 382 const AllocaInst *A = cast<AllocaInst>(V); 383 DenseMap<const AllocaInst*, int>::iterator SI = 384 FuncInfo.StaticAllocaMap.find(A); 385 if (SI != FuncInfo.StaticAllocaMap.end()) { 386 AM.BaseType = X86AddressMode::FrameIndexBase; 387 AM.Base.FrameIndex = SI->second; 388 return true; 389 } 390 break; 391 } 392 393 case Instruction::Add: { 394 // Adds of constants are common and easy enough. 395 if (const ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) { 396 uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue(); 397 // They have to fit in the 32-bit signed displacement field though. 398 if (isInt<32>(Disp)) { 399 AM.Disp = (uint32_t)Disp; 400 return X86SelectAddress(U->getOperand(0), AM); 401 } 402 } 403 break; 404 } 405 406 case Instruction::GetElementPtr: { 407 X86AddressMode SavedAM = AM; 408 409 // Pattern-match simple GEPs. 410 uint64_t Disp = (int32_t)AM.Disp; 411 unsigned IndexReg = AM.IndexReg; 412 unsigned Scale = AM.Scale; 413 gep_type_iterator GTI = gep_type_begin(U); 414 // Iterate through the indices, folding what we can. Constants can be 415 // folded, and one dynamic index can be handled, if the scale is supported. 416 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); 417 i != e; ++i, ++GTI) { 418 const Value *Op = *i; 419 if (StructType *STy = dyn_cast<StructType>(*GTI)) { 420 const StructLayout *SL = TD.getStructLayout(STy); 421 Disp += SL->getElementOffset(cast<ConstantInt>(Op)->getZExtValue()); 422 continue; 423 } 424 425 // A array/variable index is always of the form i*S where S is the 426 // constant scale size. See if we can push the scale into immediates. 427 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType()); 428 for (;;) { 429 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) { 430 // Constant-offset addressing. 431 Disp += CI->getSExtValue() * S; 432 break; 433 } 434 if (isa<AddOperator>(Op) && 435 (!isa<Instruction>(Op) || 436 FuncInfo.MBBMap[cast<Instruction>(Op)->getParent()] 437 == FuncInfo.MBB) && 438 isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) { 439 // An add (in the same block) with a constant operand. Fold the 440 // constant. 441 ConstantInt *CI = 442 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1)); 443 Disp += CI->getSExtValue() * S; 444 // Iterate on the other operand. 445 Op = cast<AddOperator>(Op)->getOperand(0); 446 continue; 447 } 448 if (IndexReg == 0 && 449 (!AM.GV || !Subtarget->isPICStyleRIPRel()) && 450 (S == 1 || S == 2 || S == 4 || S == 8)) { 451 // Scaled-index addressing. 452 Scale = S; 453 IndexReg = getRegForGEPIndex(Op).first; 454 if (IndexReg == 0) 455 return false; 456 break; 457 } 458 // Unsupported. 459 goto unsupported_gep; 460 } 461 } 462 // Check for displacement overflow. 463 if (!isInt<32>(Disp)) 464 break; 465 // Ok, the GEP indices were covered by constant-offset and scaled-index 466 // addressing. Update the address state and move on to examining the base. 467 AM.IndexReg = IndexReg; 468 AM.Scale = Scale; 469 AM.Disp = (uint32_t)Disp; 470 if (X86SelectAddress(U->getOperand(0), AM)) 471 return true; 472 473 // If we couldn't merge the gep value into this addr mode, revert back to 474 // our address and just match the value instead of completely failing. 475 AM = SavedAM; 476 break; 477 unsupported_gep: 478 // Ok, the GEP indices weren't all covered. 479 break; 480 } 481 } 482 483 // Handle constant address. 484 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) { 485 // Can't handle alternate code models yet. 486 if (TM.getCodeModel() != CodeModel::Small) 487 return false; 488 489 // Can't handle TLS yet. 490 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV)) 491 if (GVar->isThreadLocal()) 492 return false; 493 494 // Can't handle TLS yet, part 2 (this is slightly crazy, but this is how 495 // it works...). 496 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 497 if (const GlobalVariable *GVar = 498 dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false))) 499 if (GVar->isThreadLocal()) 500 return false; 501 502 // RIP-relative addresses can't have additional register operands, so if 503 // we've already folded stuff into the addressing mode, just force the 504 // global value into its own register, which we can use as the basereg. 505 if (!Subtarget->isPICStyleRIPRel() || 506 (AM.Base.Reg == 0 && AM.IndexReg == 0)) { 507 // Okay, we've committed to selecting this global. Set up the address. 508 AM.GV = GV; 509 510 // Allow the subtarget to classify the global. 511 unsigned char GVFlags = Subtarget->ClassifyGlobalReference(GV, TM); 512 513 // If this reference is relative to the pic base, set it now. 514 if (isGlobalRelativeToPICBase(GVFlags)) { 515 // FIXME: How do we know Base.Reg is free?? 516 AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF); 517 } 518 519 // Unless the ABI requires an extra load, return a direct reference to 520 // the global. 521 if (!isGlobalStubReference(GVFlags)) { 522 if (Subtarget->isPICStyleRIPRel()) { 523 // Use rip-relative addressing if we can. Above we verified that the 524 // base and index registers are unused. 525 assert(AM.Base.Reg == 0 && AM.IndexReg == 0); 526 AM.Base.Reg = X86::RIP; 527 } 528 AM.GVOpFlags = GVFlags; 529 return true; 530 } 531 532 // Ok, we need to do a load from a stub. If we've already loaded from 533 // this stub, reuse the loaded pointer, otherwise emit the load now. 534 DenseMap<const Value*, unsigned>::iterator I = LocalValueMap.find(V); 535 unsigned LoadReg; 536 if (I != LocalValueMap.end() && I->second != 0) { 537 LoadReg = I->second; 538 } else { 539 // Issue load from stub. 540 unsigned Opc = 0; 541 const TargetRegisterClass *RC = NULL; 542 X86AddressMode StubAM; 543 StubAM.Base.Reg = AM.Base.Reg; 544 StubAM.GV = GV; 545 StubAM.GVOpFlags = GVFlags; 546 547 // Prepare for inserting code in the local-value area. 548 SavePoint SaveInsertPt = enterLocalValueArea(); 549 550 if (TLI.getPointerTy() == MVT::i64) { 551 Opc = X86::MOV64rm; 552 RC = &X86::GR64RegClass; 553 554 if (Subtarget->isPICStyleRIPRel()) 555 StubAM.Base.Reg = X86::RIP; 556 } else { 557 Opc = X86::MOV32rm; 558 RC = &X86::GR32RegClass; 559 } 560 561 LoadReg = createResultReg(RC); 562 MachineInstrBuilder LoadMI = 563 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), LoadReg); 564 addFullAddress(LoadMI, StubAM); 565 566 // Ok, back to normal mode. 567 leaveLocalValueArea(SaveInsertPt); 568 569 // Prevent loading GV stub multiple times in same MBB. 570 LocalValueMap[V] = LoadReg; 571 } 572 573 // Now construct the final address. Note that the Disp, Scale, 574 // and Index values may already be set here. 575 AM.Base.Reg = LoadReg; 576 AM.GV = 0; 577 return true; 578 } 579 } 580 581 // If all else fails, try to materialize the value in a register. 582 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) { 583 if (AM.Base.Reg == 0) { 584 AM.Base.Reg = getRegForValue(V); 585 return AM.Base.Reg != 0; 586 } 587 if (AM.IndexReg == 0) { 588 assert(AM.Scale == 1 && "Scale with no index!"); 589 AM.IndexReg = getRegForValue(V); 590 return AM.IndexReg != 0; 591 } 592 } 593 594 return false; 595} 596 597/// X86SelectCallAddress - Attempt to fill in an address from the given value. 598/// 599bool X86FastISel::X86SelectCallAddress(const Value *V, X86AddressMode &AM) { 600 const User *U = NULL; 601 unsigned Opcode = Instruction::UserOp1; 602 if (const Instruction *I = dyn_cast<Instruction>(V)) { 603 Opcode = I->getOpcode(); 604 U = I; 605 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(V)) { 606 Opcode = C->getOpcode(); 607 U = C; 608 } 609 610 switch (Opcode) { 611 default: break; 612 case Instruction::BitCast: 613 // Look past bitcasts. 614 return X86SelectCallAddress(U->getOperand(0), AM); 615 616 case Instruction::IntToPtr: 617 // Look past no-op inttoptrs. 618 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy()) 619 return X86SelectCallAddress(U->getOperand(0), AM); 620 break; 621 622 case Instruction::PtrToInt: 623 // Look past no-op ptrtoints. 624 if (TLI.getValueType(U->getType()) == TLI.getPointerTy()) 625 return X86SelectCallAddress(U->getOperand(0), AM); 626 break; 627 } 628 629 // Handle constant address. 630 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) { 631 // Can't handle alternate code models yet. 632 if (TM.getCodeModel() != CodeModel::Small) 633 return false; 634 635 // RIP-relative addresses can't have additional register operands. 636 if (Subtarget->isPICStyleRIPRel() && 637 (AM.Base.Reg != 0 || AM.IndexReg != 0)) 638 return false; 639 640 // Can't handle DLLImport. 641 if (GV->hasDLLImportLinkage()) 642 return false; 643 644 // Can't handle TLS. 645 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV)) 646 if (GVar->isThreadLocal()) 647 return false; 648 649 // Okay, we've committed to selecting this global. Set up the basic address. 650 AM.GV = GV; 651 652 // No ABI requires an extra load for anything other than DLLImport, which 653 // we rejected above. Return a direct reference to the global. 654 if (Subtarget->isPICStyleRIPRel()) { 655 // Use rip-relative addressing if we can. Above we verified that the 656 // base and index registers are unused. 657 assert(AM.Base.Reg == 0 && AM.IndexReg == 0); 658 AM.Base.Reg = X86::RIP; 659 } else if (Subtarget->isPICStyleStubPIC()) { 660 AM.GVOpFlags = X86II::MO_PIC_BASE_OFFSET; 661 } else if (Subtarget->isPICStyleGOT()) { 662 AM.GVOpFlags = X86II::MO_GOTOFF; 663 } 664 665 return true; 666 } 667 668 // If all else fails, try to materialize the value in a register. 669 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) { 670 if (AM.Base.Reg == 0) { 671 AM.Base.Reg = getRegForValue(V); 672 return AM.Base.Reg != 0; 673 } 674 if (AM.IndexReg == 0) { 675 assert(AM.Scale == 1 && "Scale with no index!"); 676 AM.IndexReg = getRegForValue(V); 677 return AM.IndexReg != 0; 678 } 679 } 680 681 return false; 682} 683 684 685/// X86SelectStore - Select and emit code to implement store instructions. 686bool X86FastISel::X86SelectStore(const Instruction *I) { 687 // Atomic stores need special handling. 688 const StoreInst *S = cast<StoreInst>(I); 689 690 if (S->isAtomic()) 691 return false; 692 693 unsigned SABIAlignment = 694 TD.getABITypeAlignment(S->getValueOperand()->getType()); 695 if (S->getAlignment() != 0 && S->getAlignment() < SABIAlignment) 696 return false; 697 698 MVT VT; 699 if (!isTypeLegal(I->getOperand(0)->getType(), VT, /*AllowI1=*/true)) 700 return false; 701 702 X86AddressMode AM; 703 if (!X86SelectAddress(I->getOperand(1), AM)) 704 return false; 705 706 return X86FastEmitStore(VT, I->getOperand(0), AM); 707} 708 709/// X86SelectRet - Select and emit code to implement ret instructions. 710bool X86FastISel::X86SelectRet(const Instruction *I) { 711 const ReturnInst *Ret = cast<ReturnInst>(I); 712 const Function &F = *I->getParent()->getParent(); 713 const X86MachineFunctionInfo *X86MFInfo = 714 FuncInfo.MF->getInfo<X86MachineFunctionInfo>(); 715 716 if (!FuncInfo.CanLowerReturn) 717 return false; 718 719 CallingConv::ID CC = F.getCallingConv(); 720 if (CC != CallingConv::C && 721 CC != CallingConv::Fast && 722 CC != CallingConv::X86_FastCall) 723 return false; 724 725 if (Subtarget->isTargetWin64()) 726 return false; 727 728 // Don't handle popping bytes on return for now. 729 if (X86MFInfo->getBytesToPopOnReturn() != 0) 730 return 0; 731 732 // fastcc with -tailcallopt is intended to provide a guaranteed 733 // tail call optimization. Fastisel doesn't know how to do that. 734 if (CC == CallingConv::Fast && TM.Options.GuaranteedTailCallOpt) 735 return false; 736 737 // Let SDISel handle vararg functions. 738 if (F.isVarArg()) 739 return false; 740 741 if (Ret->getNumOperands() > 0) { 742 SmallVector<ISD::OutputArg, 4> Outs; 743 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 744 Outs, TLI); 745 746 // Analyze operands of the call, assigning locations to each operand. 747 SmallVector<CCValAssign, 16> ValLocs; 748 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs, 749 I->getContext()); 750 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 751 752 const Value *RV = Ret->getOperand(0); 753 unsigned Reg = getRegForValue(RV); 754 if (Reg == 0) 755 return false; 756 757 // Only handle a single return value for now. 758 if (ValLocs.size() != 1) 759 return false; 760 761 CCValAssign &VA = ValLocs[0]; 762 763 // Don't bother handling odd stuff for now. 764 if (VA.getLocInfo() != CCValAssign::Full) 765 return false; 766 // Only handle register returns for now. 767 if (!VA.isRegLoc()) 768 return false; 769 770 // The calling-convention tables for x87 returns don't tell 771 // the whole story. 772 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 773 return false; 774 775 unsigned SrcReg = Reg + VA.getValNo(); 776 EVT SrcVT = TLI.getValueType(RV->getType()); 777 EVT DstVT = VA.getValVT(); 778 // Special handling for extended integers. 779 if (SrcVT != DstVT) { 780 if (SrcVT != MVT::i1 && SrcVT != MVT::i8 && SrcVT != MVT::i16) 781 return false; 782 783 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) 784 return false; 785 786 assert(DstVT == MVT::i32 && "X86 should always ext to i32"); 787 788 if (SrcVT == MVT::i1) { 789 if (Outs[0].Flags.isSExt()) 790 return false; 791 SrcReg = FastEmitZExtFromI1(MVT::i8, SrcReg, /*TODO: Kill=*/false); 792 SrcVT = MVT::i8; 793 } 794 unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND : 795 ISD::SIGN_EXTEND; 796 SrcReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, 797 SrcReg, /*TODO: Kill=*/false); 798 } 799 800 // Make the copy. 801 unsigned DstReg = VA.getLocReg(); 802 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg); 803 // Avoid a cross-class copy. This is very unlikely. 804 if (!SrcRC->contains(DstReg)) 805 return false; 806 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 807 DstReg).addReg(SrcReg); 808 809 // Mark the register as live out of the function. 810 MRI.addLiveOut(VA.getLocReg()); 811 } 812 813 // The x86-64 ABI for returning structs by value requires that we copy 814 // the sret argument into %rax for the return. We saved the argument into 815 // a virtual register in the entry block, so now we copy the value out 816 // and into %rax. 817 if (Subtarget->is64Bit() && F.hasStructRetAttr()) { 818 unsigned Reg = X86MFInfo->getSRetReturnReg(); 819 assert(Reg && 820 "SRetReturnReg should have been set in LowerFormalArguments()!"); 821 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 822 X86::RAX).addReg(Reg); 823 MRI.addLiveOut(X86::RAX); 824 } 825 826 // Now emit the RET. 827 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::RET)); 828 return true; 829} 830 831/// X86SelectLoad - Select and emit code to implement load instructions. 832/// 833bool X86FastISel::X86SelectLoad(const Instruction *I) { 834 // Atomic loads need special handling. 835 if (cast<LoadInst>(I)->isAtomic()) 836 return false; 837 838 MVT VT; 839 if (!isTypeLegal(I->getType(), VT, /*AllowI1=*/true)) 840 return false; 841 842 X86AddressMode AM; 843 if (!X86SelectAddress(I->getOperand(0), AM)) 844 return false; 845 846 unsigned ResultReg = 0; 847 if (X86FastEmitLoad(VT, AM, ResultReg)) { 848 UpdateValueMap(I, ResultReg); 849 return true; 850 } 851 return false; 852} 853 854static unsigned X86ChooseCmpOpcode(EVT VT, const X86Subtarget *Subtarget) { 855 bool HasAVX = Subtarget->hasAVX(); 856 bool X86ScalarSSEf32 = Subtarget->hasSSE1(); 857 bool X86ScalarSSEf64 = Subtarget->hasSSE2(); 858 859 switch (VT.getSimpleVT().SimpleTy) { 860 default: return 0; 861 case MVT::i8: return X86::CMP8rr; 862 case MVT::i16: return X86::CMP16rr; 863 case MVT::i32: return X86::CMP32rr; 864 case MVT::i64: return X86::CMP64rr; 865 case MVT::f32: 866 return X86ScalarSSEf32 ? (HasAVX ? X86::VUCOMISSrr : X86::UCOMISSrr) : 0; 867 case MVT::f64: 868 return X86ScalarSSEf64 ? (HasAVX ? X86::VUCOMISDrr : X86::UCOMISDrr) : 0; 869 } 870} 871 872/// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS 873/// of the comparison, return an opcode that works for the compare (e.g. 874/// CMP32ri) otherwise return 0. 875static unsigned X86ChooseCmpImmediateOpcode(EVT VT, const ConstantInt *RHSC) { 876 switch (VT.getSimpleVT().SimpleTy) { 877 // Otherwise, we can't fold the immediate into this comparison. 878 default: return 0; 879 case MVT::i8: return X86::CMP8ri; 880 case MVT::i16: return X86::CMP16ri; 881 case MVT::i32: return X86::CMP32ri; 882 case MVT::i64: 883 // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext 884 // field. 885 if ((int)RHSC->getSExtValue() == RHSC->getSExtValue()) 886 return X86::CMP64ri32; 887 return 0; 888 } 889} 890 891bool X86FastISel::X86FastEmitCompare(const Value *Op0, const Value *Op1, 892 EVT VT) { 893 unsigned Op0Reg = getRegForValue(Op0); 894 if (Op0Reg == 0) return false; 895 896 // Handle 'null' like i32/i64 0. 897 if (isa<ConstantPointerNull>(Op1)) 898 Op1 = Constant::getNullValue(TD.getIntPtrType(Op0->getContext())); 899 900 // We have two options: compare with register or immediate. If the RHS of 901 // the compare is an immediate that we can fold into this compare, use 902 // CMPri, otherwise use CMPrr. 903 if (const ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) { 904 if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) { 905 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CompareImmOpc)) 906 .addReg(Op0Reg) 907 .addImm(Op1C->getSExtValue()); 908 return true; 909 } 910 } 911 912 unsigned CompareOpc = X86ChooseCmpOpcode(VT, Subtarget); 913 if (CompareOpc == 0) return false; 914 915 unsigned Op1Reg = getRegForValue(Op1); 916 if (Op1Reg == 0) return false; 917 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CompareOpc)) 918 .addReg(Op0Reg) 919 .addReg(Op1Reg); 920 921 return true; 922} 923 924bool X86FastISel::X86SelectCmp(const Instruction *I) { 925 const CmpInst *CI = cast<CmpInst>(I); 926 927 MVT VT; 928 if (!isTypeLegal(I->getOperand(0)->getType(), VT)) 929 return false; 930 931 unsigned ResultReg = createResultReg(&X86::GR8RegClass); 932 unsigned SetCCOpc; 933 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0. 934 switch (CI->getPredicate()) { 935 case CmpInst::FCMP_OEQ: { 936 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT)) 937 return false; 938 939 unsigned EReg = createResultReg(&X86::GR8RegClass); 940 unsigned NPReg = createResultReg(&X86::GR8RegClass); 941 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETEr), EReg); 942 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 943 TII.get(X86::SETNPr), NPReg); 944 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 945 TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg); 946 UpdateValueMap(I, ResultReg); 947 return true; 948 } 949 case CmpInst::FCMP_UNE: { 950 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT)) 951 return false; 952 953 unsigned NEReg = createResultReg(&X86::GR8RegClass); 954 unsigned PReg = createResultReg(&X86::GR8RegClass); 955 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETNEr), NEReg); 956 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETPr), PReg); 957 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::OR8rr),ResultReg) 958 .addReg(PReg).addReg(NEReg); 959 UpdateValueMap(I, ResultReg); 960 return true; 961 } 962 case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break; 963 case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break; 964 case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break; 965 case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break; 966 case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break; 967 case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break; 968 case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break; 969 case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break; 970 case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break; 971 case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break; 972 case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break; 973 case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break; 974 975 case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break; 976 case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break; 977 case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break; 978 case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break; 979 case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break; 980 case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break; 981 case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break; 982 case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break; 983 case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break; 984 case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break; 985 default: 986 return false; 987 } 988 989 const Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1); 990 if (SwapArgs) 991 std::swap(Op0, Op1); 992 993 // Emit a compare of Op0/Op1. 994 if (!X86FastEmitCompare(Op0, Op1, VT)) 995 return false; 996 997 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(SetCCOpc), ResultReg); 998 UpdateValueMap(I, ResultReg); 999 return true; 1000} 1001 1002bool X86FastISel::X86SelectZExt(const Instruction *I) { 1003 // Handle zero-extension from i1 to i8, which is common. 1004 if (!I->getOperand(0)->getType()->isIntegerTy(1)) 1005 return false; 1006 1007 EVT DstVT = TLI.getValueType(I->getType()); 1008 if (!TLI.isTypeLegal(DstVT)) 1009 return false; 1010 1011 unsigned ResultReg = getRegForValue(I->getOperand(0)); 1012 if (ResultReg == 0) 1013 return false; 1014 1015 // Set the high bits to zero. 1016 ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg, /*TODO: Kill=*/false); 1017 if (ResultReg == 0) 1018 return false; 1019 1020 if (DstVT != MVT::i8) { 1021 ResultReg = FastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::ZERO_EXTEND, 1022 ResultReg, /*Kill=*/true); 1023 if (ResultReg == 0) 1024 return false; 1025 } 1026 1027 UpdateValueMap(I, ResultReg); 1028 return true; 1029} 1030 1031 1032bool X86FastISel::X86SelectBranch(const Instruction *I) { 1033 // Unconditional branches are selected by tablegen-generated code. 1034 // Handle a conditional branch. 1035 const BranchInst *BI = cast<BranchInst>(I); 1036 MachineBasicBlock *TrueMBB = FuncInfo.MBBMap[BI->getSuccessor(0)]; 1037 MachineBasicBlock *FalseMBB = FuncInfo.MBBMap[BI->getSuccessor(1)]; 1038 1039 // Fold the common case of a conditional branch with a comparison 1040 // in the same block (values defined on other blocks may not have 1041 // initialized registers). 1042 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) { 1043 if (CI->hasOneUse() && CI->getParent() == I->getParent()) { 1044 EVT VT = TLI.getValueType(CI->getOperand(0)->getType()); 1045 1046 // Try to take advantage of fallthrough opportunities. 1047 CmpInst::Predicate Predicate = CI->getPredicate(); 1048 if (FuncInfo.MBB->isLayoutSuccessor(TrueMBB)) { 1049 std::swap(TrueMBB, FalseMBB); 1050 Predicate = CmpInst::getInversePredicate(Predicate); 1051 } 1052 1053 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0. 1054 unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA" 1055 1056 switch (Predicate) { 1057 case CmpInst::FCMP_OEQ: 1058 std::swap(TrueMBB, FalseMBB); 1059 Predicate = CmpInst::FCMP_UNE; 1060 // FALL THROUGH 1061 case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE_4; break; 1062 case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA_4; break; 1063 case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE_4; break; 1064 case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA_4; break; 1065 case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE_4; break; 1066 case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE_4; break; 1067 case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP_4; break; 1068 case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP_4; break; 1069 case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE_4; break; 1070 case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB_4; break; 1071 case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE_4; break; 1072 case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break; 1073 case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break; 1074 1075 case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE_4; break; 1076 case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE_4; break; 1077 case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA_4; break; 1078 case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE_4; break; 1079 case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break; 1080 case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break; 1081 case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG_4; break; 1082 case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE_4; break; 1083 case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL_4; break; 1084 case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE_4; break; 1085 default: 1086 return false; 1087 } 1088 1089 const Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1); 1090 if (SwapArgs) 1091 std::swap(Op0, Op1); 1092 1093 // Emit a compare of the LHS and RHS, setting the flags. 1094 if (!X86FastEmitCompare(Op0, Op1, VT)) 1095 return false; 1096 1097 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BranchOpc)) 1098 .addMBB(TrueMBB); 1099 1100 if (Predicate == CmpInst::FCMP_UNE) { 1101 // X86 requires a second branch to handle UNE (and OEQ, 1102 // which is mapped to UNE above). 1103 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::JP_4)) 1104 .addMBB(TrueMBB); 1105 } 1106 1107 FastEmitBranch(FalseMBB, DL); 1108 FuncInfo.MBB->addSuccessor(TrueMBB); 1109 return true; 1110 } 1111 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) { 1112 // Handle things like "%cond = trunc i32 %X to i1 / br i1 %cond", which 1113 // typically happen for _Bool and C++ bools. 1114 MVT SourceVT; 1115 if (TI->hasOneUse() && TI->getParent() == I->getParent() && 1116 isTypeLegal(TI->getOperand(0)->getType(), SourceVT)) { 1117 unsigned TestOpc = 0; 1118 switch (SourceVT.SimpleTy) { 1119 default: break; 1120 case MVT::i8: TestOpc = X86::TEST8ri; break; 1121 case MVT::i16: TestOpc = X86::TEST16ri; break; 1122 case MVT::i32: TestOpc = X86::TEST32ri; break; 1123 case MVT::i64: TestOpc = X86::TEST64ri32; break; 1124 } 1125 if (TestOpc) { 1126 unsigned OpReg = getRegForValue(TI->getOperand(0)); 1127 if (OpReg == 0) return false; 1128 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TestOpc)) 1129 .addReg(OpReg).addImm(1); 1130 1131 unsigned JmpOpc = X86::JNE_4; 1132 if (FuncInfo.MBB->isLayoutSuccessor(TrueMBB)) { 1133 std::swap(TrueMBB, FalseMBB); 1134 JmpOpc = X86::JE_4; 1135 } 1136 1137 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(JmpOpc)) 1138 .addMBB(TrueMBB); 1139 FastEmitBranch(FalseMBB, DL); 1140 FuncInfo.MBB->addSuccessor(TrueMBB); 1141 return true; 1142 } 1143 } 1144 } 1145 1146 // Otherwise do a clumsy setcc and re-test it. 1147 // Note that i1 essentially gets ANY_EXTEND'ed to i8 where it isn't used 1148 // in an explicit cast, so make sure to handle that correctly. 1149 unsigned OpReg = getRegForValue(BI->getCondition()); 1150 if (OpReg == 0) return false; 1151 1152 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8ri)) 1153 .addReg(OpReg).addImm(1); 1154 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::JNE_4)) 1155 .addMBB(TrueMBB); 1156 FastEmitBranch(FalseMBB, DL); 1157 FuncInfo.MBB->addSuccessor(TrueMBB); 1158 return true; 1159} 1160 1161bool X86FastISel::X86SelectShift(const Instruction *I) { 1162 unsigned CReg = 0, OpReg = 0; 1163 const TargetRegisterClass *RC = NULL; 1164 if (I->getType()->isIntegerTy(8)) { 1165 CReg = X86::CL; 1166 RC = &X86::GR8RegClass; 1167 switch (I->getOpcode()) { 1168 case Instruction::LShr: OpReg = X86::SHR8rCL; break; 1169 case Instruction::AShr: OpReg = X86::SAR8rCL; break; 1170 case Instruction::Shl: OpReg = X86::SHL8rCL; break; 1171 default: return false; 1172 } 1173 } else if (I->getType()->isIntegerTy(16)) { 1174 CReg = X86::CX; 1175 RC = &X86::GR16RegClass; 1176 switch (I->getOpcode()) { 1177 case Instruction::LShr: OpReg = X86::SHR16rCL; break; 1178 case Instruction::AShr: OpReg = X86::SAR16rCL; break; 1179 case Instruction::Shl: OpReg = X86::SHL16rCL; break; 1180 default: return false; 1181 } 1182 } else if (I->getType()->isIntegerTy(32)) { 1183 CReg = X86::ECX; 1184 RC = &X86::GR32RegClass; 1185 switch (I->getOpcode()) { 1186 case Instruction::LShr: OpReg = X86::SHR32rCL; break; 1187 case Instruction::AShr: OpReg = X86::SAR32rCL; break; 1188 case Instruction::Shl: OpReg = X86::SHL32rCL; break; 1189 default: return false; 1190 } 1191 } else if (I->getType()->isIntegerTy(64)) { 1192 CReg = X86::RCX; 1193 RC = &X86::GR64RegClass; 1194 switch (I->getOpcode()) { 1195 case Instruction::LShr: OpReg = X86::SHR64rCL; break; 1196 case Instruction::AShr: OpReg = X86::SAR64rCL; break; 1197 case Instruction::Shl: OpReg = X86::SHL64rCL; break; 1198 default: return false; 1199 } 1200 } else { 1201 return false; 1202 } 1203 1204 MVT VT; 1205 if (!isTypeLegal(I->getType(), VT)) 1206 return false; 1207 1208 unsigned Op0Reg = getRegForValue(I->getOperand(0)); 1209 if (Op0Reg == 0) return false; 1210 1211 unsigned Op1Reg = getRegForValue(I->getOperand(1)); 1212 if (Op1Reg == 0) return false; 1213 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1214 CReg).addReg(Op1Reg); 1215 1216 // The shift instruction uses X86::CL. If we defined a super-register 1217 // of X86::CL, emit a subreg KILL to precisely describe what we're doing here. 1218 if (CReg != X86::CL) 1219 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1220 TII.get(TargetOpcode::KILL), X86::CL) 1221 .addReg(CReg, RegState::Kill); 1222 1223 unsigned ResultReg = createResultReg(RC); 1224 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpReg), ResultReg) 1225 .addReg(Op0Reg); 1226 UpdateValueMap(I, ResultReg); 1227 return true; 1228} 1229 1230bool X86FastISel::X86SelectSelect(const Instruction *I) { 1231 MVT VT; 1232 if (!isTypeLegal(I->getType(), VT)) 1233 return false; 1234 1235 // We only use cmov here, if we don't have a cmov instruction bail. 1236 if (!Subtarget->hasCMov()) return false; 1237 1238 unsigned Opc = 0; 1239 const TargetRegisterClass *RC = NULL; 1240 if (VT == MVT::i16) { 1241 Opc = X86::CMOVE16rr; 1242 RC = &X86::GR16RegClass; 1243 } else if (VT == MVT::i32) { 1244 Opc = X86::CMOVE32rr; 1245 RC = &X86::GR32RegClass; 1246 } else if (VT == MVT::i64) { 1247 Opc = X86::CMOVE64rr; 1248 RC = &X86::GR64RegClass; 1249 } else { 1250 return false; 1251 } 1252 1253 unsigned Op0Reg = getRegForValue(I->getOperand(0)); 1254 if (Op0Reg == 0) return false; 1255 unsigned Op1Reg = getRegForValue(I->getOperand(1)); 1256 if (Op1Reg == 0) return false; 1257 unsigned Op2Reg = getRegForValue(I->getOperand(2)); 1258 if (Op2Reg == 0) return false; 1259 1260 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8rr)) 1261 .addReg(Op0Reg).addReg(Op0Reg); 1262 unsigned ResultReg = createResultReg(RC); 1263 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg) 1264 .addReg(Op1Reg).addReg(Op2Reg); 1265 UpdateValueMap(I, ResultReg); 1266 return true; 1267} 1268 1269bool X86FastISel::X86SelectFPExt(const Instruction *I) { 1270 // fpext from float to double. 1271 if (X86ScalarSSEf64 && 1272 I->getType()->isDoubleTy()) { 1273 const Value *V = I->getOperand(0); 1274 if (V->getType()->isFloatTy()) { 1275 unsigned OpReg = getRegForValue(V); 1276 if (OpReg == 0) return false; 1277 unsigned ResultReg = createResultReg(&X86::FR64RegClass); 1278 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1279 TII.get(X86::CVTSS2SDrr), ResultReg) 1280 .addReg(OpReg); 1281 UpdateValueMap(I, ResultReg); 1282 return true; 1283 } 1284 } 1285 1286 return false; 1287} 1288 1289bool X86FastISel::X86SelectFPTrunc(const Instruction *I) { 1290 if (X86ScalarSSEf64) { 1291 if (I->getType()->isFloatTy()) { 1292 const Value *V = I->getOperand(0); 1293 if (V->getType()->isDoubleTy()) { 1294 unsigned OpReg = getRegForValue(V); 1295 if (OpReg == 0) return false; 1296 unsigned ResultReg = createResultReg(&X86::FR32RegClass); 1297 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1298 TII.get(X86::CVTSD2SSrr), ResultReg) 1299 .addReg(OpReg); 1300 UpdateValueMap(I, ResultReg); 1301 return true; 1302 } 1303 } 1304 } 1305 1306 return false; 1307} 1308 1309bool X86FastISel::X86SelectTrunc(const Instruction *I) { 1310 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 1311 EVT DstVT = TLI.getValueType(I->getType()); 1312 1313 // This code only handles truncation to byte. 1314 if (DstVT != MVT::i8 && DstVT != MVT::i1) 1315 return false; 1316 if (!TLI.isTypeLegal(SrcVT)) 1317 return false; 1318 1319 unsigned InputReg = getRegForValue(I->getOperand(0)); 1320 if (!InputReg) 1321 // Unhandled operand. Halt "fast" selection and bail. 1322 return false; 1323 1324 if (SrcVT == MVT::i8) { 1325 // Truncate from i8 to i1; no code needed. 1326 UpdateValueMap(I, InputReg); 1327 return true; 1328 } 1329 1330 if (!Subtarget->is64Bit()) { 1331 // If we're on x86-32; we can't extract an i8 from a general register. 1332 // First issue a copy to GR16_ABCD or GR32_ABCD. 1333 const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16) ? 1334 (const TargetRegisterClass*)&X86::GR16_ABCDRegClass : 1335 (const TargetRegisterClass*)&X86::GR32_ABCDRegClass; 1336 unsigned CopyReg = createResultReg(CopyRC); 1337 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1338 CopyReg).addReg(InputReg); 1339 InputReg = CopyReg; 1340 } 1341 1342 // Issue an extract_subreg. 1343 unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8, 1344 InputReg, /*Kill=*/true, 1345 X86::sub_8bit); 1346 if (!ResultReg) 1347 return false; 1348 1349 UpdateValueMap(I, ResultReg); 1350 return true; 1351} 1352 1353bool X86FastISel::IsMemcpySmall(uint64_t Len) { 1354 return Len <= (Subtarget->is64Bit() ? 32 : 16); 1355} 1356 1357bool X86FastISel::TryEmitSmallMemcpy(X86AddressMode DestAM, 1358 X86AddressMode SrcAM, uint64_t Len) { 1359 1360 // Make sure we don't bloat code by inlining very large memcpy's. 1361 if (!IsMemcpySmall(Len)) 1362 return false; 1363 1364 bool i64Legal = Subtarget->is64Bit(); 1365 1366 // We don't care about alignment here since we just emit integer accesses. 1367 while (Len) { 1368 MVT VT; 1369 if (Len >= 8 && i64Legal) 1370 VT = MVT::i64; 1371 else if (Len >= 4) 1372 VT = MVT::i32; 1373 else if (Len >= 2) 1374 VT = MVT::i16; 1375 else { 1376 assert(Len == 1); 1377 VT = MVT::i8; 1378 } 1379 1380 unsigned Reg; 1381 bool RV = X86FastEmitLoad(VT, SrcAM, Reg); 1382 RV &= X86FastEmitStore(VT, Reg, DestAM); 1383 assert(RV && "Failed to emit load or store??"); 1384 1385 unsigned Size = VT.getSizeInBits()/8; 1386 Len -= Size; 1387 DestAM.Disp += Size; 1388 SrcAM.Disp += Size; 1389 } 1390 1391 return true; 1392} 1393 1394bool X86FastISel::X86VisitIntrinsicCall(const IntrinsicInst &I) { 1395 // FIXME: Handle more intrinsics. 1396 switch (I.getIntrinsicID()) { 1397 default: return false; 1398 case Intrinsic::memcpy: { 1399 const MemCpyInst &MCI = cast<MemCpyInst>(I); 1400 // Don't handle volatile or variable length memcpys. 1401 if (MCI.isVolatile()) 1402 return false; 1403 1404 if (isa<ConstantInt>(MCI.getLength())) { 1405 // Small memcpy's are common enough that we want to do them 1406 // without a call if possible. 1407 uint64_t Len = cast<ConstantInt>(MCI.getLength())->getZExtValue(); 1408 if (IsMemcpySmall(Len)) { 1409 X86AddressMode DestAM, SrcAM; 1410 if (!X86SelectAddress(MCI.getRawDest(), DestAM) || 1411 !X86SelectAddress(MCI.getRawSource(), SrcAM)) 1412 return false; 1413 TryEmitSmallMemcpy(DestAM, SrcAM, Len); 1414 return true; 1415 } 1416 } 1417 1418 unsigned SizeWidth = Subtarget->is64Bit() ? 64 : 32; 1419 if (!MCI.getLength()->getType()->isIntegerTy(SizeWidth)) 1420 return false; 1421 1422 if (MCI.getSourceAddressSpace() > 255 || MCI.getDestAddressSpace() > 255) 1423 return false; 1424 1425 return DoSelectCall(&I, "memcpy"); 1426 } 1427 case Intrinsic::memset: { 1428 const MemSetInst &MSI = cast<MemSetInst>(I); 1429 1430 if (MSI.isVolatile()) 1431 return false; 1432 1433 unsigned SizeWidth = Subtarget->is64Bit() ? 64 : 32; 1434 if (!MSI.getLength()->getType()->isIntegerTy(SizeWidth)) 1435 return false; 1436 1437 if (MSI.getDestAddressSpace() > 255) 1438 return false; 1439 1440 return DoSelectCall(&I, "memset"); 1441 } 1442 case Intrinsic::stackprotector: { 1443 // Emit code to store the stack guard onto the stack. 1444 EVT PtrTy = TLI.getPointerTy(); 1445 1446 const Value *Op1 = I.getArgOperand(0); // The guard's value. 1447 const AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 1448 1449 // Grab the frame index. 1450 X86AddressMode AM; 1451 if (!X86SelectAddress(Slot, AM)) return false; 1452 if (!X86FastEmitStore(PtrTy, Op1, AM)) return false; 1453 return true; 1454 } 1455 case Intrinsic::dbg_declare: { 1456 const DbgDeclareInst *DI = cast<DbgDeclareInst>(&I); 1457 X86AddressMode AM; 1458 assert(DI->getAddress() && "Null address should be checked earlier!"); 1459 if (!X86SelectAddress(DI->getAddress(), AM)) 1460 return false; 1461 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); 1462 // FIXME may need to add RegState::Debug to any registers produced, 1463 // although ESP/EBP should be the only ones at the moment. 1464 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II), AM). 1465 addImm(0).addMetadata(DI->getVariable()); 1466 return true; 1467 } 1468 case Intrinsic::trap: { 1469 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TRAP)); 1470 return true; 1471 } 1472 case Intrinsic::sadd_with_overflow: 1473 case Intrinsic::uadd_with_overflow: { 1474 // FIXME: Should fold immediates. 1475 1476 // Replace "add with overflow" intrinsics with an "add" instruction followed 1477 // by a seto/setc instruction. 1478 const Function *Callee = I.getCalledFunction(); 1479 Type *RetTy = 1480 cast<StructType>(Callee->getReturnType())->getTypeAtIndex(unsigned(0)); 1481 1482 MVT VT; 1483 if (!isTypeLegal(RetTy, VT)) 1484 return false; 1485 1486 const Value *Op1 = I.getArgOperand(0); 1487 const Value *Op2 = I.getArgOperand(1); 1488 unsigned Reg1 = getRegForValue(Op1); 1489 unsigned Reg2 = getRegForValue(Op2); 1490 1491 if (Reg1 == 0 || Reg2 == 0) 1492 // FIXME: Handle values *not* in registers. 1493 return false; 1494 1495 unsigned OpC = 0; 1496 if (VT == MVT::i32) 1497 OpC = X86::ADD32rr; 1498 else if (VT == MVT::i64) 1499 OpC = X86::ADD64rr; 1500 else 1501 return false; 1502 1503 // The call to CreateRegs builds two sequential registers, to store the 1504 // both the returned values. 1505 unsigned ResultReg = FuncInfo.CreateRegs(I.getType()); 1506 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpC), ResultReg) 1507 .addReg(Reg1).addReg(Reg2); 1508 1509 unsigned Opc = X86::SETBr; 1510 if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow) 1511 Opc = X86::SETOr; 1512 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg+1); 1513 1514 UpdateValueMap(&I, ResultReg, 2); 1515 return true; 1516 } 1517 } 1518} 1519 1520bool X86FastISel::X86SelectCall(const Instruction *I) { 1521 const CallInst *CI = cast<CallInst>(I); 1522 const Value *Callee = CI->getCalledValue(); 1523 1524 // Can't handle inline asm yet. 1525 if (isa<InlineAsm>(Callee)) 1526 return false; 1527 1528 // Handle intrinsic calls. 1529 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(CI)) 1530 return X86VisitIntrinsicCall(*II); 1531 1532 return DoSelectCall(I, 0); 1533} 1534 1535static unsigned computeBytesPoppedByCallee(const X86Subtarget &Subtarget, 1536 const ImmutableCallSite &CS) { 1537 if (Subtarget.is64Bit()) 1538 return 0; 1539 if (Subtarget.isTargetWindows()) 1540 return 0; 1541 CallingConv::ID CC = CS.getCallingConv(); 1542 if (CC == CallingConv::Fast || CC == CallingConv::GHC) 1543 return 0; 1544 if (!CS.paramHasAttr(1, Attributes::StructRet)) 1545 return 0; 1546 if (CS.paramHasAttr(1, Attributes::InReg)) 1547 return 0; 1548 return 4; 1549} 1550 1551// Select either a call, or an llvm.memcpy/memmove/memset intrinsic 1552bool X86FastISel::DoSelectCall(const Instruction *I, const char *MemIntName) { 1553 const CallInst *CI = cast<CallInst>(I); 1554 const Value *Callee = CI->getCalledValue(); 1555 1556 // Handle only C and fastcc calling conventions for now. 1557 ImmutableCallSite CS(CI); 1558 CallingConv::ID CC = CS.getCallingConv(); 1559 if (CC != CallingConv::C && CC != CallingConv::Fast && 1560 CC != CallingConv::X86_FastCall) 1561 return false; 1562 1563 // fastcc with -tailcallopt is intended to provide a guaranteed 1564 // tail call optimization. Fastisel doesn't know how to do that. 1565 if (CC == CallingConv::Fast && TM.Options.GuaranteedTailCallOpt) 1566 return false; 1567 1568 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 1569 FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 1570 bool isVarArg = FTy->isVarArg(); 1571 1572 // Don't know how to handle Win64 varargs yet. Nothing special needed for 1573 // x86-32. Special handling for x86-64 is implemented. 1574 if (isVarArg && Subtarget->isTargetWin64()) 1575 return false; 1576 1577 // Fast-isel doesn't know about callee-pop yet. 1578 if (X86::isCalleePop(CC, Subtarget->is64Bit(), isVarArg, 1579 TM.Options.GuaranteedTailCallOpt)) 1580 return false; 1581 1582 // Check whether the function can return without sret-demotion. 1583 SmallVector<ISD::OutputArg, 4> Outs; 1584 GetReturnInfo(I->getType(), CS.getAttributes().getRetAttributes(), 1585 Outs, TLI); 1586 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 1587 *FuncInfo.MF, FTy->isVarArg(), 1588 Outs, FTy->getContext()); 1589 if (!CanLowerReturn) 1590 return false; 1591 1592 // Materialize callee address in a register. FIXME: GV address can be 1593 // handled with a CALLpcrel32 instead. 1594 X86AddressMode CalleeAM; 1595 if (!X86SelectCallAddress(Callee, CalleeAM)) 1596 return false; 1597 unsigned CalleeOp = 0; 1598 const GlobalValue *GV = 0; 1599 if (CalleeAM.GV != 0) { 1600 GV = CalleeAM.GV; 1601 } else if (CalleeAM.Base.Reg != 0) { 1602 CalleeOp = CalleeAM.Base.Reg; 1603 } else 1604 return false; 1605 1606 // Deal with call operands first. 1607 SmallVector<const Value *, 8> ArgVals; 1608 SmallVector<unsigned, 8> Args; 1609 SmallVector<MVT, 8> ArgVTs; 1610 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags; 1611 unsigned arg_size = CS.arg_size(); 1612 Args.reserve(arg_size); 1613 ArgVals.reserve(arg_size); 1614 ArgVTs.reserve(arg_size); 1615 ArgFlags.reserve(arg_size); 1616 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 1617 i != e; ++i) { 1618 // If we're lowering a mem intrinsic instead of a regular call, skip the 1619 // last two arguments, which should not passed to the underlying functions. 1620 if (MemIntName && e-i <= 2) 1621 break; 1622 Value *ArgVal = *i; 1623 ISD::ArgFlagsTy Flags; 1624 unsigned AttrInd = i - CS.arg_begin() + 1; 1625 if (CS.paramHasAttr(AttrInd, Attributes::SExt)) 1626 Flags.setSExt(); 1627 if (CS.paramHasAttr(AttrInd, Attributes::ZExt)) 1628 Flags.setZExt(); 1629 1630 if (CS.paramHasAttr(AttrInd, Attributes::ByVal)) { 1631 PointerType *Ty = cast<PointerType>(ArgVal->getType()); 1632 Type *ElementTy = Ty->getElementType(); 1633 unsigned FrameSize = TD.getTypeAllocSize(ElementTy); 1634 unsigned FrameAlign = CS.getParamAlignment(AttrInd); 1635 if (!FrameAlign) 1636 FrameAlign = TLI.getByValTypeAlignment(ElementTy); 1637 Flags.setByVal(); 1638 Flags.setByValSize(FrameSize); 1639 Flags.setByValAlign(FrameAlign); 1640 if (!IsMemcpySmall(FrameSize)) 1641 return false; 1642 } 1643 1644 if (CS.paramHasAttr(AttrInd, Attributes::InReg)) 1645 Flags.setInReg(); 1646 if (CS.paramHasAttr(AttrInd, Attributes::Nest)) 1647 Flags.setNest(); 1648 1649 // If this is an i1/i8/i16 argument, promote to i32 to avoid an extra 1650 // instruction. This is safe because it is common to all fastisel supported 1651 // calling conventions on x86. 1652 if (ConstantInt *CI = dyn_cast<ConstantInt>(ArgVal)) { 1653 if (CI->getBitWidth() == 1 || CI->getBitWidth() == 8 || 1654 CI->getBitWidth() == 16) { 1655 if (Flags.isSExt()) 1656 ArgVal = ConstantExpr::getSExt(CI,Type::getInt32Ty(CI->getContext())); 1657 else 1658 ArgVal = ConstantExpr::getZExt(CI,Type::getInt32Ty(CI->getContext())); 1659 } 1660 } 1661 1662 unsigned ArgReg; 1663 1664 // Passing bools around ends up doing a trunc to i1 and passing it. 1665 // Codegen this as an argument + "and 1". 1666 if (ArgVal->getType()->isIntegerTy(1) && isa<TruncInst>(ArgVal) && 1667 cast<TruncInst>(ArgVal)->getParent() == I->getParent() && 1668 ArgVal->hasOneUse()) { 1669 ArgVal = cast<TruncInst>(ArgVal)->getOperand(0); 1670 ArgReg = getRegForValue(ArgVal); 1671 if (ArgReg == 0) return false; 1672 1673 MVT ArgVT; 1674 if (!isTypeLegal(ArgVal->getType(), ArgVT)) return false; 1675 1676 ArgReg = FastEmit_ri(ArgVT, ArgVT, ISD::AND, ArgReg, 1677 ArgVal->hasOneUse(), 1); 1678 } else { 1679 ArgReg = getRegForValue(ArgVal); 1680 } 1681 1682 if (ArgReg == 0) return false; 1683 1684 Type *ArgTy = ArgVal->getType(); 1685 MVT ArgVT; 1686 if (!isTypeLegal(ArgTy, ArgVT)) 1687 return false; 1688 if (ArgVT == MVT::x86mmx) 1689 return false; 1690 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy); 1691 Flags.setOrigAlign(OriginalAlignment); 1692 1693 Args.push_back(ArgReg); 1694 ArgVals.push_back(ArgVal); 1695 ArgVTs.push_back(ArgVT); 1696 ArgFlags.push_back(Flags); 1697 } 1698 1699 // Analyze operands of the call, assigning locations to each operand. 1700 SmallVector<CCValAssign, 16> ArgLocs; 1701 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, ArgLocs, 1702 I->getParent()->getContext()); 1703 1704 // Allocate shadow area for Win64 1705 if (Subtarget->isTargetWin64()) 1706 CCInfo.AllocateStack(32, 8); 1707 1708 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CC_X86); 1709 1710 // Get a count of how many bytes are to be pushed on the stack. 1711 unsigned NumBytes = CCInfo.getNextStackOffset(); 1712 1713 // Issue CALLSEQ_START 1714 unsigned AdjStackDown = TII.getCallFrameSetupOpcode(); 1715 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackDown)) 1716 .addImm(NumBytes); 1717 1718 // Process argument: walk the register/memloc assignments, inserting 1719 // copies / loads. 1720 SmallVector<unsigned, 4> RegArgs; 1721 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1722 CCValAssign &VA = ArgLocs[i]; 1723 unsigned Arg = Args[VA.getValNo()]; 1724 EVT ArgVT = ArgVTs[VA.getValNo()]; 1725 1726 // Promote the value if needed. 1727 switch (VA.getLocInfo()) { 1728 case CCValAssign::Full: break; 1729 case CCValAssign::SExt: { 1730 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && 1731 "Unexpected extend"); 1732 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), 1733 Arg, ArgVT, Arg); 1734 assert(Emitted && "Failed to emit a sext!"); (void)Emitted; 1735 ArgVT = VA.getLocVT(); 1736 break; 1737 } 1738 case CCValAssign::ZExt: { 1739 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && 1740 "Unexpected extend"); 1741 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), 1742 Arg, ArgVT, Arg); 1743 assert(Emitted && "Failed to emit a zext!"); (void)Emitted; 1744 ArgVT = VA.getLocVT(); 1745 break; 1746 } 1747 case CCValAssign::AExt: { 1748 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && 1749 "Unexpected extend"); 1750 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(), 1751 Arg, ArgVT, Arg); 1752 if (!Emitted) 1753 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), 1754 Arg, ArgVT, Arg); 1755 if (!Emitted) 1756 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), 1757 Arg, ArgVT, Arg); 1758 1759 assert(Emitted && "Failed to emit a aext!"); (void)Emitted; 1760 ArgVT = VA.getLocVT(); 1761 break; 1762 } 1763 case CCValAssign::BCvt: { 1764 unsigned BC = FastEmit_r(ArgVT.getSimpleVT(), VA.getLocVT(), 1765 ISD::BITCAST, Arg, /*TODO: Kill=*/false); 1766 assert(BC != 0 && "Failed to emit a bitcast!"); 1767 Arg = BC; 1768 ArgVT = VA.getLocVT(); 1769 break; 1770 } 1771 case CCValAssign::VExt: 1772 // VExt has not been implemented, so this should be impossible to reach 1773 // for now. However, fallback to Selection DAG isel once implemented. 1774 return false; 1775 case CCValAssign::Indirect: 1776 // FIXME: Indirect doesn't need extending, but fast-isel doesn't fully 1777 // support this. 1778 return false; 1779 } 1780 1781 if (VA.isRegLoc()) { 1782 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1783 VA.getLocReg()).addReg(Arg); 1784 RegArgs.push_back(VA.getLocReg()); 1785 } else { 1786 unsigned LocMemOffset = VA.getLocMemOffset(); 1787 X86AddressMode AM; 1788 AM.Base.Reg = RegInfo->getStackRegister(); 1789 AM.Disp = LocMemOffset; 1790 const Value *ArgVal = ArgVals[VA.getValNo()]; 1791 ISD::ArgFlagsTy Flags = ArgFlags[VA.getValNo()]; 1792 1793 if (Flags.isByVal()) { 1794 X86AddressMode SrcAM; 1795 SrcAM.Base.Reg = Arg; 1796 bool Res = TryEmitSmallMemcpy(AM, SrcAM, Flags.getByValSize()); 1797 assert(Res && "memcpy length already checked!"); (void)Res; 1798 } else if (isa<ConstantInt>(ArgVal) || isa<ConstantPointerNull>(ArgVal)) { 1799 // If this is a really simple value, emit this with the Value* version 1800 // of X86FastEmitStore. If it isn't simple, we don't want to do this, 1801 // as it can cause us to reevaluate the argument. 1802 if (!X86FastEmitStore(ArgVT, ArgVal, AM)) 1803 return false; 1804 } else { 1805 if (!X86FastEmitStore(ArgVT, Arg, AM)) 1806 return false; 1807 } 1808 } 1809 } 1810 1811 // ELF / PIC requires GOT in the EBX register before function calls via PLT 1812 // GOT pointer. 1813 if (Subtarget->isPICStyleGOT()) { 1814 unsigned Base = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF); 1815 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1816 X86::EBX).addReg(Base); 1817 } 1818 1819 if (Subtarget->is64Bit() && isVarArg && !Subtarget->isTargetWin64()) { 1820 // Count the number of XMM registers allocated. 1821 static const uint16_t XMMArgRegs[] = { 1822 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1823 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1824 }; 1825 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 1826 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::MOV8ri), 1827 X86::AL).addImm(NumXMMRegs); 1828 } 1829 1830 // Issue the call. 1831 MachineInstrBuilder MIB; 1832 if (CalleeOp) { 1833 // Register-indirect call. 1834 unsigned CallOpc; 1835 if (Subtarget->is64Bit()) 1836 CallOpc = X86::CALL64r; 1837 else 1838 CallOpc = X86::CALL32r; 1839 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc)) 1840 .addReg(CalleeOp); 1841 1842 } else { 1843 // Direct call. 1844 assert(GV && "Not a direct call"); 1845 unsigned CallOpc; 1846 if (Subtarget->is64Bit()) 1847 CallOpc = X86::CALL64pcrel32; 1848 else 1849 CallOpc = X86::CALLpcrel32; 1850 1851 // See if we need any target-specific flags on the GV operand. 1852 unsigned char OpFlags = 0; 1853 1854 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 1855 // external symbols most go through the PLT in PIC mode. If the symbol 1856 // has hidden or protected visibility, or if it is static or local, then 1857 // we don't need to use the PLT - we can directly call it. 1858 if (Subtarget->isTargetELF() && 1859 TM.getRelocationModel() == Reloc::PIC_ && 1860 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 1861 OpFlags = X86II::MO_PLT; 1862 } else if (Subtarget->isPICStyleStubAny() && 1863 (GV->isDeclaration() || GV->isWeakForLinker()) && 1864 (!Subtarget->getTargetTriple().isMacOSX() || 1865 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 1866 // PC-relative references to external symbols should go through $stub, 1867 // unless we're building with the leopard linker or later, which 1868 // automatically synthesizes these stubs. 1869 OpFlags = X86II::MO_DARWIN_STUB; 1870 } 1871 1872 1873 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc)); 1874 if (MemIntName) 1875 MIB.addExternalSymbol(MemIntName, OpFlags); 1876 else 1877 MIB.addGlobalAddress(GV, 0, OpFlags); 1878 } 1879 1880 // Add a register mask with the call-preserved registers. 1881 // Proper defs for return values will be added by setPhysRegsDeadExcept(). 1882 MIB.addRegMask(TRI.getCallPreservedMask(CS.getCallingConv())); 1883 1884 // Add an implicit use GOT pointer in EBX. 1885 if (Subtarget->isPICStyleGOT()) 1886 MIB.addReg(X86::EBX, RegState::Implicit); 1887 1888 if (Subtarget->is64Bit() && isVarArg && !Subtarget->isTargetWin64()) 1889 MIB.addReg(X86::AL, RegState::Implicit); 1890 1891 // Add implicit physical register uses to the call. 1892 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i) 1893 MIB.addReg(RegArgs[i], RegState::Implicit); 1894 1895 // Issue CALLSEQ_END 1896 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode(); 1897 const unsigned NumBytesCallee = computeBytesPoppedByCallee(*Subtarget, CS); 1898 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackUp)) 1899 .addImm(NumBytes).addImm(NumBytesCallee); 1900 1901 // Build info for return calling conv lowering code. 1902 // FIXME: This is practically a copy-paste from TargetLowering::LowerCallTo. 1903 SmallVector<ISD::InputArg, 32> Ins; 1904 SmallVector<EVT, 4> RetTys; 1905 ComputeValueVTs(TLI, I->getType(), RetTys); 1906 for (unsigned i = 0, e = RetTys.size(); i != e; ++i) { 1907 EVT VT = RetTys[i]; 1908 EVT RegisterVT = TLI.getRegisterType(I->getParent()->getContext(), VT); 1909 unsigned NumRegs = TLI.getNumRegisters(I->getParent()->getContext(), VT); 1910 for (unsigned j = 0; j != NumRegs; ++j) { 1911 ISD::InputArg MyFlags; 1912 MyFlags.VT = RegisterVT.getSimpleVT(); 1913 MyFlags.Used = !CS.getInstruction()->use_empty(); 1914 if (CS.paramHasAttr(0, Attributes::SExt)) 1915 MyFlags.Flags.setSExt(); 1916 if (CS.paramHasAttr(0, Attributes::ZExt)) 1917 MyFlags.Flags.setZExt(); 1918 if (CS.paramHasAttr(0, Attributes::InReg)) 1919 MyFlags.Flags.setInReg(); 1920 Ins.push_back(MyFlags); 1921 } 1922 } 1923 1924 // Now handle call return values. 1925 SmallVector<unsigned, 4> UsedRegs; 1926 SmallVector<CCValAssign, 16> RVLocs; 1927 CCState CCRetInfo(CC, false, *FuncInfo.MF, TM, RVLocs, 1928 I->getParent()->getContext()); 1929 unsigned ResultReg = FuncInfo.CreateRegs(I->getType()); 1930 CCRetInfo.AnalyzeCallResult(Ins, RetCC_X86); 1931 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1932 EVT CopyVT = RVLocs[i].getValVT(); 1933 unsigned CopyReg = ResultReg + i; 1934 1935 // If this is a call to a function that returns an fp value on the x87 fp 1936 // stack, but where we prefer to use the value in xmm registers, copy it 1937 // out as F80 and use a truncate to move it from fp stack reg to xmm reg. 1938 if ((RVLocs[i].getLocReg() == X86::ST0 || 1939 RVLocs[i].getLocReg() == X86::ST1)) { 1940 if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) { 1941 CopyVT = MVT::f80; 1942 CopyReg = createResultReg(&X86::RFP80RegClass); 1943 } 1944 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::FpPOP_RETVAL), 1945 CopyReg); 1946 } else { 1947 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1948 CopyReg).addReg(RVLocs[i].getLocReg()); 1949 UsedRegs.push_back(RVLocs[i].getLocReg()); 1950 } 1951 1952 if (CopyVT != RVLocs[i].getValVT()) { 1953 // Round the F80 the right size, which also moves to the appropriate xmm 1954 // register. This is accomplished by storing the F80 value in memory and 1955 // then loading it back. Ewww... 1956 EVT ResVT = RVLocs[i].getValVT(); 1957 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; 1958 unsigned MemSize = ResVT.getSizeInBits()/8; 1959 int FI = MFI.CreateStackObject(MemSize, MemSize, false); 1960 addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1961 TII.get(Opc)), FI) 1962 .addReg(CopyReg); 1963 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm; 1964 addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1965 TII.get(Opc), ResultReg + i), FI); 1966 } 1967 } 1968 1969 if (RVLocs.size()) 1970 UpdateValueMap(I, ResultReg, RVLocs.size()); 1971 1972 // Set all unused physreg defs as dead. 1973 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI); 1974 1975 return true; 1976} 1977 1978 1979bool 1980X86FastISel::TargetSelectInstruction(const Instruction *I) { 1981 switch (I->getOpcode()) { 1982 default: break; 1983 case Instruction::Load: 1984 return X86SelectLoad(I); 1985 case Instruction::Store: 1986 return X86SelectStore(I); 1987 case Instruction::Ret: 1988 return X86SelectRet(I); 1989 case Instruction::ICmp: 1990 case Instruction::FCmp: 1991 return X86SelectCmp(I); 1992 case Instruction::ZExt: 1993 return X86SelectZExt(I); 1994 case Instruction::Br: 1995 return X86SelectBranch(I); 1996 case Instruction::Call: 1997 return X86SelectCall(I); 1998 case Instruction::LShr: 1999 case Instruction::AShr: 2000 case Instruction::Shl: 2001 return X86SelectShift(I); 2002 case Instruction::Select: 2003 return X86SelectSelect(I); 2004 case Instruction::Trunc: 2005 return X86SelectTrunc(I); 2006 case Instruction::FPExt: 2007 return X86SelectFPExt(I); 2008 case Instruction::FPTrunc: 2009 return X86SelectFPTrunc(I); 2010 case Instruction::IntToPtr: // Deliberate fall-through. 2011 case Instruction::PtrToInt: { 2012 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 2013 EVT DstVT = TLI.getValueType(I->getType()); 2014 if (DstVT.bitsGT(SrcVT)) 2015 return X86SelectZExt(I); 2016 if (DstVT.bitsLT(SrcVT)) 2017 return X86SelectTrunc(I); 2018 unsigned Reg = getRegForValue(I->getOperand(0)); 2019 if (Reg == 0) return false; 2020 UpdateValueMap(I, Reg); 2021 return true; 2022 } 2023 } 2024 2025 return false; 2026} 2027 2028unsigned X86FastISel::TargetMaterializeConstant(const Constant *C) { 2029 MVT VT; 2030 if (!isTypeLegal(C->getType(), VT)) 2031 return 0; 2032 2033 // Can't handle alternate code models yet. 2034 if (TM.getCodeModel() != CodeModel::Small) 2035 return 0; 2036 2037 // Get opcode and regclass of the output for the given load instruction. 2038 unsigned Opc = 0; 2039 const TargetRegisterClass *RC = NULL; 2040 switch (VT.SimpleTy) { 2041 default: return 0; 2042 case MVT::i8: 2043 Opc = X86::MOV8rm; 2044 RC = &X86::GR8RegClass; 2045 break; 2046 case MVT::i16: 2047 Opc = X86::MOV16rm; 2048 RC = &X86::GR16RegClass; 2049 break; 2050 case MVT::i32: 2051 Opc = X86::MOV32rm; 2052 RC = &X86::GR32RegClass; 2053 break; 2054 case MVT::i64: 2055 // Must be in x86-64 mode. 2056 Opc = X86::MOV64rm; 2057 RC = &X86::GR64RegClass; 2058 break; 2059 case MVT::f32: 2060 if (X86ScalarSSEf32) { 2061 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm; 2062 RC = &X86::FR32RegClass; 2063 } else { 2064 Opc = X86::LD_Fp32m; 2065 RC = &X86::RFP32RegClass; 2066 } 2067 break; 2068 case MVT::f64: 2069 if (X86ScalarSSEf64) { 2070 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm; 2071 RC = &X86::FR64RegClass; 2072 } else { 2073 Opc = X86::LD_Fp64m; 2074 RC = &X86::RFP64RegClass; 2075 } 2076 break; 2077 case MVT::f80: 2078 // No f80 support yet. 2079 return 0; 2080 } 2081 2082 // Materialize addresses with LEA instructions. 2083 if (isa<GlobalValue>(C)) { 2084 X86AddressMode AM; 2085 if (X86SelectAddress(C, AM)) { 2086 // If the expression is just a basereg, then we're done, otherwise we need 2087 // to emit an LEA. 2088 if (AM.BaseType == X86AddressMode::RegBase && 2089 AM.IndexReg == 0 && AM.Disp == 0 && AM.GV == 0) 2090 return AM.Base.Reg; 2091 2092 Opc = TLI.getPointerTy() == MVT::i32 ? X86::LEA32r : X86::LEA64r; 2093 unsigned ResultReg = createResultReg(RC); 2094 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 2095 TII.get(Opc), ResultReg), AM); 2096 return ResultReg; 2097 } 2098 return 0; 2099 } 2100 2101 // MachineConstantPool wants an explicit alignment. 2102 unsigned Align = TD.getPrefTypeAlignment(C->getType()); 2103 if (Align == 0) { 2104 // Alignment of vector types. FIXME! 2105 Align = TD.getTypeAllocSize(C->getType()); 2106 } 2107 2108 // x86-32 PIC requires a PIC base register for constant pools. 2109 unsigned PICBase = 0; 2110 unsigned char OpFlag = 0; 2111 if (Subtarget->isPICStyleStubPIC()) { // Not dynamic-no-pic 2112 OpFlag = X86II::MO_PIC_BASE_OFFSET; 2113 PICBase = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF); 2114 } else if (Subtarget->isPICStyleGOT()) { 2115 OpFlag = X86II::MO_GOTOFF; 2116 PICBase = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF); 2117 } else if (Subtarget->isPICStyleRIPRel() && 2118 TM.getCodeModel() == CodeModel::Small) { 2119 PICBase = X86::RIP; 2120 } 2121 2122 // Create the load from the constant pool. 2123 unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align); 2124 unsigned ResultReg = createResultReg(RC); 2125 addConstantPoolReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 2126 TII.get(Opc), ResultReg), 2127 MCPOffset, PICBase, OpFlag); 2128 2129 return ResultReg; 2130} 2131 2132unsigned X86FastISel::TargetMaterializeAlloca(const AllocaInst *C) { 2133 // Fail on dynamic allocas. At this point, getRegForValue has already 2134 // checked its CSE maps, so if we're here trying to handle a dynamic 2135 // alloca, we're not going to succeed. X86SelectAddress has a 2136 // check for dynamic allocas, because it's called directly from 2137 // various places, but TargetMaterializeAlloca also needs a check 2138 // in order to avoid recursion between getRegForValue, 2139 // X86SelectAddrss, and TargetMaterializeAlloca. 2140 if (!FuncInfo.StaticAllocaMap.count(C)) 2141 return 0; 2142 2143 X86AddressMode AM; 2144 if (!X86SelectAddress(C, AM)) 2145 return 0; 2146 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 2147 const TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy()); 2148 unsigned ResultReg = createResultReg(RC); 2149 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 2150 TII.get(Opc), ResultReg), AM); 2151 return ResultReg; 2152} 2153 2154unsigned X86FastISel::TargetMaterializeFloatZero(const ConstantFP *CF) { 2155 MVT VT; 2156 if (!isTypeLegal(CF->getType(), VT)) 2157 return false; 2158 2159 // Get opcode and regclass for the given zero. 2160 unsigned Opc = 0; 2161 const TargetRegisterClass *RC = NULL; 2162 switch (VT.SimpleTy) { 2163 default: return false; 2164 case MVT::f32: 2165 if (X86ScalarSSEf32) { 2166 Opc = X86::FsFLD0SS; 2167 RC = &X86::FR32RegClass; 2168 } else { 2169 Opc = X86::LD_Fp032; 2170 RC = &X86::RFP32RegClass; 2171 } 2172 break; 2173 case MVT::f64: 2174 if (X86ScalarSSEf64) { 2175 Opc = X86::FsFLD0SD; 2176 RC = &X86::FR64RegClass; 2177 } else { 2178 Opc = X86::LD_Fp064; 2179 RC = &X86::RFP64RegClass; 2180 } 2181 break; 2182 case MVT::f80: 2183 // No f80 support yet. 2184 return false; 2185 } 2186 2187 unsigned ResultReg = createResultReg(RC); 2188 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg); 2189 return ResultReg; 2190} 2191 2192 2193/// TryToFoldLoad - The specified machine instr operand is a vreg, and that 2194/// vreg is being provided by the specified load instruction. If possible, 2195/// try to fold the load as an operand to the instruction, returning true if 2196/// possible. 2197bool X86FastISel::TryToFoldLoad(MachineInstr *MI, unsigned OpNo, 2198 const LoadInst *LI) { 2199 X86AddressMode AM; 2200 if (!X86SelectAddress(LI->getOperand(0), AM)) 2201 return false; 2202 2203 const X86InstrInfo &XII = (const X86InstrInfo&)TII; 2204 2205 unsigned Size = TD.getTypeAllocSize(LI->getType()); 2206 unsigned Alignment = LI->getAlignment(); 2207 2208 SmallVector<MachineOperand, 8> AddrOps; 2209 AM.getFullAddress(AddrOps); 2210 2211 MachineInstr *Result = 2212 XII.foldMemoryOperandImpl(*FuncInfo.MF, MI, OpNo, AddrOps, Size, Alignment); 2213 if (Result == 0) return false; 2214 2215 FuncInfo.MBB->insert(FuncInfo.InsertPt, Result); 2216 MI->eraseFromParent(); 2217 return true; 2218} 2219 2220 2221namespace llvm { 2222 FastISel *X86::createFastISel(FunctionLoweringInfo &funcInfo, 2223 const TargetLibraryInfo *libInfo) { 2224 return new X86FastISel(funcInfo, libInfo); 2225 } 2226} 2227