X86FloatingPoint.cpp revision 2c79de8018bb8c77a245d4ccb740affbf1f52319
1//===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the pass which converts floating point instructions from 11// virtual registers into register stack instructions. This pass uses live 12// variable information to indicate where the FPn registers are used and their 13// lifetimes. 14// 15// This pass is hampered by the lack of decent CFG manipulation routines for 16// machine code. In particular, this wants to be able to split critical edges 17// as necessary, traverse the machine basic block CFG in depth-first order, and 18// allow there to be multiple machine basic blocks for each LLVM basicblock 19// (needed for critical edge splitting). 20// 21// In particular, this pass currently barfs on critical edges. Because of this, 22// it requires the instruction selector to insert FP_REG_KILL instructions on 23// the exits of any basic block that has critical edges going from it, or which 24// branch to a critical basic block. 25// 26// FIXME: this is not implemented yet. The stackifier pass only works on local 27// basic blocks. 28// 29//===----------------------------------------------------------------------===// 30 31#define DEBUG_TYPE "fp" 32#include "X86.h" 33#include "X86InstrInfo.h" 34#include "llvm/CodeGen/MachineFunctionPass.h" 35#include "llvm/CodeGen/MachineInstrBuilder.h" 36#include "llvm/CodeGen/LiveVariables.h" 37#include "llvm/CodeGen/Passes.h" 38#include "llvm/Target/TargetInstrInfo.h" 39#include "llvm/Target/TargetMachine.h" 40#include "llvm/Support/Debug.h" 41#include "llvm/Support/Visibility.h" 42#include "llvm/ADT/DepthFirstIterator.h" 43#include "llvm/ADT/Statistic.h" 44#include "llvm/ADT/STLExtras.h" 45#include <algorithm> 46#include <iostream> 47#include <set> 48using namespace llvm; 49 50namespace { 51 Statistic<> NumFXCH("x86-codegen", "Number of fxch instructions inserted"); 52 Statistic<> NumFP ("x86-codegen", "Number of floating point instructions"); 53 54 struct VISIBILITY_HIDDEN FPS : public MachineFunctionPass { 55 virtual bool runOnMachineFunction(MachineFunction &MF); 56 57 virtual const char *getPassName() const { return "X86 FP Stackifier"; } 58 59 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 60 AU.addRequired<LiveVariables>(); 61 MachineFunctionPass::getAnalysisUsage(AU); 62 } 63 private: 64 LiveVariables *LV; // Live variable info for current function... 65 MachineBasicBlock *MBB; // Current basic block 66 unsigned Stack[8]; // FP<n> Registers in each stack slot... 67 unsigned RegMap[8]; // Track which stack slot contains each register 68 unsigned StackTop; // The current top of the FP stack. 69 70 void dumpStack() const { 71 std::cerr << "Stack contents:"; 72 for (unsigned i = 0; i != StackTop; ++i) { 73 std::cerr << " FP" << Stack[i]; 74 assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!"); 75 } 76 std::cerr << "\n"; 77 } 78 private: 79 // getSlot - Return the stack slot number a particular register number is 80 // in... 81 unsigned getSlot(unsigned RegNo) const { 82 assert(RegNo < 8 && "Regno out of range!"); 83 return RegMap[RegNo]; 84 } 85 86 // getStackEntry - Return the X86::FP<n> register in register ST(i) 87 unsigned getStackEntry(unsigned STi) const { 88 assert(STi < StackTop && "Access past stack top!"); 89 return Stack[StackTop-1-STi]; 90 } 91 92 // getSTReg - Return the X86::ST(i) register which contains the specified 93 // FP<RegNo> register 94 unsigned getSTReg(unsigned RegNo) const { 95 return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0; 96 } 97 98 // pushReg - Push the specified FP<n> register onto the stack 99 void pushReg(unsigned Reg) { 100 assert(Reg < 8 && "Register number out of range!"); 101 assert(StackTop < 8 && "Stack overflow!"); 102 Stack[StackTop] = Reg; 103 RegMap[Reg] = StackTop++; 104 } 105 106 bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; } 107 void moveToTop(unsigned RegNo, MachineBasicBlock::iterator &I) { 108 if (!isAtTop(RegNo)) { 109 unsigned Slot = getSlot(RegNo); 110 unsigned STReg = getSTReg(RegNo); 111 unsigned RegOnTop = getStackEntry(0); 112 113 // Swap the slots the regs are in 114 std::swap(RegMap[RegNo], RegMap[RegOnTop]); 115 116 // Swap stack slot contents 117 assert(RegMap[RegOnTop] < StackTop); 118 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]); 119 120 // Emit an fxch to update the runtime processors version of the state 121 BuildMI(*MBB, I, X86::FXCH, 1).addReg(STReg); 122 NumFXCH++; 123 } 124 } 125 126 void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) { 127 unsigned STReg = getSTReg(RegNo); 128 pushReg(AsReg); // New register on top of stack 129 130 BuildMI(*MBB, I, X86::FLDrr, 1).addReg(STReg); 131 } 132 133 // popStackAfter - Pop the current value off of the top of the FP stack 134 // after the specified instruction. 135 void popStackAfter(MachineBasicBlock::iterator &I); 136 137 // freeStackSlotAfter - Free the specified register from the register stack, 138 // so that it is no longer in a register. If the register is currently at 139 // the top of the stack, we just pop the current instruction, otherwise we 140 // store the current top-of-stack into the specified slot, then pop the top 141 // of stack. 142 void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg); 143 144 bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB); 145 146 void handleZeroArgFP(MachineBasicBlock::iterator &I); 147 void handleOneArgFP(MachineBasicBlock::iterator &I); 148 void handleOneArgFPRW(MachineBasicBlock::iterator &I); 149 void handleTwoArgFP(MachineBasicBlock::iterator &I); 150 void handleCompareFP(MachineBasicBlock::iterator &I); 151 void handleCondMovFP(MachineBasicBlock::iterator &I); 152 void handleSpecialFP(MachineBasicBlock::iterator &I); 153 }; 154} 155 156FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); } 157 158/// runOnMachineFunction - Loop over all of the basic blocks, transforming FP 159/// register references into FP stack references. 160/// 161bool FPS::runOnMachineFunction(MachineFunction &MF) { 162 // We only need to run this pass if there are any FP registers used in this 163 // function. If it is all integer, there is nothing for us to do! 164 const bool *PhysRegsUsed = MF.getUsedPhysregs(); 165 bool FPIsUsed = false; 166 167 assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!"); 168 for (unsigned i = 0; i <= 6; ++i) 169 if (PhysRegsUsed[X86::FP0+i]) { 170 FPIsUsed = true; 171 break; 172 } 173 174 // Early exit. 175 if (!FPIsUsed) return false; 176 177 LV = &getAnalysis<LiveVariables>(); 178 StackTop = 0; 179 180 // Process the function in depth first order so that we process at least one 181 // of the predecessors for every reachable block in the function. 182 std::set<MachineBasicBlock*> Processed; 183 MachineBasicBlock *Entry = MF.begin(); 184 185 bool Changed = false; 186 for (df_ext_iterator<MachineBasicBlock*, std::set<MachineBasicBlock*> > 187 I = df_ext_begin(Entry, Processed), E = df_ext_end(Entry, Processed); 188 I != E; ++I) 189 Changed |= processBasicBlock(MF, **I); 190 191 return Changed; 192} 193 194/// processBasicBlock - Loop over all of the instructions in the basic block, 195/// transforming FP instructions into their stack form. 196/// 197bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) { 198 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 199 bool Changed = false; 200 MBB = &BB; 201 202 for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) { 203 MachineInstr *MI = I; 204 unsigned Flags = TII.get(MI->getOpcode()).TSFlags; 205 if ((Flags & X86II::FPTypeMask) == X86II::NotFP) 206 continue; // Efficiently ignore non-fp insts! 207 208 MachineInstr *PrevMI = 0; 209 if (I != BB.begin()) 210 PrevMI = prior(I); 211 212 ++NumFP; // Keep track of # of pseudo instrs 213 DEBUG(std::cerr << "\nFPInst:\t"; MI->print(std::cerr, &(MF.getTarget()))); 214 215 // Get dead variables list now because the MI pointer may be deleted as part 216 // of processing! 217 LiveVariables::killed_iterator IB, IE; 218 tie(IB, IE) = LV->dead_range(MI); 219 220 DEBUG( 221 const MRegisterInfo *MRI = MF.getTarget().getRegisterInfo(); 222 LiveVariables::killed_iterator I = LV->killed_begin(MI); 223 LiveVariables::killed_iterator E = LV->killed_end(MI); 224 if (I != E) { 225 std::cerr << "Killed Operands:"; 226 for (; I != E; ++I) 227 std::cerr << " %" << MRI->getName(*I); 228 std::cerr << "\n"; 229 } 230 ); 231 232 switch (Flags & X86II::FPTypeMask) { 233 case X86II::ZeroArgFP: handleZeroArgFP(I); break; 234 case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0) 235 case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0)) 236 case X86II::TwoArgFP: handleTwoArgFP(I); break; 237 case X86II::CompareFP: handleCompareFP(I); break; 238 case X86II::CondMovFP: handleCondMovFP(I); break; 239 case X86II::SpecialFP: handleSpecialFP(I); break; 240 default: assert(0 && "Unknown FP Type!"); 241 } 242 243 // Check to see if any of the values defined by this instruction are dead 244 // after definition. If so, pop them. 245 for (; IB != IE; ++IB) { 246 unsigned Reg = *IB; 247 if (Reg >= X86::FP0 && Reg <= X86::FP6) { 248 DEBUG(std::cerr << "Register FP#" << Reg-X86::FP0 << " is dead!\n"); 249 freeStackSlotAfter(I, Reg-X86::FP0); 250 } 251 } 252 253 // Print out all of the instructions expanded to if -debug 254 DEBUG( 255 MachineBasicBlock::iterator PrevI(PrevMI); 256 if (I == PrevI) { 257 std::cerr << "Just deleted pseudo instruction\n"; 258 } else { 259 MachineBasicBlock::iterator Start = I; 260 // Rewind to first instruction newly inserted. 261 while (Start != BB.begin() && prior(Start) != PrevI) --Start; 262 std::cerr << "Inserted instructions:\n\t"; 263 Start->print(std::cerr, &MF.getTarget()); 264 while (++Start != next(I)); 265 } 266 dumpStack(); 267 ); 268 269 Changed = true; 270 } 271 272 assert(StackTop == 0 && "Stack not empty at end of basic block?"); 273 return Changed; 274} 275 276//===----------------------------------------------------------------------===// 277// Efficient Lookup Table Support 278//===----------------------------------------------------------------------===// 279 280namespace { 281 struct TableEntry { 282 unsigned from; 283 unsigned to; 284 bool operator<(const TableEntry &TE) const { return from < TE.from; } 285 friend bool operator<(const TableEntry &TE, unsigned V) { 286 return TE.from < V; 287 } 288 friend bool operator<(unsigned V, const TableEntry &TE) { 289 return V < TE.from; 290 } 291 }; 292} 293 294static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) { 295 for (unsigned i = 0; i != NumEntries-1; ++i) 296 if (!(Table[i] < Table[i+1])) return false; 297 return true; 298} 299 300static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) { 301 const TableEntry *I = std::lower_bound(Table, Table+N, Opcode); 302 if (I != Table+N && I->from == Opcode) 303 return I->to; 304 return -1; 305} 306 307#define ARRAY_SIZE(TABLE) \ 308 (sizeof(TABLE)/sizeof(TABLE[0])) 309 310#ifdef NDEBUG 311#define ASSERT_SORTED(TABLE) 312#else 313#define ASSERT_SORTED(TABLE) \ 314 { static bool TABLE##Checked = false; \ 315 if (!TABLE##Checked) \ 316 assert(TableIsSorted(TABLE, ARRAY_SIZE(TABLE)) && \ 317 "All lookup tables must be sorted for efficient access!"); \ 318 } 319#endif 320 321//===----------------------------------------------------------------------===// 322// Register File -> Register Stack Mapping Methods 323//===----------------------------------------------------------------------===// 324 325// OpcodeTable - Sorted map of register instructions to their stack version. 326// The first element is an register file pseudo instruction, the second is the 327// concrete X86 instruction which uses the register stack. 328// 329static const TableEntry OpcodeTable[] = { 330 { X86::FpABS , X86::FABS }, 331 { X86::FpADD32m , X86::FADD32m }, 332 { X86::FpADD64m , X86::FADD64m }, 333 { X86::FpCHS , X86::FCHS }, 334 { X86::FpCMOVB , X86::FCMOVB }, 335 { X86::FpCMOVBE , X86::FCMOVBE }, 336 { X86::FpCMOVE , X86::FCMOVE }, 337 { X86::FpCMOVNB , X86::FCMOVNB }, 338 { X86::FpCMOVNBE , X86::FCMOVNBE }, 339 { X86::FpCMOVNE , X86::FCMOVNE }, 340 { X86::FpCMOVNP , X86::FCMOVNP }, 341 { X86::FpCMOVP , X86::FCMOVP }, 342 { X86::FpCOS , X86::FCOS }, 343 { X86::FpDIV32m , X86::FDIV32m }, 344 { X86::FpDIV64m , X86::FDIV64m }, 345 { X86::FpDIVR32m , X86::FDIVR32m }, 346 { X86::FpDIVR64m , X86::FDIVR64m }, 347 { X86::FpIADD16m , X86::FIADD16m }, 348 { X86::FpIADD32m , X86::FIADD32m }, 349 { X86::FpIDIV16m , X86::FIDIV16m }, 350 { X86::FpIDIV32m , X86::FIDIV32m }, 351 { X86::FpIDIVR16m, X86::FIDIVR16m}, 352 { X86::FpIDIVR32m, X86::FIDIVR32m}, 353 { X86::FpILD16m , X86::FILD16m }, 354 { X86::FpILD32m , X86::FILD32m }, 355 { X86::FpILD64m , X86::FILD64m }, 356 { X86::FpIMUL16m , X86::FIMUL16m }, 357 { X86::FpIMUL32m , X86::FIMUL32m }, 358 { X86::FpIST16m , X86::FIST16m }, 359 { X86::FpIST32m , X86::FIST32m }, 360 { X86::FpIST64m , X86::FISTP64m }, 361 { X86::FpISTT16m , X86::FISTTP16m}, 362 { X86::FpISTT32m , X86::FISTTP32m}, 363 { X86::FpISTT64m , X86::FISTTP64m}, 364 { X86::FpISUB16m , X86::FISUB16m }, 365 { X86::FpISUB32m , X86::FISUB32m }, 366 { X86::FpISUBR16m, X86::FISUBR16m}, 367 { X86::FpISUBR32m, X86::FISUBR32m}, 368 { X86::FpLD0 , X86::FLD0 }, 369 { X86::FpLD1 , X86::FLD1 }, 370 { X86::FpLD32m , X86::FLD32m }, 371 { X86::FpLD64m , X86::FLD64m }, 372 { X86::FpMUL32m , X86::FMUL32m }, 373 { X86::FpMUL64m , X86::FMUL64m }, 374 { X86::FpSIN , X86::FSIN }, 375 { X86::FpSQRT , X86::FSQRT }, 376 { X86::FpST32m , X86::FST32m }, 377 { X86::FpST64m , X86::FST64m }, 378 { X86::FpSUB32m , X86::FSUB32m }, 379 { X86::FpSUB64m , X86::FSUB64m }, 380 { X86::FpSUBR32m , X86::FSUBR32m }, 381 { X86::FpSUBR64m , X86::FSUBR64m }, 382 { X86::FpTST , X86::FTST }, 383 { X86::FpUCOMIr , X86::FUCOMIr }, 384 { X86::FpUCOMr , X86::FUCOMr }, 385}; 386 387static unsigned getConcreteOpcode(unsigned Opcode) { 388 ASSERT_SORTED(OpcodeTable); 389 int Opc = Lookup(OpcodeTable, ARRAY_SIZE(OpcodeTable), Opcode); 390 assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!"); 391 return Opc; 392} 393 394//===----------------------------------------------------------------------===// 395// Helper Methods 396//===----------------------------------------------------------------------===// 397 398// PopTable - Sorted map of instructions to their popping version. The first 399// element is an instruction, the second is the version which pops. 400// 401static const TableEntry PopTable[] = { 402 { X86::FADDrST0 , X86::FADDPrST0 }, 403 404 { X86::FDIVRrST0, X86::FDIVRPrST0 }, 405 { X86::FDIVrST0 , X86::FDIVPrST0 }, 406 407 { X86::FIST16m , X86::FISTP16m }, 408 { X86::FIST32m , X86::FISTP32m }, 409 410 { X86::FMULrST0 , X86::FMULPrST0 }, 411 412 { X86::FST32m , X86::FSTP32m }, 413 { X86::FST64m , X86::FSTP64m }, 414 { X86::FSTrr , X86::FSTPrr }, 415 416 { X86::FSUBRrST0, X86::FSUBRPrST0 }, 417 { X86::FSUBrST0 , X86::FSUBPrST0 }, 418 419 { X86::FUCOMIr , X86::FUCOMIPr }, 420 421 { X86::FUCOMPr , X86::FUCOMPPr }, 422 { X86::FUCOMr , X86::FUCOMPr }, 423}; 424 425/// popStackAfter - Pop the current value off of the top of the FP stack after 426/// the specified instruction. This attempts to be sneaky and combine the pop 427/// into the instruction itself if possible. The iterator is left pointing to 428/// the last instruction, be it a new pop instruction inserted, or the old 429/// instruction if it was modified in place. 430/// 431void FPS::popStackAfter(MachineBasicBlock::iterator &I) { 432 ASSERT_SORTED(PopTable); 433 assert(StackTop > 0 && "Cannot pop empty stack!"); 434 RegMap[Stack[--StackTop]] = ~0; // Update state 435 436 // Check to see if there is a popping version of this instruction... 437 int Opcode = Lookup(PopTable, ARRAY_SIZE(PopTable), I->getOpcode()); 438 if (Opcode != -1) { 439 I->setOpcode(Opcode); 440 if (Opcode == X86::FUCOMPPr) 441 I->RemoveOperand(0); 442 443 } else { // Insert an explicit pop 444 I = BuildMI(*MBB, ++I, X86::FSTPrr, 1).addReg(X86::ST0); 445 } 446} 447 448/// freeStackSlotAfter - Free the specified register from the register stack, so 449/// that it is no longer in a register. If the register is currently at the top 450/// of the stack, we just pop the current instruction, otherwise we store the 451/// current top-of-stack into the specified slot, then pop the top of stack. 452void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) { 453 if (getStackEntry(0) == FPRegNo) { // already at the top of stack? easy. 454 popStackAfter(I); 455 return; 456 } 457 458 // Otherwise, store the top of stack into the dead slot, killing the operand 459 // without having to add in an explicit xchg then pop. 460 // 461 unsigned STReg = getSTReg(FPRegNo); 462 unsigned OldSlot = getSlot(FPRegNo); 463 unsigned TopReg = Stack[StackTop-1]; 464 Stack[OldSlot] = TopReg; 465 RegMap[TopReg] = OldSlot; 466 RegMap[FPRegNo] = ~0; 467 Stack[--StackTop] = ~0; 468 I = BuildMI(*MBB, ++I, X86::FSTPrr, 1).addReg(STReg); 469} 470 471 472static unsigned getFPReg(const MachineOperand &MO) { 473 assert(MO.isRegister() && "Expected an FP register!"); 474 unsigned Reg = MO.getReg(); 475 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!"); 476 return Reg - X86::FP0; 477} 478 479 480//===----------------------------------------------------------------------===// 481// Instruction transformation implementation 482//===----------------------------------------------------------------------===// 483 484/// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem> 485/// 486void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) { 487 MachineInstr *MI = I; 488 unsigned DestReg = getFPReg(MI->getOperand(0)); 489 490 // Change from the pseudo instruction to the concrete instruction. 491 MI->RemoveOperand(0); // Remove the explicit ST(0) operand 492 MI->setOpcode(getConcreteOpcode(MI->getOpcode())); 493 494 // Result gets pushed on the stack. 495 pushReg(DestReg); 496} 497 498/// handleOneArgFP - fst <mem>, ST(0) 499/// 500void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) { 501 MachineInstr *MI = I; 502 assert((MI->getNumOperands() == 5 || MI->getNumOperands() == 1) && 503 "Can only handle fst* & ftst instructions!"); 504 505 // Is this the last use of the source register? 506 unsigned Reg = getFPReg(MI->getOperand(MI->getNumOperands()-1)); 507 bool KillsSrc = LV->KillsRegister(MI, X86::FP0+Reg); 508 509 // FISTP64m is strange because there isn't a non-popping versions. 510 // If we have one _and_ we don't want to pop the operand, duplicate the value 511 // on the stack instead of moving it. This ensure that popping the value is 512 // always ok. 513 // Ditto FISTTP16m, FISTTP32m, FISTTP64m. 514 // 515 if (!KillsSrc && 516 (MI->getOpcode() == X86::FpIST64m || 517 MI->getOpcode() == X86::FpISTT16m || 518 MI->getOpcode() == X86::FpISTT32m || 519 MI->getOpcode() == X86::FpISTT64m)) { 520 duplicateToTop(Reg, 7 /*temp register*/, I); 521 } else { 522 moveToTop(Reg, I); // Move to the top of the stack... 523 } 524 525 // Convert from the pseudo instruction to the concrete instruction. 526 MI->RemoveOperand(MI->getNumOperands()-1); // Remove explicit ST(0) operand 527 MI->setOpcode(getConcreteOpcode(MI->getOpcode())); 528 529 if (MI->getOpcode() == X86::FISTP64m || 530 MI->getOpcode() == X86::FISTTP16m || 531 MI->getOpcode() == X86::FISTTP32m || 532 MI->getOpcode() == X86::FISTTP64m) { 533 assert(StackTop > 0 && "Stack empty??"); 534 --StackTop; 535 } else if (KillsSrc) { // Last use of operand? 536 popStackAfter(I); 537 } 538} 539 540 541/// handleOneArgFPRW: Handle instructions that read from the top of stack and 542/// replace the value with a newly computed value. These instructions may have 543/// non-fp operands after their FP operands. 544/// 545/// Examples: 546/// R1 = fchs R2 547/// R1 = fadd R2, [mem] 548/// 549void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) { 550 MachineInstr *MI = I; 551 assert(MI->getNumOperands() >= 2 && "FPRW instructions must have 2 ops!!"); 552 553 // Is this the last use of the source register? 554 unsigned Reg = getFPReg(MI->getOperand(1)); 555 bool KillsSrc = LV->KillsRegister(MI, X86::FP0+Reg); 556 557 if (KillsSrc) { 558 // If this is the last use of the source register, just make sure it's on 559 // the top of the stack. 560 moveToTop(Reg, I); 561 assert(StackTop > 0 && "Stack cannot be empty!"); 562 --StackTop; 563 pushReg(getFPReg(MI->getOperand(0))); 564 } else { 565 // If this is not the last use of the source register, _copy_ it to the top 566 // of the stack. 567 duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I); 568 } 569 570 // Change from the pseudo instruction to the concrete instruction. 571 MI->RemoveOperand(1); // Drop the source operand. 572 MI->RemoveOperand(0); // Drop the destination operand. 573 MI->setOpcode(getConcreteOpcode(MI->getOpcode())); 574} 575 576 577//===----------------------------------------------------------------------===// 578// Define tables of various ways to map pseudo instructions 579// 580 581// ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i) 582static const TableEntry ForwardST0Table[] = { 583 { X86::FpADD , X86::FADDST0r }, 584 { X86::FpDIV , X86::FDIVST0r }, 585 { X86::FpMUL , X86::FMULST0r }, 586 { X86::FpSUB , X86::FSUBST0r }, 587}; 588 589// ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0) 590static const TableEntry ReverseST0Table[] = { 591 { X86::FpADD , X86::FADDST0r }, // commutative 592 { X86::FpDIV , X86::FDIVRST0r }, 593 { X86::FpMUL , X86::FMULST0r }, // commutative 594 { X86::FpSUB , X86::FSUBRST0r }, 595}; 596 597// ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i) 598static const TableEntry ForwardSTiTable[] = { 599 { X86::FpADD , X86::FADDrST0 }, // commutative 600 { X86::FpDIV , X86::FDIVRrST0 }, 601 { X86::FpMUL , X86::FMULrST0 }, // commutative 602 { X86::FpSUB , X86::FSUBRrST0 }, 603}; 604 605// ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0) 606static const TableEntry ReverseSTiTable[] = { 607 { X86::FpADD , X86::FADDrST0 }, 608 { X86::FpDIV , X86::FDIVrST0 }, 609 { X86::FpMUL , X86::FMULrST0 }, 610 { X86::FpSUB , X86::FSUBrST0 }, 611}; 612 613 614/// handleTwoArgFP - Handle instructions like FADD and friends which are virtual 615/// instructions which need to be simplified and possibly transformed. 616/// 617/// Result: ST(0) = fsub ST(0), ST(i) 618/// ST(i) = fsub ST(0), ST(i) 619/// ST(0) = fsubr ST(0), ST(i) 620/// ST(i) = fsubr ST(0), ST(i) 621/// 622void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) { 623 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table); 624 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable); 625 MachineInstr *MI = I; 626 627 unsigned NumOperands = MI->getNumOperands(); 628 assert(NumOperands == 3 && "Illegal TwoArgFP instruction!"); 629 unsigned Dest = getFPReg(MI->getOperand(0)); 630 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2)); 631 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1)); 632 bool KillsOp0 = LV->KillsRegister(MI, X86::FP0+Op0); 633 bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1); 634 635 unsigned TOS = getStackEntry(0); 636 637 // One of our operands must be on the top of the stack. If neither is yet, we 638 // need to move one. 639 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS? 640 // We can choose to move either operand to the top of the stack. If one of 641 // the operands is killed by this instruction, we want that one so that we 642 // can update right on top of the old version. 643 if (KillsOp0) { 644 moveToTop(Op0, I); // Move dead operand to TOS. 645 TOS = Op0; 646 } else if (KillsOp1) { 647 moveToTop(Op1, I); 648 TOS = Op1; 649 } else { 650 // All of the operands are live after this instruction executes, so we 651 // cannot update on top of any operand. Because of this, we must 652 // duplicate one of the stack elements to the top. It doesn't matter 653 // which one we pick. 654 // 655 duplicateToTop(Op0, Dest, I); 656 Op0 = TOS = Dest; 657 KillsOp0 = true; 658 } 659 } else if (!KillsOp0 && !KillsOp1) { 660 // If we DO have one of our operands at the top of the stack, but we don't 661 // have a dead operand, we must duplicate one of the operands to a new slot 662 // on the stack. 663 duplicateToTop(Op0, Dest, I); 664 Op0 = TOS = Dest; 665 KillsOp0 = true; 666 } 667 668 // Now we know that one of our operands is on the top of the stack, and at 669 // least one of our operands is killed by this instruction. 670 assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) && 671 "Stack conditions not set up right!"); 672 673 // We decide which form to use based on what is on the top of the stack, and 674 // which operand is killed by this instruction. 675 const TableEntry *InstTable; 676 bool isForward = TOS == Op0; 677 bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0); 678 if (updateST0) { 679 if (isForward) 680 InstTable = ForwardST0Table; 681 else 682 InstTable = ReverseST0Table; 683 } else { 684 if (isForward) 685 InstTable = ForwardSTiTable; 686 else 687 InstTable = ReverseSTiTable; 688 } 689 690 int Opcode = Lookup(InstTable, ARRAY_SIZE(ForwardST0Table), MI->getOpcode()); 691 assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!"); 692 693 // NotTOS - The register which is not on the top of stack... 694 unsigned NotTOS = (TOS == Op0) ? Op1 : Op0; 695 696 // Replace the old instruction with a new instruction 697 MBB->remove(I++); 698 I = BuildMI(*MBB, I, Opcode, 1).addReg(getSTReg(NotTOS)); 699 700 // If both operands are killed, pop one off of the stack in addition to 701 // overwriting the other one. 702 if (KillsOp0 && KillsOp1 && Op0 != Op1) { 703 assert(!updateST0 && "Should have updated other operand!"); 704 popStackAfter(I); // Pop the top of stack 705 } 706 707 // Update stack information so that we know the destination register is now on 708 // the stack. 709 unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS); 710 assert(UpdatedSlot < StackTop && Dest < 7); 711 Stack[UpdatedSlot] = Dest; 712 RegMap[Dest] = UpdatedSlot; 713 delete MI; // Remove the old instruction 714} 715 716/// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP 717/// register arguments and no explicit destinations. 718/// 719void FPS::handleCompareFP(MachineBasicBlock::iterator &I) { 720 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table); 721 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable); 722 MachineInstr *MI = I; 723 724 unsigned NumOperands = MI->getNumOperands(); 725 assert(NumOperands == 2 && "Illegal FUCOM* instruction!"); 726 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2)); 727 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1)); 728 bool KillsOp0 = LV->KillsRegister(MI, X86::FP0+Op0); 729 bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1); 730 731 // Make sure the first operand is on the top of stack, the other one can be 732 // anywhere. 733 moveToTop(Op0, I); 734 735 // Change from the pseudo instruction to the concrete instruction. 736 MI->getOperand(0).setReg(getSTReg(Op1)); 737 MI->RemoveOperand(1); 738 MI->setOpcode(getConcreteOpcode(MI->getOpcode())); 739 740 // If any of the operands are killed by this instruction, free them. 741 if (KillsOp0) freeStackSlotAfter(I, Op0); 742 if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1); 743} 744 745/// handleCondMovFP - Handle two address conditional move instructions. These 746/// instructions move a st(i) register to st(0) iff a condition is true. These 747/// instructions require that the first operand is at the top of the stack, but 748/// otherwise don't modify the stack at all. 749void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) { 750 MachineInstr *MI = I; 751 752 unsigned Op0 = getFPReg(MI->getOperand(0)); 753 unsigned Op1 = getFPReg(MI->getOperand(1)); 754 755 // The first operand *must* be on the top of the stack. 756 moveToTop(Op0, I); 757 758 // Change the second operand to the stack register that the operand is in. 759 // Change from the pseudo instruction to the concrete instruction. 760 MI->RemoveOperand(0); 761 MI->getOperand(0).setReg(getSTReg(Op1)); 762 MI->setOpcode(getConcreteOpcode(MI->getOpcode())); 763 764 765 // If we kill the second operand, make sure to pop it from the stack. 766 if (Op0 != Op1 && LV->KillsRegister(MI, X86::FP0+Op1)) { 767 // Get this value off of the register stack. 768 freeStackSlotAfter(I, Op1); 769 } 770} 771 772 773/// handleSpecialFP - Handle special instructions which behave unlike other 774/// floating point instructions. This is primarily intended for use by pseudo 775/// instructions. 776/// 777void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) { 778 MachineInstr *MI = I; 779 switch (MI->getOpcode()) { 780 default: assert(0 && "Unknown SpecialFP instruction!"); 781 case X86::FpGETRESULT: // Appears immediately after a call returning FP type! 782 assert(StackTop == 0 && "Stack should be empty after a call!"); 783 pushReg(getFPReg(MI->getOperand(0))); 784 break; 785 case X86::FpSETRESULT: 786 assert(StackTop == 1 && "Stack should have one element on it to return!"); 787 --StackTop; // "Forget" we have something on the top of stack! 788 break; 789 case X86::FpMOV: { 790 unsigned SrcReg = getFPReg(MI->getOperand(1)); 791 unsigned DestReg = getFPReg(MI->getOperand(0)); 792 793 if (LV->KillsRegister(MI, X86::FP0+SrcReg)) { 794 // If the input operand is killed, we can just change the owner of the 795 // incoming stack slot into the result. 796 unsigned Slot = getSlot(SrcReg); 797 assert(Slot < 7 && DestReg < 7 && "FpMOV operands invalid!"); 798 Stack[Slot] = DestReg; 799 RegMap[DestReg] = Slot; 800 801 } else { 802 // For FMOV we just duplicate the specified value to a new stack slot. 803 // This could be made better, but would require substantial changes. 804 duplicateToTop(SrcReg, DestReg, I); 805 } 806 break; 807 } 808 } 809 810 I = MBB->erase(I); // Remove the pseudo instruction 811 --I; 812} 813