X86FloatingPoint.cpp revision 7db1e7a527bc74e605da6ea86eb67945d8f17b07 
1//===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the pass which converts floating point instructions from
11// virtual registers into register stack instructions.  This pass uses live
12// variable information to indicate where the FPn registers are used and their
13// lifetimes.
14//
15// This pass is hampered by the lack of decent CFG manipulation routines for
16// machine code.  In particular, this wants to be able to split critical edges
17// as necessary, traverse the machine basic block CFG in depth-first order, and
18// allow there to be multiple machine basic blocks for each LLVM basicblock
19// (needed for critical edge splitting).
20//
21// In particular, this pass currently barfs on critical edges.  Because of this,
22// it requires the instruction selector to insert FP_REG_KILL instructions on
23// the exits of any basic block that has critical edges going from it, or which
24// branch to a critical basic block.
25//
26// FIXME: this is not implemented yet.  The stackifier pass only works on local
27// basic blocks.
28//
29//===----------------------------------------------------------------------===//
30
31#define DEBUG_TYPE "x86-codegen"
32#include "X86.h"
33#include "X86InstrInfo.h"
34#include "llvm/ADT/DepthFirstIterator.h"
35#include "llvm/ADT/SmallPtrSet.h"
36#include "llvm/ADT/SmallVector.h"
37#include "llvm/ADT/Statistic.h"
38#include "llvm/ADT/STLExtras.h"
39#include "llvm/CodeGen/MachineFunctionPass.h"
40#include "llvm/CodeGen/MachineInstrBuilder.h"
41#include "llvm/CodeGen/MachineRegisterInfo.h"
42#include "llvm/CodeGen/Passes.h"
43#include "llvm/Support/Debug.h"
44#include "llvm/Support/ErrorHandling.h"
45#include "llvm/Support/raw_ostream.h"
46#include "llvm/Target/TargetInstrInfo.h"
47#include "llvm/Target/TargetMachine.h"
48#include <algorithm>
49using namespace llvm;
50
51STATISTIC(NumFXCH, "Number of fxch instructions inserted");
52STATISTIC(NumFP  , "Number of floating point instructions");
53
54namespace {
55  struct FPS : public MachineFunctionPass {
56    static char ID;
57    FPS() : MachineFunctionPass(&ID) {}
58
59    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
60      AU.setPreservesCFG();
61      AU.addPreservedID(MachineLoopInfoID);
62      AU.addPreservedID(MachineDominatorsID);
63      MachineFunctionPass::getAnalysisUsage(AU);
64    }
65
66    virtual bool runOnMachineFunction(MachineFunction &MF);
67
68    virtual const char *getPassName() const { return "X86 FP Stackifier"; }
69
70  private:
71    const TargetInstrInfo *TII; // Machine instruction info.
72    MachineBasicBlock *MBB;     // Current basic block
73    unsigned Stack[8];          // FP<n> Registers in each stack slot...
74    unsigned RegMap[8];         // Track which stack slot contains each register
75    unsigned StackTop;          // The current top of the FP stack.
76
77    void dumpStack() const {
78      dbgs() << "Stack contents:";
79      for (unsigned i = 0; i != StackTop; ++i) {
80        dbgs() << " FP" << Stack[i];
81        assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
82      }
83      dbgs() << "\n";
84    }
85  private:
86    /// isStackEmpty - Return true if the FP stack is empty.
87    bool isStackEmpty() const {
88      return StackTop == 0;
89    }
90
91    // getSlot - Return the stack slot number a particular register number is
92    // in.
93    unsigned getSlot(unsigned RegNo) const {
94      assert(RegNo < 8 && "Regno out of range!");
95      return RegMap[RegNo];
96    }
97
98    // getStackEntry - Return the X86::FP<n> register in register ST(i).
99    unsigned getStackEntry(unsigned STi) const {
100      assert(STi < StackTop && "Access past stack top!");
101      return Stack[StackTop-1-STi];
102    }
103
104    // getSTReg - Return the X86::ST(i) register which contains the specified
105    // FP<RegNo> register.
106    unsigned getSTReg(unsigned RegNo) const {
107      return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0;
108    }
109
110    // pushReg - Push the specified FP<n> register onto the stack.
111    void pushReg(unsigned Reg) {
112      assert(Reg < 8 && "Register number out of range!");
113      assert(StackTop < 8 && "Stack overflow!");
114      Stack[StackTop] = Reg;
115      RegMap[Reg] = StackTop++;
116    }
117
118    bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
119    void moveToTop(unsigned RegNo, MachineBasicBlock::iterator I) {
120      MachineInstr *MI = I;
121      DebugLoc dl = MI->getDebugLoc();
122      if (isAtTop(RegNo)) return;
123
124      unsigned STReg = getSTReg(RegNo);
125      unsigned RegOnTop = getStackEntry(0);
126
127      // Swap the slots the regs are in.
128      std::swap(RegMap[RegNo], RegMap[RegOnTop]);
129
130      // Swap stack slot contents.
131      assert(RegMap[RegOnTop] < StackTop);
132      std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
133
134      // Emit an fxch to update the runtime processors version of the state.
135      BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg);
136      ++NumFXCH;
137    }
138
139    void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) {
140      DebugLoc dl = I->getDebugLoc();
141      unsigned STReg = getSTReg(RegNo);
142      pushReg(AsReg);   // New register on top of stack
143
144      BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg);
145    }
146
147    // popStackAfter - Pop the current value off of the top of the FP stack
148    // after the specified instruction.
149    void popStackAfter(MachineBasicBlock::iterator &I);
150
151    // freeStackSlotAfter - Free the specified register from the register stack,
152    // so that it is no longer in a register.  If the register is currently at
153    // the top of the stack, we just pop the current instruction, otherwise we
154    // store the current top-of-stack into the specified slot, then pop the top
155    // of stack.
156    void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
157
158    bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
159
160    void handleZeroArgFP(MachineBasicBlock::iterator &I);
161    void handleOneArgFP(MachineBasicBlock::iterator &I);
162    void handleOneArgFPRW(MachineBasicBlock::iterator &I);
163    void handleTwoArgFP(MachineBasicBlock::iterator &I);
164    void handleCompareFP(MachineBasicBlock::iterator &I);
165    void handleCondMovFP(MachineBasicBlock::iterator &I);
166    void handleSpecialFP(MachineBasicBlock::iterator &I);
167
168    bool translateCopy(MachineInstr*);
169  };
170  char FPS::ID = 0;
171}
172
173FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); }
174
175/// getFPReg - Return the X86::FPx register number for the specified operand.
176/// For example, this returns 3 for X86::FP3.
177static unsigned getFPReg(const MachineOperand &MO) {
178  assert(MO.isReg() && "Expected an FP register!");
179  unsigned Reg = MO.getReg();
180  assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
181  return Reg - X86::FP0;
182}
183
184
185/// runOnMachineFunction - Loop over all of the basic blocks, transforming FP
186/// register references into FP stack references.
187///
188bool FPS::runOnMachineFunction(MachineFunction &MF) {
189  // We only need to run this pass if there are any FP registers used in this
190  // function.  If it is all integer, there is nothing for us to do!
191  bool FPIsUsed = false;
192
193  assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!");
194  for (unsigned i = 0; i <= 6; ++i)
195    if (MF.getRegInfo().isPhysRegUsed(X86::FP0+i)) {
196      FPIsUsed = true;
197      break;
198    }
199
200  // Early exit.
201  if (!FPIsUsed) return false;
202
203  TII = MF.getTarget().getInstrInfo();
204  StackTop = 0;
205
206  // Process the function in depth first order so that we process at least one
207  // of the predecessors for every reachable block in the function.
208  SmallPtrSet<MachineBasicBlock*, 8> Processed;
209  MachineBasicBlock *Entry = MF.begin();
210
211  bool Changed = false;
212  for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*, 8> >
213         I = df_ext_begin(Entry, Processed), E = df_ext_end(Entry, Processed);
214       I != E; ++I)
215    Changed |= processBasicBlock(MF, **I);
216
217  // Process any unreachable blocks in arbitrary order now.
218  if (MF.size() == Processed.size())
219    return Changed;
220
221  for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
222    if (Processed.insert(BB))
223      Changed |= processBasicBlock(MF, *BB);
224
225  return Changed;
226}
227
228/// processBasicBlock - Loop over all of the instructions in the basic block,
229/// transforming FP instructions into their stack form.
230///
231bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
232  bool Changed = false;
233  MBB = &BB;
234
235  for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
236    MachineInstr *MI = I;
237    uint64_t Flags = MI->getDesc().TSFlags;
238
239    unsigned FPInstClass = Flags & X86II::FPTypeMask;
240    if (MI->isInlineAsm())
241      FPInstClass = X86II::SpecialFP;
242
243    if (MI->isCopy() && translateCopy(MI))
244      FPInstClass = X86II::SpecialFP;
245
246    if (FPInstClass == X86II::NotFP)
247      continue;  // Efficiently ignore non-fp insts!
248
249    MachineInstr *PrevMI = 0;
250    if (I != BB.begin())
251      PrevMI = prior(I);
252
253    ++NumFP;  // Keep track of # of pseudo instrs
254    DEBUG(dbgs() << "\nFPInst:\t" << *MI);
255
256    // Get dead variables list now because the MI pointer may be deleted as part
257    // of processing!
258    SmallVector<unsigned, 8> DeadRegs;
259    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
260      const MachineOperand &MO = MI->getOperand(i);
261      if (MO.isReg() && MO.isDead())
262        DeadRegs.push_back(MO.getReg());
263    }
264
265    switch (FPInstClass) {
266    case X86II::ZeroArgFP:  handleZeroArgFP(I); break;
267    case X86II::OneArgFP:   handleOneArgFP(I);  break;  // fstp ST(0)
268    case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0))
269    case X86II::TwoArgFP:   handleTwoArgFP(I);  break;
270    case X86II::CompareFP:  handleCompareFP(I); break;
271    case X86II::CondMovFP:  handleCondMovFP(I); break;
272    case X86II::SpecialFP:  handleSpecialFP(I); break;
273    default: llvm_unreachable("Unknown FP Type!");
274    }
275
276    // Check to see if any of the values defined by this instruction are dead
277    // after definition.  If so, pop them.
278    for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
279      unsigned Reg = DeadRegs[i];
280      if (Reg >= X86::FP0 && Reg <= X86::FP6) {
281        DEBUG(dbgs() << "Register FP#" << Reg-X86::FP0 << " is dead!\n");
282        freeStackSlotAfter(I, Reg-X86::FP0);
283      }
284    }
285
286    // Print out all of the instructions expanded to if -debug
287    DEBUG(
288      MachineBasicBlock::iterator PrevI(PrevMI);
289      if (I == PrevI) {
290        dbgs() << "Just deleted pseudo instruction\n";
291      } else {
292        MachineBasicBlock::iterator Start = I;
293        // Rewind to first instruction newly inserted.
294        while (Start != BB.begin() && prior(Start) != PrevI) --Start;
295        dbgs() << "Inserted instructions:\n\t";
296        Start->print(dbgs(), &MF.getTarget());
297        while (++Start != llvm::next(I)) {}
298      }
299      dumpStack();
300    );
301
302    Changed = true;
303  }
304
305  assert(isStackEmpty() && "Stack not empty at end of basic block?");
306  return Changed;
307}
308
309//===----------------------------------------------------------------------===//
310// Efficient Lookup Table Support
311//===----------------------------------------------------------------------===//
312
313namespace {
314  struct TableEntry {
315    unsigned from;
316    unsigned to;
317    bool operator<(const TableEntry &TE) const { return from < TE.from; }
318    friend bool operator<(const TableEntry &TE, unsigned V) {
319      return TE.from < V;
320    }
321    friend bool operator<(unsigned V, const TableEntry &TE) {
322      return V < TE.from;
323    }
324  };
325}
326
327#ifndef NDEBUG
328static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
329  for (unsigned i = 0; i != NumEntries-1; ++i)
330    if (!(Table[i] < Table[i+1])) return false;
331  return true;
332}
333#endif
334
335static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) {
336  const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
337  if (I != Table+N && I->from == Opcode)
338    return I->to;
339  return -1;
340}
341
342#ifdef NDEBUG
343#define ASSERT_SORTED(TABLE)
344#else
345#define ASSERT_SORTED(TABLE)                                              \
346  { static bool TABLE##Checked = false;                                   \
347    if (!TABLE##Checked) {                                                \
348       assert(TableIsSorted(TABLE, array_lengthof(TABLE)) &&              \
349              "All lookup tables must be sorted for efficient access!");  \
350       TABLE##Checked = true;                                             \
351    }                                                                     \
352  }
353#endif
354
355//===----------------------------------------------------------------------===//
356// Register File -> Register Stack Mapping Methods
357//===----------------------------------------------------------------------===//
358
359// OpcodeTable - Sorted map of register instructions to their stack version.
360// The first element is an register file pseudo instruction, the second is the
361// concrete X86 instruction which uses the register stack.
362//
363static const TableEntry OpcodeTable[] = {
364  { X86::ABS_Fp32     , X86::ABS_F     },
365  { X86::ABS_Fp64     , X86::ABS_F     },
366  { X86::ABS_Fp80     , X86::ABS_F     },
367  { X86::ADD_Fp32m    , X86::ADD_F32m  },
368  { X86::ADD_Fp64m    , X86::ADD_F64m  },
369  { X86::ADD_Fp64m32  , X86::ADD_F32m  },
370  { X86::ADD_Fp80m32  , X86::ADD_F32m  },
371  { X86::ADD_Fp80m64  , X86::ADD_F64m  },
372  { X86::ADD_FpI16m32 , X86::ADD_FI16m },
373  { X86::ADD_FpI16m64 , X86::ADD_FI16m },
374  { X86::ADD_FpI16m80 , X86::ADD_FI16m },
375  { X86::ADD_FpI32m32 , X86::ADD_FI32m },
376  { X86::ADD_FpI32m64 , X86::ADD_FI32m },
377  { X86::ADD_FpI32m80 , X86::ADD_FI32m },
378  { X86::CHS_Fp32     , X86::CHS_F     },
379  { X86::CHS_Fp64     , X86::CHS_F     },
380  { X86::CHS_Fp80     , X86::CHS_F     },
381  { X86::CMOVBE_Fp32  , X86::CMOVBE_F  },
382  { X86::CMOVBE_Fp64  , X86::CMOVBE_F  },
383  { X86::CMOVBE_Fp80  , X86::CMOVBE_F  },
384  { X86::CMOVB_Fp32   , X86::CMOVB_F   },
385  { X86::CMOVB_Fp64   , X86::CMOVB_F  },
386  { X86::CMOVB_Fp80   , X86::CMOVB_F  },
387  { X86::CMOVE_Fp32   , X86::CMOVE_F  },
388  { X86::CMOVE_Fp64   , X86::CMOVE_F   },
389  { X86::CMOVE_Fp80   , X86::CMOVE_F   },
390  { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F },
391  { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F },
392  { X86::CMOVNBE_Fp80 , X86::CMOVNBE_F },
393  { X86::CMOVNB_Fp32  , X86::CMOVNB_F  },
394  { X86::CMOVNB_Fp64  , X86::CMOVNB_F  },
395  { X86::CMOVNB_Fp80  , X86::CMOVNB_F  },
396  { X86::CMOVNE_Fp32  , X86::CMOVNE_F  },
397  { X86::CMOVNE_Fp64  , X86::CMOVNE_F  },
398  { X86::CMOVNE_Fp80  , X86::CMOVNE_F  },
399  { X86::CMOVNP_Fp32  , X86::CMOVNP_F  },
400  { X86::CMOVNP_Fp64  , X86::CMOVNP_F  },
401  { X86::CMOVNP_Fp80  , X86::CMOVNP_F  },
402  { X86::CMOVP_Fp32   , X86::CMOVP_F   },
403  { X86::CMOVP_Fp64   , X86::CMOVP_F   },
404  { X86::CMOVP_Fp80   , X86::CMOVP_F   },
405  { X86::COS_Fp32     , X86::COS_F     },
406  { X86::COS_Fp64     , X86::COS_F     },
407  { X86::COS_Fp80     , X86::COS_F     },
408  { X86::DIVR_Fp32m   , X86::DIVR_F32m },
409  { X86::DIVR_Fp64m   , X86::DIVR_F64m },
410  { X86::DIVR_Fp64m32 , X86::DIVR_F32m },
411  { X86::DIVR_Fp80m32 , X86::DIVR_F32m },
412  { X86::DIVR_Fp80m64 , X86::DIVR_F64m },
413  { X86::DIVR_FpI16m32, X86::DIVR_FI16m},
414  { X86::DIVR_FpI16m64, X86::DIVR_FI16m},
415  { X86::DIVR_FpI16m80, X86::DIVR_FI16m},
416  { X86::DIVR_FpI32m32, X86::DIVR_FI32m},
417  { X86::DIVR_FpI32m64, X86::DIVR_FI32m},
418  { X86::DIVR_FpI32m80, X86::DIVR_FI32m},
419  { X86::DIV_Fp32m    , X86::DIV_F32m  },
420  { X86::DIV_Fp64m    , X86::DIV_F64m  },
421  { X86::DIV_Fp64m32  , X86::DIV_F32m  },
422  { X86::DIV_Fp80m32  , X86::DIV_F32m  },
423  { X86::DIV_Fp80m64  , X86::DIV_F64m  },
424  { X86::DIV_FpI16m32 , X86::DIV_FI16m },
425  { X86::DIV_FpI16m64 , X86::DIV_FI16m },
426  { X86::DIV_FpI16m80 , X86::DIV_FI16m },
427  { X86::DIV_FpI32m32 , X86::DIV_FI32m },
428  { X86::DIV_FpI32m64 , X86::DIV_FI32m },
429  { X86::DIV_FpI32m80 , X86::DIV_FI32m },
430  { X86::ILD_Fp16m32  , X86::ILD_F16m  },
431  { X86::ILD_Fp16m64  , X86::ILD_F16m  },
432  { X86::ILD_Fp16m80  , X86::ILD_F16m  },
433  { X86::ILD_Fp32m32  , X86::ILD_F32m  },
434  { X86::ILD_Fp32m64  , X86::ILD_F32m  },
435  { X86::ILD_Fp32m80  , X86::ILD_F32m  },
436  { X86::ILD_Fp64m32  , X86::ILD_F64m  },
437  { X86::ILD_Fp64m64  , X86::ILD_F64m  },
438  { X86::ILD_Fp64m80  , X86::ILD_F64m  },
439  { X86::ISTT_Fp16m32 , X86::ISTT_FP16m},
440  { X86::ISTT_Fp16m64 , X86::ISTT_FP16m},
441  { X86::ISTT_Fp16m80 , X86::ISTT_FP16m},
442  { X86::ISTT_Fp32m32 , X86::ISTT_FP32m},
443  { X86::ISTT_Fp32m64 , X86::ISTT_FP32m},
444  { X86::ISTT_Fp32m80 , X86::ISTT_FP32m},
445  { X86::ISTT_Fp64m32 , X86::ISTT_FP64m},
446  { X86::ISTT_Fp64m64 , X86::ISTT_FP64m},
447  { X86::ISTT_Fp64m80 , X86::ISTT_FP64m},
448  { X86::IST_Fp16m32  , X86::IST_F16m  },
449  { X86::IST_Fp16m64  , X86::IST_F16m  },
450  { X86::IST_Fp16m80  , X86::IST_F16m  },
451  { X86::IST_Fp32m32  , X86::IST_F32m  },
452  { X86::IST_Fp32m64  , X86::IST_F32m  },
453  { X86::IST_Fp32m80  , X86::IST_F32m  },
454  { X86::IST_Fp64m32  , X86::IST_FP64m },
455  { X86::IST_Fp64m64  , X86::IST_FP64m },
456  { X86::IST_Fp64m80  , X86::IST_FP64m },
457  { X86::LD_Fp032     , X86::LD_F0     },
458  { X86::LD_Fp064     , X86::LD_F0     },
459  { X86::LD_Fp080     , X86::LD_F0     },
460  { X86::LD_Fp132     , X86::LD_F1     },
461  { X86::LD_Fp164     , X86::LD_F1     },
462  { X86::LD_Fp180     , X86::LD_F1     },
463  { X86::LD_Fp32m     , X86::LD_F32m   },
464  { X86::LD_Fp32m64   , X86::LD_F32m   },
465  { X86::LD_Fp32m80   , X86::LD_F32m   },
466  { X86::LD_Fp64m     , X86::LD_F64m   },
467  { X86::LD_Fp64m80   , X86::LD_F64m   },
468  { X86::LD_Fp80m     , X86::LD_F80m   },
469  { X86::MUL_Fp32m    , X86::MUL_F32m  },
470  { X86::MUL_Fp64m    , X86::MUL_F64m  },
471  { X86::MUL_Fp64m32  , X86::MUL_F32m  },
472  { X86::MUL_Fp80m32  , X86::MUL_F32m  },
473  { X86::MUL_Fp80m64  , X86::MUL_F64m  },
474  { X86::MUL_FpI16m32 , X86::MUL_FI16m },
475  { X86::MUL_FpI16m64 , X86::MUL_FI16m },
476  { X86::MUL_FpI16m80 , X86::MUL_FI16m },
477  { X86::MUL_FpI32m32 , X86::MUL_FI32m },
478  { X86::MUL_FpI32m64 , X86::MUL_FI32m },
479  { X86::MUL_FpI32m80 , X86::MUL_FI32m },
480  { X86::SIN_Fp32     , X86::SIN_F     },
481  { X86::SIN_Fp64     , X86::SIN_F     },
482  { X86::SIN_Fp80     , X86::SIN_F     },
483  { X86::SQRT_Fp32    , X86::SQRT_F    },
484  { X86::SQRT_Fp64    , X86::SQRT_F    },
485  { X86::SQRT_Fp80    , X86::SQRT_F    },
486  { X86::ST_Fp32m     , X86::ST_F32m   },
487  { X86::ST_Fp64m     , X86::ST_F64m   },
488  { X86::ST_Fp64m32   , X86::ST_F32m   },
489  { X86::ST_Fp80m32   , X86::ST_F32m   },
490  { X86::ST_Fp80m64   , X86::ST_F64m   },
491  { X86::ST_FpP80m    , X86::ST_FP80m  },
492  { X86::SUBR_Fp32m   , X86::SUBR_F32m },
493  { X86::SUBR_Fp64m   , X86::SUBR_F64m },
494  { X86::SUBR_Fp64m32 , X86::SUBR_F32m },
495  { X86::SUBR_Fp80m32 , X86::SUBR_F32m },
496  { X86::SUBR_Fp80m64 , X86::SUBR_F64m },
497  { X86::SUBR_FpI16m32, X86::SUBR_FI16m},
498  { X86::SUBR_FpI16m64, X86::SUBR_FI16m},
499  { X86::SUBR_FpI16m80, X86::SUBR_FI16m},
500  { X86::SUBR_FpI32m32, X86::SUBR_FI32m},
501  { X86::SUBR_FpI32m64, X86::SUBR_FI32m},
502  { X86::SUBR_FpI32m80, X86::SUBR_FI32m},
503  { X86::SUB_Fp32m    , X86::SUB_F32m  },
504  { X86::SUB_Fp64m    , X86::SUB_F64m  },
505  { X86::SUB_Fp64m32  , X86::SUB_F32m  },
506  { X86::SUB_Fp80m32  , X86::SUB_F32m  },
507  { X86::SUB_Fp80m64  , X86::SUB_F64m  },
508  { X86::SUB_FpI16m32 , X86::SUB_FI16m },
509  { X86::SUB_FpI16m64 , X86::SUB_FI16m },
510  { X86::SUB_FpI16m80 , X86::SUB_FI16m },
511  { X86::SUB_FpI32m32 , X86::SUB_FI32m },
512  { X86::SUB_FpI32m64 , X86::SUB_FI32m },
513  { X86::SUB_FpI32m80 , X86::SUB_FI32m },
514  { X86::TST_Fp32     , X86::TST_F     },
515  { X86::TST_Fp64     , X86::TST_F     },
516  { X86::TST_Fp80     , X86::TST_F     },
517  { X86::UCOM_FpIr32  , X86::UCOM_FIr  },
518  { X86::UCOM_FpIr64  , X86::UCOM_FIr  },
519  { X86::UCOM_FpIr80  , X86::UCOM_FIr  },
520  { X86::UCOM_Fpr32   , X86::UCOM_Fr   },
521  { X86::UCOM_Fpr64   , X86::UCOM_Fr   },
522  { X86::UCOM_Fpr80   , X86::UCOM_Fr   },
523};
524
525static unsigned getConcreteOpcode(unsigned Opcode) {
526  ASSERT_SORTED(OpcodeTable);
527  int Opc = Lookup(OpcodeTable, array_lengthof(OpcodeTable), Opcode);
528  assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!");
529  return Opc;
530}
531
532//===----------------------------------------------------------------------===//
533// Helper Methods
534//===----------------------------------------------------------------------===//
535
536// PopTable - Sorted map of instructions to their popping version.  The first
537// element is an instruction, the second is the version which pops.
538//
539static const TableEntry PopTable[] = {
540  { X86::ADD_FrST0 , X86::ADD_FPrST0  },
541
542  { X86::DIVR_FrST0, X86::DIVR_FPrST0 },
543  { X86::DIV_FrST0 , X86::DIV_FPrST0  },
544
545  { X86::IST_F16m  , X86::IST_FP16m   },
546  { X86::IST_F32m  , X86::IST_FP32m   },
547
548  { X86::MUL_FrST0 , X86::MUL_FPrST0  },
549
550  { X86::ST_F32m   , X86::ST_FP32m    },
551  { X86::ST_F64m   , X86::ST_FP64m    },
552  { X86::ST_Frr    , X86::ST_FPrr     },
553
554  { X86::SUBR_FrST0, X86::SUBR_FPrST0 },
555  { X86::SUB_FrST0 , X86::SUB_FPrST0  },
556
557  { X86::UCOM_FIr  , X86::UCOM_FIPr   },
558
559  { X86::UCOM_FPr  , X86::UCOM_FPPr   },
560  { X86::UCOM_Fr   , X86::UCOM_FPr    },
561};
562
563/// popStackAfter - Pop the current value off of the top of the FP stack after
564/// the specified instruction.  This attempts to be sneaky and combine the pop
565/// into the instruction itself if possible.  The iterator is left pointing to
566/// the last instruction, be it a new pop instruction inserted, or the old
567/// instruction if it was modified in place.
568///
569void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
570  MachineInstr* MI = I;
571  DebugLoc dl = MI->getDebugLoc();
572  ASSERT_SORTED(PopTable);
573  assert(StackTop > 0 && "Cannot pop empty stack!");
574  RegMap[Stack[--StackTop]] = ~0;     // Update state
575
576  // Check to see if there is a popping version of this instruction...
577  int Opcode = Lookup(PopTable, array_lengthof(PopTable), I->getOpcode());
578  if (Opcode != -1) {
579    I->setDesc(TII->get(Opcode));
580    if (Opcode == X86::UCOM_FPPr)
581      I->RemoveOperand(0);
582  } else {    // Insert an explicit pop
583    I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
584  }
585}
586
587/// freeStackSlotAfter - Free the specified register from the register stack, so
588/// that it is no longer in a register.  If the register is currently at the top
589/// of the stack, we just pop the current instruction, otherwise we store the
590/// current top-of-stack into the specified slot, then pop the top of stack.
591void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) {
592  if (getStackEntry(0) == FPRegNo) {  // already at the top of stack? easy.
593    popStackAfter(I);
594    return;
595  }
596
597  // Otherwise, store the top of stack into the dead slot, killing the operand
598  // without having to add in an explicit xchg then pop.
599  //
600  unsigned STReg    = getSTReg(FPRegNo);
601  unsigned OldSlot  = getSlot(FPRegNo);
602  unsigned TopReg   = Stack[StackTop-1];
603  Stack[OldSlot]    = TopReg;
604  RegMap[TopReg]    = OldSlot;
605  RegMap[FPRegNo]   = ~0;
606  Stack[--StackTop] = ~0;
607  MachineInstr *MI  = I;
608  DebugLoc dl = MI->getDebugLoc();
609  I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(STReg);
610}
611
612
613//===----------------------------------------------------------------------===//
614// Instruction transformation implementation
615//===----------------------------------------------------------------------===//
616
617/// handleZeroArgFP - ST(0) = fld0    ST(0) = flds <mem>
618///
619void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
620  MachineInstr *MI = I;
621  unsigned DestReg = getFPReg(MI->getOperand(0));
622
623  // Change from the pseudo instruction to the concrete instruction.
624  MI->RemoveOperand(0);   // Remove the explicit ST(0) operand
625  MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
626
627  // Result gets pushed on the stack.
628  pushReg(DestReg);
629}
630
631/// handleOneArgFP - fst <mem>, ST(0)
632///
633void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
634  MachineInstr *MI = I;
635  unsigned NumOps = MI->getDesc().getNumOperands();
636  assert((NumOps == X86AddrNumOperands + 1 || NumOps == 1) &&
637         "Can only handle fst* & ftst instructions!");
638
639  // Is this the last use of the source register?
640  unsigned Reg = getFPReg(MI->getOperand(NumOps-1));
641  bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
642
643  // FISTP64m is strange because there isn't a non-popping versions.
644  // If we have one _and_ we don't want to pop the operand, duplicate the value
645  // on the stack instead of moving it.  This ensure that popping the value is
646  // always ok.
647  // Ditto FISTTP16m, FISTTP32m, FISTTP64m, ST_FpP80m.
648  //
649  if (!KillsSrc &&
650      (MI->getOpcode() == X86::IST_Fp64m32 ||
651       MI->getOpcode() == X86::ISTT_Fp16m32 ||
652       MI->getOpcode() == X86::ISTT_Fp32m32 ||
653       MI->getOpcode() == X86::ISTT_Fp64m32 ||
654       MI->getOpcode() == X86::IST_Fp64m64 ||
655       MI->getOpcode() == X86::ISTT_Fp16m64 ||
656       MI->getOpcode() == X86::ISTT_Fp32m64 ||
657       MI->getOpcode() == X86::ISTT_Fp64m64 ||
658       MI->getOpcode() == X86::IST_Fp64m80 ||
659       MI->getOpcode() == X86::ISTT_Fp16m80 ||
660       MI->getOpcode() == X86::ISTT_Fp32m80 ||
661       MI->getOpcode() == X86::ISTT_Fp64m80 ||
662       MI->getOpcode() == X86::ST_FpP80m)) {
663    duplicateToTop(Reg, 7 /*temp register*/, I);
664  } else {
665    moveToTop(Reg, I);            // Move to the top of the stack...
666  }
667
668  // Convert from the pseudo instruction to the concrete instruction.
669  MI->RemoveOperand(NumOps-1);    // Remove explicit ST(0) operand
670  MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
671
672  if (MI->getOpcode() == X86::IST_FP64m ||
673      MI->getOpcode() == X86::ISTT_FP16m ||
674      MI->getOpcode() == X86::ISTT_FP32m ||
675      MI->getOpcode() == X86::ISTT_FP64m ||
676      MI->getOpcode() == X86::ST_FP80m) {
677    assert(StackTop > 0 && "Stack empty??");
678    --StackTop;
679  } else if (KillsSrc) { // Last use of operand?
680    popStackAfter(I);
681  }
682}
683
684
685/// handleOneArgFPRW: Handle instructions that read from the top of stack and
686/// replace the value with a newly computed value.  These instructions may have
687/// non-fp operands after their FP operands.
688///
689///  Examples:
690///     R1 = fchs R2
691///     R1 = fadd R2, [mem]
692///
693void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
694  MachineInstr *MI = I;
695#ifndef NDEBUG
696  unsigned NumOps = MI->getDesc().getNumOperands();
697  assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
698#endif
699
700  // Is this the last use of the source register?
701  unsigned Reg = getFPReg(MI->getOperand(1));
702  bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
703
704  if (KillsSrc) {
705    // If this is the last use of the source register, just make sure it's on
706    // the top of the stack.
707    moveToTop(Reg, I);
708    assert(StackTop > 0 && "Stack cannot be empty!");
709    --StackTop;
710    pushReg(getFPReg(MI->getOperand(0)));
711  } else {
712    // If this is not the last use of the source register, _copy_ it to the top
713    // of the stack.
714    duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I);
715  }
716
717  // Change from the pseudo instruction to the concrete instruction.
718  MI->RemoveOperand(1);   // Drop the source operand.
719  MI->RemoveOperand(0);   // Drop the destination operand.
720  MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
721}
722
723
724//===----------------------------------------------------------------------===//
725// Define tables of various ways to map pseudo instructions
726//
727
728// ForwardST0Table - Map: A = B op C  into: ST(0) = ST(0) op ST(i)
729static const TableEntry ForwardST0Table[] = {
730  { X86::ADD_Fp32  , X86::ADD_FST0r },
731  { X86::ADD_Fp64  , X86::ADD_FST0r },
732  { X86::ADD_Fp80  , X86::ADD_FST0r },
733  { X86::DIV_Fp32  , X86::DIV_FST0r },
734  { X86::DIV_Fp64  , X86::DIV_FST0r },
735  { X86::DIV_Fp80  , X86::DIV_FST0r },
736  { X86::MUL_Fp32  , X86::MUL_FST0r },
737  { X86::MUL_Fp64  , X86::MUL_FST0r },
738  { X86::MUL_Fp80  , X86::MUL_FST0r },
739  { X86::SUB_Fp32  , X86::SUB_FST0r },
740  { X86::SUB_Fp64  , X86::SUB_FST0r },
741  { X86::SUB_Fp80  , X86::SUB_FST0r },
742};
743
744// ReverseST0Table - Map: A = B op C  into: ST(0) = ST(i) op ST(0)
745static const TableEntry ReverseST0Table[] = {
746  { X86::ADD_Fp32  , X86::ADD_FST0r  },   // commutative
747  { X86::ADD_Fp64  , X86::ADD_FST0r  },   // commutative
748  { X86::ADD_Fp80  , X86::ADD_FST0r  },   // commutative
749  { X86::DIV_Fp32  , X86::DIVR_FST0r },
750  { X86::DIV_Fp64  , X86::DIVR_FST0r },
751  { X86::DIV_Fp80  , X86::DIVR_FST0r },
752  { X86::MUL_Fp32  , X86::MUL_FST0r  },   // commutative
753  { X86::MUL_Fp64  , X86::MUL_FST0r  },   // commutative
754  { X86::MUL_Fp80  , X86::MUL_FST0r  },   // commutative
755  { X86::SUB_Fp32  , X86::SUBR_FST0r },
756  { X86::SUB_Fp64  , X86::SUBR_FST0r },
757  { X86::SUB_Fp80  , X86::SUBR_FST0r },
758};
759
760// ForwardSTiTable - Map: A = B op C  into: ST(i) = ST(0) op ST(i)
761static const TableEntry ForwardSTiTable[] = {
762  { X86::ADD_Fp32  , X86::ADD_FrST0  },   // commutative
763  { X86::ADD_Fp64  , X86::ADD_FrST0  },   // commutative
764  { X86::ADD_Fp80  , X86::ADD_FrST0  },   // commutative
765  { X86::DIV_Fp32  , X86::DIVR_FrST0 },
766  { X86::DIV_Fp64  , X86::DIVR_FrST0 },
767  { X86::DIV_Fp80  , X86::DIVR_FrST0 },
768  { X86::MUL_Fp32  , X86::MUL_FrST0  },   // commutative
769  { X86::MUL_Fp64  , X86::MUL_FrST0  },   // commutative
770  { X86::MUL_Fp80  , X86::MUL_FrST0  },   // commutative
771  { X86::SUB_Fp32  , X86::SUBR_FrST0 },
772  { X86::SUB_Fp64  , X86::SUBR_FrST0 },
773  { X86::SUB_Fp80  , X86::SUBR_FrST0 },
774};
775
776// ReverseSTiTable - Map: A = B op C  into: ST(i) = ST(i) op ST(0)
777static const TableEntry ReverseSTiTable[] = {
778  { X86::ADD_Fp32  , X86::ADD_FrST0 },
779  { X86::ADD_Fp64  , X86::ADD_FrST0 },
780  { X86::ADD_Fp80  , X86::ADD_FrST0 },
781  { X86::DIV_Fp32  , X86::DIV_FrST0 },
782  { X86::DIV_Fp64  , X86::DIV_FrST0 },
783  { X86::DIV_Fp80  , X86::DIV_FrST0 },
784  { X86::MUL_Fp32  , X86::MUL_FrST0 },
785  { X86::MUL_Fp64  , X86::MUL_FrST0 },
786  { X86::MUL_Fp80  , X86::MUL_FrST0 },
787  { X86::SUB_Fp32  , X86::SUB_FrST0 },
788  { X86::SUB_Fp64  , X86::SUB_FrST0 },
789  { X86::SUB_Fp80  , X86::SUB_FrST0 },
790};
791
792
793/// handleTwoArgFP - Handle instructions like FADD and friends which are virtual
794/// instructions which need to be simplified and possibly transformed.
795///
796/// Result: ST(0) = fsub  ST(0), ST(i)
797///         ST(i) = fsub  ST(0), ST(i)
798///         ST(0) = fsubr ST(0), ST(i)
799///         ST(i) = fsubr ST(0), ST(i)
800///
801void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
802  ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
803  ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
804  MachineInstr *MI = I;
805
806  unsigned NumOperands = MI->getDesc().getNumOperands();
807  assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
808  unsigned Dest = getFPReg(MI->getOperand(0));
809  unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
810  unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
811  bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
812  bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
813  DebugLoc dl = MI->getDebugLoc();
814
815  unsigned TOS = getStackEntry(0);
816
817  // One of our operands must be on the top of the stack.  If neither is yet, we
818  // need to move one.
819  if (Op0 != TOS && Op1 != TOS) {   // No operand at TOS?
820    // We can choose to move either operand to the top of the stack.  If one of
821    // the operands is killed by this instruction, we want that one so that we
822    // can update right on top of the old version.
823    if (KillsOp0) {
824      moveToTop(Op0, I);         // Move dead operand to TOS.
825      TOS = Op0;
826    } else if (KillsOp1) {
827      moveToTop(Op1, I);
828      TOS = Op1;
829    } else {
830      // All of the operands are live after this instruction executes, so we
831      // cannot update on top of any operand.  Because of this, we must
832      // duplicate one of the stack elements to the top.  It doesn't matter
833      // which one we pick.
834      //
835      duplicateToTop(Op0, Dest, I);
836      Op0 = TOS = Dest;
837      KillsOp0 = true;
838    }
839  } else if (!KillsOp0 && !KillsOp1) {
840    // If we DO have one of our operands at the top of the stack, but we don't
841    // have a dead operand, we must duplicate one of the operands to a new slot
842    // on the stack.
843    duplicateToTop(Op0, Dest, I);
844    Op0 = TOS = Dest;
845    KillsOp0 = true;
846  }
847
848  // Now we know that one of our operands is on the top of the stack, and at
849  // least one of our operands is killed by this instruction.
850  assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) &&
851         "Stack conditions not set up right!");
852
853  // We decide which form to use based on what is on the top of the stack, and
854  // which operand is killed by this instruction.
855  const TableEntry *InstTable;
856  bool isForward = TOS == Op0;
857  bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0);
858  if (updateST0) {
859    if (isForward)
860      InstTable = ForwardST0Table;
861    else
862      InstTable = ReverseST0Table;
863  } else {
864    if (isForward)
865      InstTable = ForwardSTiTable;
866    else
867      InstTable = ReverseSTiTable;
868  }
869
870  int Opcode = Lookup(InstTable, array_lengthof(ForwardST0Table),
871                      MI->getOpcode());
872  assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
873
874  // NotTOS - The register which is not on the top of stack...
875  unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
876
877  // Replace the old instruction with a new instruction
878  MBB->remove(I++);
879  I = BuildMI(*MBB, I, dl, TII->get(Opcode)).addReg(getSTReg(NotTOS));
880
881  // If both operands are killed, pop one off of the stack in addition to
882  // overwriting the other one.
883  if (KillsOp0 && KillsOp1 && Op0 != Op1) {
884    assert(!updateST0 && "Should have updated other operand!");
885    popStackAfter(I);   // Pop the top of stack
886  }
887
888  // Update stack information so that we know the destination register is now on
889  // the stack.
890  unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS);
891  assert(UpdatedSlot < StackTop && Dest < 7);
892  Stack[UpdatedSlot]   = Dest;
893  RegMap[Dest]         = UpdatedSlot;
894  MBB->getParent()->DeleteMachineInstr(MI); // Remove the old instruction
895}
896
897/// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP
898/// register arguments and no explicit destinations.
899///
900void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
901  ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
902  ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
903  MachineInstr *MI = I;
904
905  unsigned NumOperands = MI->getDesc().getNumOperands();
906  assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
907  unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
908  unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
909  bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
910  bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
911
912  // Make sure the first operand is on the top of stack, the other one can be
913  // anywhere.
914  moveToTop(Op0, I);
915
916  // Change from the pseudo instruction to the concrete instruction.
917  MI->getOperand(0).setReg(getSTReg(Op1));
918  MI->RemoveOperand(1);
919  MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
920
921  // If any of the operands are killed by this instruction, free them.
922  if (KillsOp0) freeStackSlotAfter(I, Op0);
923  if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1);
924}
925
926/// handleCondMovFP - Handle two address conditional move instructions.  These
927/// instructions move a st(i) register to st(0) iff a condition is true.  These
928/// instructions require that the first operand is at the top of the stack, but
929/// otherwise don't modify the stack at all.
930void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
931  MachineInstr *MI = I;
932
933  unsigned Op0 = getFPReg(MI->getOperand(0));
934  unsigned Op1 = getFPReg(MI->getOperand(2));
935  bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
936
937  // The first operand *must* be on the top of the stack.
938  moveToTop(Op0, I);
939
940  // Change the second operand to the stack register that the operand is in.
941  // Change from the pseudo instruction to the concrete instruction.
942  MI->RemoveOperand(0);
943  MI->RemoveOperand(1);
944  MI->getOperand(0).setReg(getSTReg(Op1));
945  MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
946
947  // If we kill the second operand, make sure to pop it from the stack.
948  if (Op0 != Op1 && KillsOp1) {
949    // Get this value off of the register stack.
950    freeStackSlotAfter(I, Op1);
951  }
952}
953
954
955/// handleSpecialFP - Handle special instructions which behave unlike other
956/// floating point instructions.  This is primarily intended for use by pseudo
957/// instructions.
958///
959void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
960  MachineInstr *MI = I;
961  DebugLoc dl = MI->getDebugLoc();
962  switch (MI->getOpcode()) {
963  default: llvm_unreachable("Unknown SpecialFP instruction!");
964  case X86::FpGET_ST0_32:// Appears immediately after a call returning FP type!
965  case X86::FpGET_ST0_64:// Appears immediately after a call returning FP type!
966  case X86::FpGET_ST0_80:// Appears immediately after a call returning FP type!
967    assert(StackTop == 0 && "Stack should be empty after a call!");
968    pushReg(getFPReg(MI->getOperand(0)));
969    break;
970  case X86::FpGET_ST1_32:// Appears immediately after a call returning FP type!
971  case X86::FpGET_ST1_64:// Appears immediately after a call returning FP type!
972  case X86::FpGET_ST1_80:{// Appears immediately after a call returning FP type!
973    // FpGET_ST1 should occur right after a FpGET_ST0 for a call or inline asm.
974    // The pattern we expect is:
975    //  CALL
976    //  FP1 = FpGET_ST0
977    //  FP4 = FpGET_ST1
978    //
979    // At this point, we've pushed FP1 on the top of stack, so it should be
980    // present if it isn't dead.  If it was dead, we already emitted a pop to
981    // remove it from the stack and StackTop = 0.
982
983    // Push FP4 as top of stack next.
984    pushReg(getFPReg(MI->getOperand(0)));
985
986    // If StackTop was 0 before we pushed our operand, then ST(0) must have been
987    // dead.  In this case, the ST(1) value is the only thing that is live, so
988    // it should be on the TOS (after the pop that was emitted) and is.  Just
989    // continue in this case.
990    if (StackTop == 1)
991      break;
992
993    // Because pushReg just pushed ST(1) as TOS, we now have to swap the two top
994    // elements so that our accounting is correct.
995    unsigned RegOnTop = getStackEntry(0);
996    unsigned RegNo = getStackEntry(1);
997
998    // Swap the slots the regs are in.
999    std::swap(RegMap[RegNo], RegMap[RegOnTop]);
1000
1001    // Swap stack slot contents.
1002    assert(RegMap[RegOnTop] < StackTop);
1003    std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
1004    break;
1005  }
1006  case X86::FpSET_ST0_32:
1007  case X86::FpSET_ST0_64:
1008  case X86::FpSET_ST0_80: {
1009    unsigned Op0 = getFPReg(MI->getOperand(0));
1010
1011    // FpSET_ST0_80 is generated by copyRegToReg for both function return
1012    // and inline assembly with the "st" constrain. In the latter case,
1013    // it is possible for ST(0) to be alive after this instruction.
1014    if (!MI->killsRegister(X86::FP0 + Op0)) {
1015      // Duplicate Op0
1016      duplicateToTop(0, 7 /*temp register*/, I);
1017    } else {
1018      moveToTop(Op0, I);
1019    }
1020    --StackTop;   // "Forget" we have something on the top of stack!
1021    break;
1022  }
1023  case X86::FpSET_ST1_32:
1024  case X86::FpSET_ST1_64:
1025  case X86::FpSET_ST1_80:
1026    // StackTop can be 1 if a FpSET_ST0_* was before this. Exchange them.
1027    if (StackTop == 1) {
1028      BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(X86::ST1);
1029      ++NumFXCH;
1030      StackTop = 0;
1031      break;
1032    }
1033    assert(StackTop == 2 && "Stack should have two element on it to return!");
1034    --StackTop;   // "Forget" we have something on the top of stack!
1035    break;
1036  case X86::MOV_Fp3232:
1037  case X86::MOV_Fp3264:
1038  case X86::MOV_Fp6432:
1039  case X86::MOV_Fp6464:
1040  case X86::MOV_Fp3280:
1041  case X86::MOV_Fp6480:
1042  case X86::MOV_Fp8032:
1043  case X86::MOV_Fp8064:
1044  case X86::MOV_Fp8080: {
1045    const MachineOperand &MO1 = MI->getOperand(1);
1046    unsigned SrcReg = getFPReg(MO1);
1047
1048    const MachineOperand &MO0 = MI->getOperand(0);
1049    // These can be created due to inline asm. Two address pass can introduce
1050    // copies from RFP registers to virtual registers.
1051    if (MO0.getReg() == X86::ST0 && SrcReg == 0) {
1052      assert(MO1.isKill());
1053      // Treat %ST0<def> = MOV_Fp8080 %FP0<kill>
1054      // like  FpSET_ST0_80 %FP0<kill>, %ST0<imp-def>
1055      assert((StackTop == 1 || StackTop == 2)
1056             && "Stack should have one or two element on it to return!");
1057      --StackTop;   // "Forget" we have something on the top of stack!
1058      break;
1059    } else if (MO0.getReg() == X86::ST1 && SrcReg == 1) {
1060      assert(MO1.isKill());
1061      // Treat %ST1<def> = MOV_Fp8080 %FP1<kill>
1062      // like  FpSET_ST1_80 %FP0<kill>, %ST1<imp-def>
1063      // StackTop can be 1 if a FpSET_ST0_* was before this. Exchange them.
1064      if (StackTop == 1) {
1065        BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(X86::ST1);
1066        ++NumFXCH;
1067        StackTop = 0;
1068        break;
1069      }
1070      assert(StackTop == 2 && "Stack should have two element on it to return!");
1071      --StackTop;   // "Forget" we have something on the top of stack!
1072      break;
1073    }
1074
1075    unsigned DestReg = getFPReg(MO0);
1076    if (MI->killsRegister(X86::FP0+SrcReg)) {
1077      // If the input operand is killed, we can just change the owner of the
1078      // incoming stack slot into the result.
1079      unsigned Slot = getSlot(SrcReg);
1080      assert(Slot < 7 && DestReg < 7 && "FpMOV operands invalid!");
1081      Stack[Slot] = DestReg;
1082      RegMap[DestReg] = Slot;
1083
1084    } else {
1085      // For FMOV we just duplicate the specified value to a new stack slot.
1086      // This could be made better, but would require substantial changes.
1087      duplicateToTop(SrcReg, DestReg, I);
1088    }
1089    }
1090    break;
1091  case TargetOpcode::INLINEASM: {
1092    // The inline asm MachineInstr currently only *uses* FP registers for the
1093    // 'f' constraint.  These should be turned into the current ST(x) register
1094    // in the machine instr.  Also, any kills should be explicitly popped after
1095    // the inline asm.
1096    unsigned Kills = 0;
1097    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1098      MachineOperand &Op = MI->getOperand(i);
1099      if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1100        continue;
1101      assert(Op.isUse() && "Only handle inline asm uses right now");
1102
1103      unsigned FPReg = getFPReg(Op);
1104      Op.setReg(getSTReg(FPReg));
1105
1106      // If we kill this operand, make sure to pop it from the stack after the
1107      // asm.  We just remember it for now, and pop them all off at the end in
1108      // a batch.
1109      if (Op.isKill())
1110        Kills |= 1U << FPReg;
1111    }
1112
1113    // If this asm kills any FP registers (is the last use of them) we must
1114    // explicitly emit pop instructions for them.  Do this now after the asm has
1115    // executed so that the ST(x) numbers are not off (which would happen if we
1116    // did this inline with operand rewriting).
1117    //
1118    // Note: this might be a non-optimal pop sequence.  We might be able to do
1119    // better by trying to pop in stack order or something.
1120    MachineBasicBlock::iterator InsertPt = MI;
1121    while (Kills) {
1122      unsigned FPReg = CountTrailingZeros_32(Kills);
1123      freeStackSlotAfter(InsertPt, FPReg);
1124      Kills &= ~(1U << FPReg);
1125    }
1126    // Don't delete the inline asm!
1127    return;
1128  }
1129
1130  case X86::RET:
1131  case X86::RETI:
1132    // If RET has an FP register use operand, pass the first one in ST(0) and
1133    // the second one in ST(1).
1134    if (isStackEmpty()) return;  // Quick check to see if any are possible.
1135
1136    // Find the register operands.
1137    unsigned FirstFPRegOp = ~0U, SecondFPRegOp = ~0U;
1138
1139    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1140      MachineOperand &Op = MI->getOperand(i);
1141      if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1142        continue;
1143      // FP Register uses must be kills unless there are two uses of the same
1144      // register, in which case only one will be a kill.
1145      assert(Op.isUse() &&
1146             (Op.isKill() ||                        // Marked kill.
1147              getFPReg(Op) == FirstFPRegOp ||       // Second instance.
1148              MI->killsRegister(Op.getReg())) &&    // Later use is marked kill.
1149             "Ret only defs operands, and values aren't live beyond it");
1150
1151      if (FirstFPRegOp == ~0U)
1152        FirstFPRegOp = getFPReg(Op);
1153      else {
1154        assert(SecondFPRegOp == ~0U && "More than two fp operands!");
1155        SecondFPRegOp = getFPReg(Op);
1156      }
1157
1158      // Remove the operand so that later passes don't see it.
1159      MI->RemoveOperand(i);
1160      --i, --e;
1161    }
1162
1163    // There are only four possibilities here:
1164    // 1) we are returning a single FP value.  In this case, it has to be in
1165    //    ST(0) already, so just declare success by removing the value from the
1166    //    FP Stack.
1167    if (SecondFPRegOp == ~0U) {
1168      // Assert that the top of stack contains the right FP register.
1169      assert(StackTop == 1 && FirstFPRegOp == getStackEntry(0) &&
1170             "Top of stack not the right register for RET!");
1171
1172      // Ok, everything is good, mark the value as not being on the stack
1173      // anymore so that our assertion about the stack being empty at end of
1174      // block doesn't fire.
1175      StackTop = 0;
1176      return;
1177    }
1178
1179    // Otherwise, we are returning two values:
1180    // 2) If returning the same value for both, we only have one thing in the FP
1181    //    stack.  Consider:  RET FP1, FP1
1182    if (StackTop == 1) {
1183      assert(FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry(0)&&
1184             "Stack misconfiguration for RET!");
1185
1186      // Duplicate the TOS so that we return it twice.  Just pick some other FPx
1187      // register to hold it.
1188      unsigned NewReg = (FirstFPRegOp+1)%7;
1189      duplicateToTop(FirstFPRegOp, NewReg, MI);
1190      FirstFPRegOp = NewReg;
1191    }
1192
1193    /// Okay we know we have two different FPx operands now:
1194    assert(StackTop == 2 && "Must have two values live!");
1195
1196    /// 3) If SecondFPRegOp is currently in ST(0) and FirstFPRegOp is currently
1197    ///    in ST(1).  In this case, emit an fxch.
1198    if (getStackEntry(0) == SecondFPRegOp) {
1199      assert(getStackEntry(1) == FirstFPRegOp && "Unknown regs live");
1200      moveToTop(FirstFPRegOp, MI);
1201    }
1202
1203    /// 4) Finally, FirstFPRegOp must be in ST(0) and SecondFPRegOp must be in
1204    /// ST(1).  Just remove both from our understanding of the stack and return.
1205    assert(getStackEntry(0) == FirstFPRegOp && "Unknown regs live");
1206    assert(getStackEntry(1) == SecondFPRegOp && "Unknown regs live");
1207    StackTop = 0;
1208    return;
1209  }
1210
1211  I = MBB->erase(I);  // Remove the pseudo instruction
1212  --I;
1213}
1214
1215// Translate a COPY instruction to a pseudo-op that handleSpecialFP understands.
1216bool FPS::translateCopy(MachineInstr *MI) {
1217  unsigned DstReg = MI->getOperand(0).getReg();
1218  unsigned SrcReg = MI->getOperand(1).getReg();
1219
1220  if (DstReg == X86::ST0) {
1221    MI->setDesc(TII->get(X86::FpSET_ST0_80));
1222    MI->RemoveOperand(0);
1223    return true;
1224  }
1225  if (DstReg == X86::ST1) {
1226    MI->setDesc(TII->get(X86::FpSET_ST1_80));
1227    MI->RemoveOperand(0);
1228    return true;
1229  }
1230  if (SrcReg == X86::ST0) {
1231    MI->setDesc(TII->get(X86::FpGET_ST0_80));
1232    return true;
1233  }
1234  if (SrcReg == X86::ST1) {
1235    MI->setDesc(TII->get(X86::FpGET_ST1_80));
1236    return true;
1237  }
1238  if (X86::RFP80RegClass.contains(DstReg, SrcReg)) {
1239    MI->setDesc(TII->get(X86::MOV_Fp8080));
1240    return true;
1241  }
1242  return false;
1243}
1244