X86FloatingPoint.cpp revision 86b98b58745f09ac7fc8cee5eac9caa5739045c0
1//===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the pass which converts floating point instructions from 11// pseudo registers into register stack instructions. This pass uses live 12// variable information to indicate where the FPn registers are used and their 13// lifetimes. 14// 15// The x87 hardware tracks liveness of the stack registers, so it is necessary 16// to implement exact liveness tracking between basic blocks. The CFG edges are 17// partitioned into bundles where the same FP registers must be live in 18// identical stack positions. Instructions are inserted at the end of each basic 19// block to rearrange the live registers to match the outgoing bundle. 20// 21// This approach avoids splitting critical edges at the potential cost of more 22// live register shuffling instructions when critical edges are present. 23// 24//===----------------------------------------------------------------------===// 25 26#define DEBUG_TYPE "x86-codegen" 27#include "X86.h" 28#include "X86InstrInfo.h" 29#include "llvm/ADT/DepthFirstIterator.h" 30#include "llvm/ADT/DenseMap.h" 31#include "llvm/ADT/SmallPtrSet.h" 32#include "llvm/ADT/SmallVector.h" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/ADT/STLExtras.h" 35#include "llvm/CodeGen/MachineFunctionPass.h" 36#include "llvm/CodeGen/MachineInstrBuilder.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/CodeGen/Passes.h" 39#include "llvm/Support/Debug.h" 40#include "llvm/Support/ErrorHandling.h" 41#include "llvm/Support/raw_ostream.h" 42#include "llvm/Target/TargetInstrInfo.h" 43#include "llvm/Target/TargetMachine.h" 44#include <algorithm> 45using namespace llvm; 46 47STATISTIC(NumFXCH, "Number of fxch instructions inserted"); 48STATISTIC(NumFP , "Number of floating point instructions"); 49 50namespace { 51 struct FPS : public MachineFunctionPass { 52 static char ID; 53 FPS() : MachineFunctionPass(ID) { 54 // This is really only to keep valgrind quiet. 55 // The logic in isLive() is too much for it. 56 memset(Stack, 0, sizeof(Stack)); 57 memset(RegMap, 0, sizeof(RegMap)); 58 } 59 60 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 61 AU.setPreservesCFG(); 62 AU.addPreservedID(MachineLoopInfoID); 63 AU.addPreservedID(MachineDominatorsID); 64 MachineFunctionPass::getAnalysisUsage(AU); 65 } 66 67 virtual bool runOnMachineFunction(MachineFunction &MF); 68 69 virtual const char *getPassName() const { return "X86 FP Stackifier"; } 70 71 private: 72 const TargetInstrInfo *TII; // Machine instruction info. 73 74 // Two CFG edges are related if they leave the same block, or enter the same 75 // block. The transitive closure of an edge under this relation is a 76 // LiveBundle. It represents a set of CFG edges where the live FP stack 77 // registers must be allocated identically in the x87 stack. 78 // 79 // A LiveBundle is usually all the edges leaving a block, or all the edges 80 // entering a block, but it can contain more edges if critical edges are 81 // present. 82 // 83 // The set of live FP registers in a LiveBundle is calculated by bundleCFG, 84 // but the exact mapping of FP registers to stack slots is fixed later. 85 struct LiveBundle { 86 // Bit mask of live FP registers. Bit 0 = FP0, bit 1 = FP1, &c. 87 unsigned Mask; 88 89 // Number of pre-assigned live registers in FixStack. This is 0 when the 90 // stack order has not yet been fixed. 91 unsigned FixCount; 92 93 // Assigned stack order for live-in registers. 94 // FixStack[i] == getStackEntry(i) for all i < FixCount. 95 unsigned char FixStack[8]; 96 97 LiveBundle(unsigned m = 0) : Mask(m), FixCount(0) {} 98 99 // Have the live registers been assigned a stack order yet? 100 bool isFixed() const { return !Mask || FixCount; } 101 }; 102 103 // Numbered LiveBundle structs. LiveBundles[0] is used for all CFG edges 104 // with no live FP registers. 105 SmallVector<LiveBundle, 8> LiveBundles; 106 107 // Map each MBB in the current function to an (ingoing, outgoing) index into 108 // LiveBundles. Blocks with no FP registers live in or out map to (0, 0) 109 // and are not actually stored in the map. 110 DenseMap<MachineBasicBlock*, std::pair<unsigned, unsigned> > BlockBundle; 111 112 // Return a bitmask of FP registers in block's live-in list. 113 unsigned calcLiveInMask(MachineBasicBlock *MBB) { 114 unsigned Mask = 0; 115 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(), 116 E = MBB->livein_end(); I != E; ++I) { 117 unsigned Reg = *I - X86::FP0; 118 if (Reg < 8) 119 Mask |= 1 << Reg; 120 } 121 return Mask; 122 } 123 124 // Partition all the CFG edges into LiveBundles. 125 void bundleCFG(MachineFunction &MF); 126 127 MachineBasicBlock *MBB; // Current basic block 128 unsigned Stack[8]; // FP<n> Registers in each stack slot... 129 unsigned RegMap[8]; // Track which stack slot contains each register 130 unsigned StackTop; // The current top of the FP stack. 131 132 // Set up our stack model to match the incoming registers to MBB. 133 void setupBlockStack(); 134 135 // Shuffle live registers to match the expectations of successor blocks. 136 void finishBlockStack(); 137 138 void dumpStack() const { 139 dbgs() << "Stack contents:"; 140 for (unsigned i = 0; i != StackTop; ++i) { 141 dbgs() << " FP" << Stack[i]; 142 assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!"); 143 } 144 dbgs() << "\n"; 145 } 146 147 /// getSlot - Return the stack slot number a particular register number is 148 /// in. 149 unsigned getSlot(unsigned RegNo) const { 150 assert(RegNo < 8 && "Regno out of range!"); 151 return RegMap[RegNo]; 152 } 153 154 /// isLive - Is RegNo currently live in the stack? 155 bool isLive(unsigned RegNo) const { 156 unsigned Slot = getSlot(RegNo); 157 return Slot < StackTop && Stack[Slot] == RegNo; 158 } 159 160 /// getScratchReg - Return an FP register that is not currently in use. 161 unsigned getScratchReg() { 162 for (int i = 7; i >= 0; --i) 163 if (!isLive(i)) 164 return i; 165 llvm_unreachable("Ran out of scratch FP registers"); 166 } 167 168 /// getStackEntry - Return the X86::FP<n> register in register ST(i). 169 unsigned getStackEntry(unsigned STi) const { 170 assert(STi < StackTop && "Access past stack top!"); 171 return Stack[StackTop-1-STi]; 172 } 173 174 /// getSTReg - Return the X86::ST(i) register which contains the specified 175 /// FP<RegNo> register. 176 unsigned getSTReg(unsigned RegNo) const { 177 return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0; 178 } 179 180 // pushReg - Push the specified FP<n> register onto the stack. 181 void pushReg(unsigned Reg) { 182 assert(Reg < 8 && "Register number out of range!"); 183 assert(StackTop < 8 && "Stack overflow!"); 184 Stack[StackTop] = Reg; 185 RegMap[Reg] = StackTop++; 186 } 187 188 bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; } 189 void moveToTop(unsigned RegNo, MachineBasicBlock::iterator I) { 190 DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc(); 191 if (isAtTop(RegNo)) return; 192 193 unsigned STReg = getSTReg(RegNo); 194 unsigned RegOnTop = getStackEntry(0); 195 196 // Swap the slots the regs are in. 197 std::swap(RegMap[RegNo], RegMap[RegOnTop]); 198 199 // Swap stack slot contents. 200 assert(RegMap[RegOnTop] < StackTop); 201 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]); 202 203 // Emit an fxch to update the runtime processors version of the state. 204 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg); 205 ++NumFXCH; 206 } 207 208 void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) { 209 DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc(); 210 unsigned STReg = getSTReg(RegNo); 211 pushReg(AsReg); // New register on top of stack 212 213 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg); 214 } 215 216 /// popStackAfter - Pop the current value off of the top of the FP stack 217 /// after the specified instruction. 218 void popStackAfter(MachineBasicBlock::iterator &I); 219 220 /// freeStackSlotAfter - Free the specified register from the register 221 /// stack, so that it is no longer in a register. If the register is 222 /// currently at the top of the stack, we just pop the current instruction, 223 /// otherwise we store the current top-of-stack into the specified slot, 224 /// then pop the top of stack. 225 void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg); 226 227 /// freeStackSlotBefore - Just the pop, no folding. Return the inserted 228 /// instruction. 229 MachineBasicBlock::iterator 230 freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo); 231 232 /// Adjust the live registers to be the set in Mask. 233 void adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I); 234 235 /// Shuffle the top FixCount stack entries susch that FP reg FixStack[0] is 236 /// st(0), FP reg FixStack[1] is st(1) etc. 237 void shuffleStackTop(const unsigned char *FixStack, unsigned FixCount, 238 MachineBasicBlock::iterator I); 239 240 bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB); 241 242 void handleZeroArgFP(MachineBasicBlock::iterator &I); 243 void handleOneArgFP(MachineBasicBlock::iterator &I); 244 void handleOneArgFPRW(MachineBasicBlock::iterator &I); 245 void handleTwoArgFP(MachineBasicBlock::iterator &I); 246 void handleCompareFP(MachineBasicBlock::iterator &I); 247 void handleCondMovFP(MachineBasicBlock::iterator &I); 248 void handleSpecialFP(MachineBasicBlock::iterator &I); 249 250 bool translateCopy(MachineInstr*); 251 }; 252 char FPS::ID = 0; 253} 254 255FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); } 256 257/// getFPReg - Return the X86::FPx register number for the specified operand. 258/// For example, this returns 3 for X86::FP3. 259static unsigned getFPReg(const MachineOperand &MO) { 260 assert(MO.isReg() && "Expected an FP register!"); 261 unsigned Reg = MO.getReg(); 262 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!"); 263 return Reg - X86::FP0; 264} 265 266/// runOnMachineFunction - Loop over all of the basic blocks, transforming FP 267/// register references into FP stack references. 268/// 269bool FPS::runOnMachineFunction(MachineFunction &MF) { 270 // We only need to run this pass if there are any FP registers used in this 271 // function. If it is all integer, there is nothing for us to do! 272 bool FPIsUsed = false; 273 274 assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!"); 275 for (unsigned i = 0; i <= 6; ++i) 276 if (MF.getRegInfo().isPhysRegUsed(X86::FP0+i)) { 277 FPIsUsed = true; 278 break; 279 } 280 281 // Early exit. 282 if (!FPIsUsed) return false; 283 284 TII = MF.getTarget().getInstrInfo(); 285 286 // Prepare cross-MBB liveness. 287 bundleCFG(MF); 288 289 StackTop = 0; 290 291 // Process the function in depth first order so that we process at least one 292 // of the predecessors for every reachable block in the function. 293 SmallPtrSet<MachineBasicBlock*, 8> Processed; 294 MachineBasicBlock *Entry = MF.begin(); 295 296 bool Changed = false; 297 for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*, 8> > 298 I = df_ext_begin(Entry, Processed), E = df_ext_end(Entry, Processed); 299 I != E; ++I) 300 Changed |= processBasicBlock(MF, **I); 301 302 // Process any unreachable blocks in arbitrary order now. 303 if (MF.size() != Processed.size()) 304 for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB) 305 if (Processed.insert(BB)) 306 Changed |= processBasicBlock(MF, *BB); 307 308 BlockBundle.clear(); 309 LiveBundles.clear(); 310 311 return Changed; 312} 313 314/// bundleCFG - Scan all the basic blocks to determine consistent live-in and 315/// live-out sets for the FP registers. Consistent means that the set of 316/// registers live-out from a block is identical to the live-in set of all 317/// successors. This is not enforced by the normal live-in lists since 318/// registers may be implicitly defined, or not used by all successors. 319void FPS::bundleCFG(MachineFunction &MF) { 320 assert(LiveBundles.empty() && "Stale data in LiveBundles"); 321 assert(BlockBundle.empty() && "Stale data in BlockBundle"); 322 SmallPtrSet<MachineBasicBlock*, 8> PropDown, PropUp; 323 324 // LiveBundle[0] is the empty live-in set. 325 LiveBundles.resize(1); 326 327 // First gather the actual live-in masks for all MBBs. 328 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) { 329 MachineBasicBlock *MBB = I; 330 const unsigned Mask = calcLiveInMask(MBB); 331 if (!Mask) 332 continue; 333 // Ingoing bundle index. 334 unsigned &Idx = BlockBundle[MBB].first; 335 // Already assigned an ingoing bundle? 336 if (Idx) 337 continue; 338 // Allocate a new LiveBundle struct for this block's live-ins. 339 const unsigned BundleIdx = Idx = LiveBundles.size(); 340 DEBUG(dbgs() << "Creating LB#" << BundleIdx << ": in:BB#" 341 << MBB->getNumber()); 342 LiveBundles.push_back(Mask); 343 LiveBundle &Bundle = LiveBundles.back(); 344 345 // Make sure all predecessors have the same live-out set. 346 PropUp.insert(MBB); 347 348 // Keep pushing liveness up and down the CFG until convergence. 349 // Only critical edges cause iteration here, but when they do, multiple 350 // blocks can be assigned to the same LiveBundle index. 351 do { 352 // Assign BundleIdx as liveout from predecessors in PropUp. 353 for (SmallPtrSet<MachineBasicBlock*, 16>::iterator I = PropUp.begin(), 354 E = PropUp.end(); I != E; ++I) { 355 MachineBasicBlock *MBB = *I; 356 for (MachineBasicBlock::const_pred_iterator LinkI = MBB->pred_begin(), 357 LinkE = MBB->pred_end(); LinkI != LinkE; ++LinkI) { 358 MachineBasicBlock *PredMBB = *LinkI; 359 // PredMBB's liveout bundle should be set to LIIdx. 360 unsigned &Idx = BlockBundle[PredMBB].second; 361 if (Idx) { 362 assert(Idx == BundleIdx && "Inconsistent CFG"); 363 continue; 364 } 365 Idx = BundleIdx; 366 DEBUG(dbgs() << " out:BB#" << PredMBB->getNumber()); 367 // Propagate to siblings. 368 if (PredMBB->succ_size() > 1) 369 PropDown.insert(PredMBB); 370 } 371 } 372 PropUp.clear(); 373 374 // Assign BundleIdx as livein to successors in PropDown. 375 for (SmallPtrSet<MachineBasicBlock*, 16>::iterator I = PropDown.begin(), 376 E = PropDown.end(); I != E; ++I) { 377 MachineBasicBlock *MBB = *I; 378 for (MachineBasicBlock::const_succ_iterator LinkI = MBB->succ_begin(), 379 LinkE = MBB->succ_end(); LinkI != LinkE; ++LinkI) { 380 MachineBasicBlock *SuccMBB = *LinkI; 381 // LinkMBB's livein bundle should be set to BundleIdx. 382 unsigned &Idx = BlockBundle[SuccMBB].first; 383 if (Idx) { 384 assert(Idx == BundleIdx && "Inconsistent CFG"); 385 continue; 386 } 387 Idx = BundleIdx; 388 DEBUG(dbgs() << " in:BB#" << SuccMBB->getNumber()); 389 // Propagate to siblings. 390 if (SuccMBB->pred_size() > 1) 391 PropUp.insert(SuccMBB); 392 // Also accumulate the bundle liveness mask from the liveins here. 393 Bundle.Mask |= calcLiveInMask(SuccMBB); 394 } 395 } 396 PropDown.clear(); 397 } while (!PropUp.empty()); 398 DEBUG({ 399 dbgs() << " live:"; 400 for (unsigned i = 0; i < 8; ++i) 401 if (Bundle.Mask & (1<<i)) 402 dbgs() << " %FP" << i; 403 dbgs() << '\n'; 404 }); 405 } 406} 407 408/// processBasicBlock - Loop over all of the instructions in the basic block, 409/// transforming FP instructions into their stack form. 410/// 411bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) { 412 bool Changed = false; 413 MBB = &BB; 414 415 setupBlockStack(); 416 417 for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) { 418 MachineInstr *MI = I; 419 uint64_t Flags = MI->getDesc().TSFlags; 420 421 unsigned FPInstClass = Flags & X86II::FPTypeMask; 422 if (MI->isInlineAsm()) 423 FPInstClass = X86II::SpecialFP; 424 425 if (MI->isCopy() && translateCopy(MI)) 426 FPInstClass = X86II::SpecialFP; 427 428 if (FPInstClass == X86II::NotFP) 429 continue; // Efficiently ignore non-fp insts! 430 431 MachineInstr *PrevMI = 0; 432 if (I != BB.begin()) 433 PrevMI = prior(I); 434 435 ++NumFP; // Keep track of # of pseudo instrs 436 DEBUG(dbgs() << "\nFPInst:\t" << *MI); 437 438 // Get dead variables list now because the MI pointer may be deleted as part 439 // of processing! 440 SmallVector<unsigned, 8> DeadRegs; 441 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 442 const MachineOperand &MO = MI->getOperand(i); 443 if (MO.isReg() && MO.isDead()) 444 DeadRegs.push_back(MO.getReg()); 445 } 446 447 switch (FPInstClass) { 448 case X86II::ZeroArgFP: handleZeroArgFP(I); break; 449 case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0) 450 case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0)) 451 case X86II::TwoArgFP: handleTwoArgFP(I); break; 452 case X86II::CompareFP: handleCompareFP(I); break; 453 case X86II::CondMovFP: handleCondMovFP(I); break; 454 case X86II::SpecialFP: handleSpecialFP(I); break; 455 default: llvm_unreachable("Unknown FP Type!"); 456 } 457 458 // Check to see if any of the values defined by this instruction are dead 459 // after definition. If so, pop them. 460 for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) { 461 unsigned Reg = DeadRegs[i]; 462 if (Reg >= X86::FP0 && Reg <= X86::FP6) { 463 DEBUG(dbgs() << "Register FP#" << Reg-X86::FP0 << " is dead!\n"); 464 freeStackSlotAfter(I, Reg-X86::FP0); 465 } 466 } 467 468 // Print out all of the instructions expanded to if -debug 469 DEBUG( 470 MachineBasicBlock::iterator PrevI(PrevMI); 471 if (I == PrevI) { 472 dbgs() << "Just deleted pseudo instruction\n"; 473 } else { 474 MachineBasicBlock::iterator Start = I; 475 // Rewind to first instruction newly inserted. 476 while (Start != BB.begin() && prior(Start) != PrevI) --Start; 477 dbgs() << "Inserted instructions:\n\t"; 478 Start->print(dbgs(), &MF.getTarget()); 479 while (++Start != llvm::next(I)) {} 480 } 481 dumpStack(); 482 ); 483 484 Changed = true; 485 } 486 487 finishBlockStack(); 488 489 return Changed; 490} 491 492/// setupBlockStack - Use the BlockBundle map to set up our model of the stack 493/// to match predecessors' live out stack. 494void FPS::setupBlockStack() { 495 DEBUG(dbgs() << "\nSetting up live-ins for BB#" << MBB->getNumber() 496 << " derived from " << MBB->getName() << ".\n"); 497 StackTop = 0; 498 const LiveBundle &Bundle = LiveBundles[BlockBundle.lookup(MBB).first]; 499 500 if (!Bundle.Mask) { 501 DEBUG(dbgs() << "Block has no FP live-ins.\n"); 502 return; 503 } 504 505 // Depth-first iteration should ensure that we always have an assigned stack. 506 assert(Bundle.isFixed() && "Reached block before any predecessors"); 507 508 // Push the fixed live-in registers. 509 for (unsigned i = Bundle.FixCount; i > 0; --i) { 510 MBB->addLiveIn(X86::ST0+i-1); 511 DEBUG(dbgs() << "Live-in st(" << (i-1) << "): %FP" 512 << unsigned(Bundle.FixStack[i-1]) << '\n'); 513 pushReg(Bundle.FixStack[i-1]); 514 } 515 516 // Kill off unwanted live-ins. This can happen with a critical edge. 517 // FIXME: We could keep these live registers around as zombies. They may need 518 // to be revived at the end of a short block. It might save a few instrs. 519 adjustLiveRegs(calcLiveInMask(MBB), MBB->begin()); 520 DEBUG(MBB->dump()); 521} 522 523/// finishBlockStack - Revive live-outs that are implicitly defined out of 524/// MBB. Shuffle live registers to match the expected fixed stack of any 525/// predecessors, and ensure that all predecessors are expecting the same 526/// stack. 527void FPS::finishBlockStack() { 528 // The RET handling below takes care of return blocks for us. 529 if (MBB->succ_empty()) 530 return; 531 532 DEBUG(dbgs() << "Setting up live-outs for BB#" << MBB->getNumber() 533 << " derived from " << MBB->getName() << ".\n"); 534 535 unsigned BundleIdx = BlockBundle.lookup(MBB).second; 536 LiveBundle &Bundle = LiveBundles[BundleIdx]; 537 538 // We may need to kill and define some registers to match successors. 539 // FIXME: This can probably be combined with the shuffle below. 540 MachineBasicBlock::iterator Term = MBB->getFirstTerminator(); 541 adjustLiveRegs(Bundle.Mask, Term); 542 543 if (!Bundle.Mask) { 544 DEBUG(dbgs() << "No live-outs.\n"); 545 return; 546 } 547 548 // Has the stack order been fixed yet? 549 DEBUG(dbgs() << "LB#" << BundleIdx << ": "); 550 if (Bundle.isFixed()) { 551 DEBUG(dbgs() << "Shuffling stack to match.\n"); 552 shuffleStackTop(Bundle.FixStack, Bundle.FixCount, Term); 553 } else { 554 // Not fixed yet, we get to choose. 555 DEBUG(dbgs() << "Fixing stack order now.\n"); 556 Bundle.FixCount = StackTop; 557 for (unsigned i = 0; i < StackTop; ++i) 558 Bundle.FixStack[i] = getStackEntry(i); 559 } 560} 561 562 563//===----------------------------------------------------------------------===// 564// Efficient Lookup Table Support 565//===----------------------------------------------------------------------===// 566 567namespace { 568 struct TableEntry { 569 unsigned from; 570 unsigned to; 571 bool operator<(const TableEntry &TE) const { return from < TE.from; } 572 friend bool operator<(const TableEntry &TE, unsigned V) { 573 return TE.from < V; 574 } 575 friend bool ATTRIBUTE_USED operator<(unsigned V, const TableEntry &TE) { 576 return V < TE.from; 577 } 578 }; 579} 580 581#ifndef NDEBUG 582static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) { 583 for (unsigned i = 0; i != NumEntries-1; ++i) 584 if (!(Table[i] < Table[i+1])) return false; 585 return true; 586} 587#endif 588 589static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) { 590 const TableEntry *I = std::lower_bound(Table, Table+N, Opcode); 591 if (I != Table+N && I->from == Opcode) 592 return I->to; 593 return -1; 594} 595 596#ifdef NDEBUG 597#define ASSERT_SORTED(TABLE) 598#else 599#define ASSERT_SORTED(TABLE) \ 600 { static bool TABLE##Checked = false; \ 601 if (!TABLE##Checked) { \ 602 assert(TableIsSorted(TABLE, array_lengthof(TABLE)) && \ 603 "All lookup tables must be sorted for efficient access!"); \ 604 TABLE##Checked = true; \ 605 } \ 606 } 607#endif 608 609//===----------------------------------------------------------------------===// 610// Register File -> Register Stack Mapping Methods 611//===----------------------------------------------------------------------===// 612 613// OpcodeTable - Sorted map of register instructions to their stack version. 614// The first element is an register file pseudo instruction, the second is the 615// concrete X86 instruction which uses the register stack. 616// 617static const TableEntry OpcodeTable[] = { 618 { X86::ABS_Fp32 , X86::ABS_F }, 619 { X86::ABS_Fp64 , X86::ABS_F }, 620 { X86::ABS_Fp80 , X86::ABS_F }, 621 { X86::ADD_Fp32m , X86::ADD_F32m }, 622 { X86::ADD_Fp64m , X86::ADD_F64m }, 623 { X86::ADD_Fp64m32 , X86::ADD_F32m }, 624 { X86::ADD_Fp80m32 , X86::ADD_F32m }, 625 { X86::ADD_Fp80m64 , X86::ADD_F64m }, 626 { X86::ADD_FpI16m32 , X86::ADD_FI16m }, 627 { X86::ADD_FpI16m64 , X86::ADD_FI16m }, 628 { X86::ADD_FpI16m80 , X86::ADD_FI16m }, 629 { X86::ADD_FpI32m32 , X86::ADD_FI32m }, 630 { X86::ADD_FpI32m64 , X86::ADD_FI32m }, 631 { X86::ADD_FpI32m80 , X86::ADD_FI32m }, 632 { X86::CHS_Fp32 , X86::CHS_F }, 633 { X86::CHS_Fp64 , X86::CHS_F }, 634 { X86::CHS_Fp80 , X86::CHS_F }, 635 { X86::CMOVBE_Fp32 , X86::CMOVBE_F }, 636 { X86::CMOVBE_Fp64 , X86::CMOVBE_F }, 637 { X86::CMOVBE_Fp80 , X86::CMOVBE_F }, 638 { X86::CMOVB_Fp32 , X86::CMOVB_F }, 639 { X86::CMOVB_Fp64 , X86::CMOVB_F }, 640 { X86::CMOVB_Fp80 , X86::CMOVB_F }, 641 { X86::CMOVE_Fp32 , X86::CMOVE_F }, 642 { X86::CMOVE_Fp64 , X86::CMOVE_F }, 643 { X86::CMOVE_Fp80 , X86::CMOVE_F }, 644 { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F }, 645 { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F }, 646 { X86::CMOVNBE_Fp80 , X86::CMOVNBE_F }, 647 { X86::CMOVNB_Fp32 , X86::CMOVNB_F }, 648 { X86::CMOVNB_Fp64 , X86::CMOVNB_F }, 649 { X86::CMOVNB_Fp80 , X86::CMOVNB_F }, 650 { X86::CMOVNE_Fp32 , X86::CMOVNE_F }, 651 { X86::CMOVNE_Fp64 , X86::CMOVNE_F }, 652 { X86::CMOVNE_Fp80 , X86::CMOVNE_F }, 653 { X86::CMOVNP_Fp32 , X86::CMOVNP_F }, 654 { X86::CMOVNP_Fp64 , X86::CMOVNP_F }, 655 { X86::CMOVNP_Fp80 , X86::CMOVNP_F }, 656 { X86::CMOVP_Fp32 , X86::CMOVP_F }, 657 { X86::CMOVP_Fp64 , X86::CMOVP_F }, 658 { X86::CMOVP_Fp80 , X86::CMOVP_F }, 659 { X86::COS_Fp32 , X86::COS_F }, 660 { X86::COS_Fp64 , X86::COS_F }, 661 { X86::COS_Fp80 , X86::COS_F }, 662 { X86::DIVR_Fp32m , X86::DIVR_F32m }, 663 { X86::DIVR_Fp64m , X86::DIVR_F64m }, 664 { X86::DIVR_Fp64m32 , X86::DIVR_F32m }, 665 { X86::DIVR_Fp80m32 , X86::DIVR_F32m }, 666 { X86::DIVR_Fp80m64 , X86::DIVR_F64m }, 667 { X86::DIVR_FpI16m32, X86::DIVR_FI16m}, 668 { X86::DIVR_FpI16m64, X86::DIVR_FI16m}, 669 { X86::DIVR_FpI16m80, X86::DIVR_FI16m}, 670 { X86::DIVR_FpI32m32, X86::DIVR_FI32m}, 671 { X86::DIVR_FpI32m64, X86::DIVR_FI32m}, 672 { X86::DIVR_FpI32m80, X86::DIVR_FI32m}, 673 { X86::DIV_Fp32m , X86::DIV_F32m }, 674 { X86::DIV_Fp64m , X86::DIV_F64m }, 675 { X86::DIV_Fp64m32 , X86::DIV_F32m }, 676 { X86::DIV_Fp80m32 , X86::DIV_F32m }, 677 { X86::DIV_Fp80m64 , X86::DIV_F64m }, 678 { X86::DIV_FpI16m32 , X86::DIV_FI16m }, 679 { X86::DIV_FpI16m64 , X86::DIV_FI16m }, 680 { X86::DIV_FpI16m80 , X86::DIV_FI16m }, 681 { X86::DIV_FpI32m32 , X86::DIV_FI32m }, 682 { X86::DIV_FpI32m64 , X86::DIV_FI32m }, 683 { X86::DIV_FpI32m80 , X86::DIV_FI32m }, 684 { X86::ILD_Fp16m32 , X86::ILD_F16m }, 685 { X86::ILD_Fp16m64 , X86::ILD_F16m }, 686 { X86::ILD_Fp16m80 , X86::ILD_F16m }, 687 { X86::ILD_Fp32m32 , X86::ILD_F32m }, 688 { X86::ILD_Fp32m64 , X86::ILD_F32m }, 689 { X86::ILD_Fp32m80 , X86::ILD_F32m }, 690 { X86::ILD_Fp64m32 , X86::ILD_F64m }, 691 { X86::ILD_Fp64m64 , X86::ILD_F64m }, 692 { X86::ILD_Fp64m80 , X86::ILD_F64m }, 693 { X86::ISTT_Fp16m32 , X86::ISTT_FP16m}, 694 { X86::ISTT_Fp16m64 , X86::ISTT_FP16m}, 695 { X86::ISTT_Fp16m80 , X86::ISTT_FP16m}, 696 { X86::ISTT_Fp32m32 , X86::ISTT_FP32m}, 697 { X86::ISTT_Fp32m64 , X86::ISTT_FP32m}, 698 { X86::ISTT_Fp32m80 , X86::ISTT_FP32m}, 699 { X86::ISTT_Fp64m32 , X86::ISTT_FP64m}, 700 { X86::ISTT_Fp64m64 , X86::ISTT_FP64m}, 701 { X86::ISTT_Fp64m80 , X86::ISTT_FP64m}, 702 { X86::IST_Fp16m32 , X86::IST_F16m }, 703 { X86::IST_Fp16m64 , X86::IST_F16m }, 704 { X86::IST_Fp16m80 , X86::IST_F16m }, 705 { X86::IST_Fp32m32 , X86::IST_F32m }, 706 { X86::IST_Fp32m64 , X86::IST_F32m }, 707 { X86::IST_Fp32m80 , X86::IST_F32m }, 708 { X86::IST_Fp64m32 , X86::IST_FP64m }, 709 { X86::IST_Fp64m64 , X86::IST_FP64m }, 710 { X86::IST_Fp64m80 , X86::IST_FP64m }, 711 { X86::LD_Fp032 , X86::LD_F0 }, 712 { X86::LD_Fp064 , X86::LD_F0 }, 713 { X86::LD_Fp080 , X86::LD_F0 }, 714 { X86::LD_Fp132 , X86::LD_F1 }, 715 { X86::LD_Fp164 , X86::LD_F1 }, 716 { X86::LD_Fp180 , X86::LD_F1 }, 717 { X86::LD_Fp32m , X86::LD_F32m }, 718 { X86::LD_Fp32m64 , X86::LD_F32m }, 719 { X86::LD_Fp32m80 , X86::LD_F32m }, 720 { X86::LD_Fp64m , X86::LD_F64m }, 721 { X86::LD_Fp64m80 , X86::LD_F64m }, 722 { X86::LD_Fp80m , X86::LD_F80m }, 723 { X86::MUL_Fp32m , X86::MUL_F32m }, 724 { X86::MUL_Fp64m , X86::MUL_F64m }, 725 { X86::MUL_Fp64m32 , X86::MUL_F32m }, 726 { X86::MUL_Fp80m32 , X86::MUL_F32m }, 727 { X86::MUL_Fp80m64 , X86::MUL_F64m }, 728 { X86::MUL_FpI16m32 , X86::MUL_FI16m }, 729 { X86::MUL_FpI16m64 , X86::MUL_FI16m }, 730 { X86::MUL_FpI16m80 , X86::MUL_FI16m }, 731 { X86::MUL_FpI32m32 , X86::MUL_FI32m }, 732 { X86::MUL_FpI32m64 , X86::MUL_FI32m }, 733 { X86::MUL_FpI32m80 , X86::MUL_FI32m }, 734 { X86::SIN_Fp32 , X86::SIN_F }, 735 { X86::SIN_Fp64 , X86::SIN_F }, 736 { X86::SIN_Fp80 , X86::SIN_F }, 737 { X86::SQRT_Fp32 , X86::SQRT_F }, 738 { X86::SQRT_Fp64 , X86::SQRT_F }, 739 { X86::SQRT_Fp80 , X86::SQRT_F }, 740 { X86::ST_Fp32m , X86::ST_F32m }, 741 { X86::ST_Fp64m , X86::ST_F64m }, 742 { X86::ST_Fp64m32 , X86::ST_F32m }, 743 { X86::ST_Fp80m32 , X86::ST_F32m }, 744 { X86::ST_Fp80m64 , X86::ST_F64m }, 745 { X86::ST_FpP80m , X86::ST_FP80m }, 746 { X86::SUBR_Fp32m , X86::SUBR_F32m }, 747 { X86::SUBR_Fp64m , X86::SUBR_F64m }, 748 { X86::SUBR_Fp64m32 , X86::SUBR_F32m }, 749 { X86::SUBR_Fp80m32 , X86::SUBR_F32m }, 750 { X86::SUBR_Fp80m64 , X86::SUBR_F64m }, 751 { X86::SUBR_FpI16m32, X86::SUBR_FI16m}, 752 { X86::SUBR_FpI16m64, X86::SUBR_FI16m}, 753 { X86::SUBR_FpI16m80, X86::SUBR_FI16m}, 754 { X86::SUBR_FpI32m32, X86::SUBR_FI32m}, 755 { X86::SUBR_FpI32m64, X86::SUBR_FI32m}, 756 { X86::SUBR_FpI32m80, X86::SUBR_FI32m}, 757 { X86::SUB_Fp32m , X86::SUB_F32m }, 758 { X86::SUB_Fp64m , X86::SUB_F64m }, 759 { X86::SUB_Fp64m32 , X86::SUB_F32m }, 760 { X86::SUB_Fp80m32 , X86::SUB_F32m }, 761 { X86::SUB_Fp80m64 , X86::SUB_F64m }, 762 { X86::SUB_FpI16m32 , X86::SUB_FI16m }, 763 { X86::SUB_FpI16m64 , X86::SUB_FI16m }, 764 { X86::SUB_FpI16m80 , X86::SUB_FI16m }, 765 { X86::SUB_FpI32m32 , X86::SUB_FI32m }, 766 { X86::SUB_FpI32m64 , X86::SUB_FI32m }, 767 { X86::SUB_FpI32m80 , X86::SUB_FI32m }, 768 { X86::TST_Fp32 , X86::TST_F }, 769 { X86::TST_Fp64 , X86::TST_F }, 770 { X86::TST_Fp80 , X86::TST_F }, 771 { X86::UCOM_FpIr32 , X86::UCOM_FIr }, 772 { X86::UCOM_FpIr64 , X86::UCOM_FIr }, 773 { X86::UCOM_FpIr80 , X86::UCOM_FIr }, 774 { X86::UCOM_Fpr32 , X86::UCOM_Fr }, 775 { X86::UCOM_Fpr64 , X86::UCOM_Fr }, 776 { X86::UCOM_Fpr80 , X86::UCOM_Fr }, 777}; 778 779static unsigned getConcreteOpcode(unsigned Opcode) { 780 ASSERT_SORTED(OpcodeTable); 781 int Opc = Lookup(OpcodeTable, array_lengthof(OpcodeTable), Opcode); 782 assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!"); 783 return Opc; 784} 785 786//===----------------------------------------------------------------------===// 787// Helper Methods 788//===----------------------------------------------------------------------===// 789 790// PopTable - Sorted map of instructions to their popping version. The first 791// element is an instruction, the second is the version which pops. 792// 793static const TableEntry PopTable[] = { 794 { X86::ADD_FrST0 , X86::ADD_FPrST0 }, 795 796 { X86::DIVR_FrST0, X86::DIVR_FPrST0 }, 797 { X86::DIV_FrST0 , X86::DIV_FPrST0 }, 798 799 { X86::IST_F16m , X86::IST_FP16m }, 800 { X86::IST_F32m , X86::IST_FP32m }, 801 802 { X86::MUL_FrST0 , X86::MUL_FPrST0 }, 803 804 { X86::ST_F32m , X86::ST_FP32m }, 805 { X86::ST_F64m , X86::ST_FP64m }, 806 { X86::ST_Frr , X86::ST_FPrr }, 807 808 { X86::SUBR_FrST0, X86::SUBR_FPrST0 }, 809 { X86::SUB_FrST0 , X86::SUB_FPrST0 }, 810 811 { X86::UCOM_FIr , X86::UCOM_FIPr }, 812 813 { X86::UCOM_FPr , X86::UCOM_FPPr }, 814 { X86::UCOM_Fr , X86::UCOM_FPr }, 815}; 816 817/// popStackAfter - Pop the current value off of the top of the FP stack after 818/// the specified instruction. This attempts to be sneaky and combine the pop 819/// into the instruction itself if possible. The iterator is left pointing to 820/// the last instruction, be it a new pop instruction inserted, or the old 821/// instruction if it was modified in place. 822/// 823void FPS::popStackAfter(MachineBasicBlock::iterator &I) { 824 MachineInstr* MI = I; 825 DebugLoc dl = MI->getDebugLoc(); 826 ASSERT_SORTED(PopTable); 827 assert(StackTop > 0 && "Cannot pop empty stack!"); 828 RegMap[Stack[--StackTop]] = ~0; // Update state 829 830 // Check to see if there is a popping version of this instruction... 831 int Opcode = Lookup(PopTable, array_lengthof(PopTable), I->getOpcode()); 832 if (Opcode != -1) { 833 I->setDesc(TII->get(Opcode)); 834 if (Opcode == X86::UCOM_FPPr) 835 I->RemoveOperand(0); 836 } else { // Insert an explicit pop 837 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0); 838 } 839} 840 841/// freeStackSlotAfter - Free the specified register from the register stack, so 842/// that it is no longer in a register. If the register is currently at the top 843/// of the stack, we just pop the current instruction, otherwise we store the 844/// current top-of-stack into the specified slot, then pop the top of stack. 845void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) { 846 if (getStackEntry(0) == FPRegNo) { // already at the top of stack? easy. 847 popStackAfter(I); 848 return; 849 } 850 851 // Otherwise, store the top of stack into the dead slot, killing the operand 852 // without having to add in an explicit xchg then pop. 853 // 854 I = freeStackSlotBefore(++I, FPRegNo); 855} 856 857/// freeStackSlotBefore - Free the specified register without trying any 858/// folding. 859MachineBasicBlock::iterator 860FPS::freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo) { 861 unsigned STReg = getSTReg(FPRegNo); 862 unsigned OldSlot = getSlot(FPRegNo); 863 unsigned TopReg = Stack[StackTop-1]; 864 Stack[OldSlot] = TopReg; 865 RegMap[TopReg] = OldSlot; 866 RegMap[FPRegNo] = ~0; 867 Stack[--StackTop] = ~0; 868 return BuildMI(*MBB, I, DebugLoc(), TII->get(X86::ST_FPrr)).addReg(STReg); 869} 870 871/// adjustLiveRegs - Kill and revive registers such that exactly the FP 872/// registers with a bit in Mask are live. 873void FPS::adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I) { 874 unsigned Defs = Mask; 875 unsigned Kills = 0; 876 for (unsigned i = 0; i < StackTop; ++i) { 877 unsigned RegNo = Stack[i]; 878 if (!(Defs & (1 << RegNo))) 879 // This register is live, but we don't want it. 880 Kills |= (1 << RegNo); 881 else 882 // We don't need to imp-def this live register. 883 Defs &= ~(1 << RegNo); 884 } 885 assert((Kills & Defs) == 0 && "Register needs killing and def'ing?"); 886 887 // Produce implicit-defs for free by using killed registers. 888 while (Kills && Defs) { 889 unsigned KReg = CountTrailingZeros_32(Kills); 890 unsigned DReg = CountTrailingZeros_32(Defs); 891 DEBUG(dbgs() << "Renaming %FP" << KReg << " as imp %FP" << DReg << "\n"); 892 std::swap(Stack[getSlot(KReg)], Stack[getSlot(DReg)]); 893 std::swap(RegMap[KReg], RegMap[DReg]); 894 Kills &= ~(1 << KReg); 895 Defs &= ~(1 << DReg); 896 } 897 898 // Kill registers by popping. 899 if (Kills && I != MBB->begin()) { 900 MachineBasicBlock::iterator I2 = llvm::prior(I); 901 for (;;) { 902 unsigned KReg = getStackEntry(0); 903 if (!(Kills & (1 << KReg))) 904 break; 905 DEBUG(dbgs() << "Popping %FP" << KReg << "\n"); 906 popStackAfter(I2); 907 Kills &= ~(1 << KReg); 908 } 909 } 910 911 // Manually kill the rest. 912 while (Kills) { 913 unsigned KReg = CountTrailingZeros_32(Kills); 914 DEBUG(dbgs() << "Killing %FP" << KReg << "\n"); 915 freeStackSlotBefore(I, KReg); 916 Kills &= ~(1 << KReg); 917 } 918 919 // Load zeros for all the imp-defs. 920 while(Defs) { 921 unsigned DReg = CountTrailingZeros_32(Defs); 922 DEBUG(dbgs() << "Defining %FP" << DReg << " as 0\n"); 923 BuildMI(*MBB, I, DebugLoc(), TII->get(X86::LD_F0)); 924 pushReg(DReg); 925 Defs &= ~(1 << DReg); 926 } 927 928 // Now we should have the correct registers live. 929 DEBUG(dumpStack()); 930 assert(StackTop == CountPopulation_32(Mask) && "Live count mismatch"); 931} 932 933/// shuffleStackTop - emit fxch instructions before I to shuffle the top 934/// FixCount entries into the order given by FixStack. 935/// FIXME: Is there a better algorithm than insertion sort? 936void FPS::shuffleStackTop(const unsigned char *FixStack, 937 unsigned FixCount, 938 MachineBasicBlock::iterator I) { 939 // Move items into place, starting from the desired stack bottom. 940 while (FixCount--) { 941 // Old register at position FixCount. 942 unsigned OldReg = getStackEntry(FixCount); 943 // Desired register at position FixCount. 944 unsigned Reg = FixStack[FixCount]; 945 if (Reg == OldReg) 946 continue; 947 // (Reg st0) (OldReg st0) = (Reg OldReg st0) 948 moveToTop(Reg, I); 949 moveToTop(OldReg, I); 950 } 951 DEBUG(dumpStack()); 952} 953 954 955//===----------------------------------------------------------------------===// 956// Instruction transformation implementation 957//===----------------------------------------------------------------------===// 958 959/// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem> 960/// 961void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) { 962 MachineInstr *MI = I; 963 unsigned DestReg = getFPReg(MI->getOperand(0)); 964 965 // Change from the pseudo instruction to the concrete instruction. 966 MI->RemoveOperand(0); // Remove the explicit ST(0) operand 967 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode()))); 968 969 // Result gets pushed on the stack. 970 pushReg(DestReg); 971} 972 973/// handleOneArgFP - fst <mem>, ST(0) 974/// 975void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) { 976 MachineInstr *MI = I; 977 unsigned NumOps = MI->getDesc().getNumOperands(); 978 assert((NumOps == X86::AddrNumOperands + 1 || NumOps == 1) && 979 "Can only handle fst* & ftst instructions!"); 980 981 // Is this the last use of the source register? 982 unsigned Reg = getFPReg(MI->getOperand(NumOps-1)); 983 bool KillsSrc = MI->killsRegister(X86::FP0+Reg); 984 985 // FISTP64m is strange because there isn't a non-popping versions. 986 // If we have one _and_ we don't want to pop the operand, duplicate the value 987 // on the stack instead of moving it. This ensure that popping the value is 988 // always ok. 989 // Ditto FISTTP16m, FISTTP32m, FISTTP64m, ST_FpP80m. 990 // 991 if (!KillsSrc && 992 (MI->getOpcode() == X86::IST_Fp64m32 || 993 MI->getOpcode() == X86::ISTT_Fp16m32 || 994 MI->getOpcode() == X86::ISTT_Fp32m32 || 995 MI->getOpcode() == X86::ISTT_Fp64m32 || 996 MI->getOpcode() == X86::IST_Fp64m64 || 997 MI->getOpcode() == X86::ISTT_Fp16m64 || 998 MI->getOpcode() == X86::ISTT_Fp32m64 || 999 MI->getOpcode() == X86::ISTT_Fp64m64 || 1000 MI->getOpcode() == X86::IST_Fp64m80 || 1001 MI->getOpcode() == X86::ISTT_Fp16m80 || 1002 MI->getOpcode() == X86::ISTT_Fp32m80 || 1003 MI->getOpcode() == X86::ISTT_Fp64m80 || 1004 MI->getOpcode() == X86::ST_FpP80m)) { 1005 duplicateToTop(Reg, getScratchReg(), I); 1006 } else { 1007 moveToTop(Reg, I); // Move to the top of the stack... 1008 } 1009 1010 // Convert from the pseudo instruction to the concrete instruction. 1011 MI->RemoveOperand(NumOps-1); // Remove explicit ST(0) operand 1012 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode()))); 1013 1014 if (MI->getOpcode() == X86::IST_FP64m || 1015 MI->getOpcode() == X86::ISTT_FP16m || 1016 MI->getOpcode() == X86::ISTT_FP32m || 1017 MI->getOpcode() == X86::ISTT_FP64m || 1018 MI->getOpcode() == X86::ST_FP80m) { 1019 assert(StackTop > 0 && "Stack empty??"); 1020 --StackTop; 1021 } else if (KillsSrc) { // Last use of operand? 1022 popStackAfter(I); 1023 } 1024} 1025 1026 1027/// handleOneArgFPRW: Handle instructions that read from the top of stack and 1028/// replace the value with a newly computed value. These instructions may have 1029/// non-fp operands after their FP operands. 1030/// 1031/// Examples: 1032/// R1 = fchs R2 1033/// R1 = fadd R2, [mem] 1034/// 1035void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) { 1036 MachineInstr *MI = I; 1037#ifndef NDEBUG 1038 unsigned NumOps = MI->getDesc().getNumOperands(); 1039 assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!"); 1040#endif 1041 1042 // Is this the last use of the source register? 1043 unsigned Reg = getFPReg(MI->getOperand(1)); 1044 bool KillsSrc = MI->killsRegister(X86::FP0+Reg); 1045 1046 if (KillsSrc) { 1047 // If this is the last use of the source register, just make sure it's on 1048 // the top of the stack. 1049 moveToTop(Reg, I); 1050 assert(StackTop > 0 && "Stack cannot be empty!"); 1051 --StackTop; 1052 pushReg(getFPReg(MI->getOperand(0))); 1053 } else { 1054 // If this is not the last use of the source register, _copy_ it to the top 1055 // of the stack. 1056 duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I); 1057 } 1058 1059 // Change from the pseudo instruction to the concrete instruction. 1060 MI->RemoveOperand(1); // Drop the source operand. 1061 MI->RemoveOperand(0); // Drop the destination operand. 1062 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode()))); 1063} 1064 1065 1066//===----------------------------------------------------------------------===// 1067// Define tables of various ways to map pseudo instructions 1068// 1069 1070// ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i) 1071static const TableEntry ForwardST0Table[] = { 1072 { X86::ADD_Fp32 , X86::ADD_FST0r }, 1073 { X86::ADD_Fp64 , X86::ADD_FST0r }, 1074 { X86::ADD_Fp80 , X86::ADD_FST0r }, 1075 { X86::DIV_Fp32 , X86::DIV_FST0r }, 1076 { X86::DIV_Fp64 , X86::DIV_FST0r }, 1077 { X86::DIV_Fp80 , X86::DIV_FST0r }, 1078 { X86::MUL_Fp32 , X86::MUL_FST0r }, 1079 { X86::MUL_Fp64 , X86::MUL_FST0r }, 1080 { X86::MUL_Fp80 , X86::MUL_FST0r }, 1081 { X86::SUB_Fp32 , X86::SUB_FST0r }, 1082 { X86::SUB_Fp64 , X86::SUB_FST0r }, 1083 { X86::SUB_Fp80 , X86::SUB_FST0r }, 1084}; 1085 1086// ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0) 1087static const TableEntry ReverseST0Table[] = { 1088 { X86::ADD_Fp32 , X86::ADD_FST0r }, // commutative 1089 { X86::ADD_Fp64 , X86::ADD_FST0r }, // commutative 1090 { X86::ADD_Fp80 , X86::ADD_FST0r }, // commutative 1091 { X86::DIV_Fp32 , X86::DIVR_FST0r }, 1092 { X86::DIV_Fp64 , X86::DIVR_FST0r }, 1093 { X86::DIV_Fp80 , X86::DIVR_FST0r }, 1094 { X86::MUL_Fp32 , X86::MUL_FST0r }, // commutative 1095 { X86::MUL_Fp64 , X86::MUL_FST0r }, // commutative 1096 { X86::MUL_Fp80 , X86::MUL_FST0r }, // commutative 1097 { X86::SUB_Fp32 , X86::SUBR_FST0r }, 1098 { X86::SUB_Fp64 , X86::SUBR_FST0r }, 1099 { X86::SUB_Fp80 , X86::SUBR_FST0r }, 1100}; 1101 1102// ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i) 1103static const TableEntry ForwardSTiTable[] = { 1104 { X86::ADD_Fp32 , X86::ADD_FrST0 }, // commutative 1105 { X86::ADD_Fp64 , X86::ADD_FrST0 }, // commutative 1106 { X86::ADD_Fp80 , X86::ADD_FrST0 }, // commutative 1107 { X86::DIV_Fp32 , X86::DIVR_FrST0 }, 1108 { X86::DIV_Fp64 , X86::DIVR_FrST0 }, 1109 { X86::DIV_Fp80 , X86::DIVR_FrST0 }, 1110 { X86::MUL_Fp32 , X86::MUL_FrST0 }, // commutative 1111 { X86::MUL_Fp64 , X86::MUL_FrST0 }, // commutative 1112 { X86::MUL_Fp80 , X86::MUL_FrST0 }, // commutative 1113 { X86::SUB_Fp32 , X86::SUBR_FrST0 }, 1114 { X86::SUB_Fp64 , X86::SUBR_FrST0 }, 1115 { X86::SUB_Fp80 , X86::SUBR_FrST0 }, 1116}; 1117 1118// ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0) 1119static const TableEntry ReverseSTiTable[] = { 1120 { X86::ADD_Fp32 , X86::ADD_FrST0 }, 1121 { X86::ADD_Fp64 , X86::ADD_FrST0 }, 1122 { X86::ADD_Fp80 , X86::ADD_FrST0 }, 1123 { X86::DIV_Fp32 , X86::DIV_FrST0 }, 1124 { X86::DIV_Fp64 , X86::DIV_FrST0 }, 1125 { X86::DIV_Fp80 , X86::DIV_FrST0 }, 1126 { X86::MUL_Fp32 , X86::MUL_FrST0 }, 1127 { X86::MUL_Fp64 , X86::MUL_FrST0 }, 1128 { X86::MUL_Fp80 , X86::MUL_FrST0 }, 1129 { X86::SUB_Fp32 , X86::SUB_FrST0 }, 1130 { X86::SUB_Fp64 , X86::SUB_FrST0 }, 1131 { X86::SUB_Fp80 , X86::SUB_FrST0 }, 1132}; 1133 1134 1135/// handleTwoArgFP - Handle instructions like FADD and friends which are virtual 1136/// instructions which need to be simplified and possibly transformed. 1137/// 1138/// Result: ST(0) = fsub ST(0), ST(i) 1139/// ST(i) = fsub ST(0), ST(i) 1140/// ST(0) = fsubr ST(0), ST(i) 1141/// ST(i) = fsubr ST(0), ST(i) 1142/// 1143void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) { 1144 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table); 1145 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable); 1146 MachineInstr *MI = I; 1147 1148 unsigned NumOperands = MI->getDesc().getNumOperands(); 1149 assert(NumOperands == 3 && "Illegal TwoArgFP instruction!"); 1150 unsigned Dest = getFPReg(MI->getOperand(0)); 1151 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2)); 1152 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1)); 1153 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0); 1154 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1); 1155 DebugLoc dl = MI->getDebugLoc(); 1156 1157 unsigned TOS = getStackEntry(0); 1158 1159 // One of our operands must be on the top of the stack. If neither is yet, we 1160 // need to move one. 1161 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS? 1162 // We can choose to move either operand to the top of the stack. If one of 1163 // the operands is killed by this instruction, we want that one so that we 1164 // can update right on top of the old version. 1165 if (KillsOp0) { 1166 moveToTop(Op0, I); // Move dead operand to TOS. 1167 TOS = Op0; 1168 } else if (KillsOp1) { 1169 moveToTop(Op1, I); 1170 TOS = Op1; 1171 } else { 1172 // All of the operands are live after this instruction executes, so we 1173 // cannot update on top of any operand. Because of this, we must 1174 // duplicate one of the stack elements to the top. It doesn't matter 1175 // which one we pick. 1176 // 1177 duplicateToTop(Op0, Dest, I); 1178 Op0 = TOS = Dest; 1179 KillsOp0 = true; 1180 } 1181 } else if (!KillsOp0 && !KillsOp1) { 1182 // If we DO have one of our operands at the top of the stack, but we don't 1183 // have a dead operand, we must duplicate one of the operands to a new slot 1184 // on the stack. 1185 duplicateToTop(Op0, Dest, I); 1186 Op0 = TOS = Dest; 1187 KillsOp0 = true; 1188 } 1189 1190 // Now we know that one of our operands is on the top of the stack, and at 1191 // least one of our operands is killed by this instruction. 1192 assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) && 1193 "Stack conditions not set up right!"); 1194 1195 // We decide which form to use based on what is on the top of the stack, and 1196 // which operand is killed by this instruction. 1197 const TableEntry *InstTable; 1198 bool isForward = TOS == Op0; 1199 bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0); 1200 if (updateST0) { 1201 if (isForward) 1202 InstTable = ForwardST0Table; 1203 else 1204 InstTable = ReverseST0Table; 1205 } else { 1206 if (isForward) 1207 InstTable = ForwardSTiTable; 1208 else 1209 InstTable = ReverseSTiTable; 1210 } 1211 1212 int Opcode = Lookup(InstTable, array_lengthof(ForwardST0Table), 1213 MI->getOpcode()); 1214 assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!"); 1215 1216 // NotTOS - The register which is not on the top of stack... 1217 unsigned NotTOS = (TOS == Op0) ? Op1 : Op0; 1218 1219 // Replace the old instruction with a new instruction 1220 MBB->remove(I++); 1221 I = BuildMI(*MBB, I, dl, TII->get(Opcode)).addReg(getSTReg(NotTOS)); 1222 1223 // If both operands are killed, pop one off of the stack in addition to 1224 // overwriting the other one. 1225 if (KillsOp0 && KillsOp1 && Op0 != Op1) { 1226 assert(!updateST0 && "Should have updated other operand!"); 1227 popStackAfter(I); // Pop the top of stack 1228 } 1229 1230 // Update stack information so that we know the destination register is now on 1231 // the stack. 1232 unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS); 1233 assert(UpdatedSlot < StackTop && Dest < 7); 1234 Stack[UpdatedSlot] = Dest; 1235 RegMap[Dest] = UpdatedSlot; 1236 MBB->getParent()->DeleteMachineInstr(MI); // Remove the old instruction 1237} 1238 1239/// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP 1240/// register arguments and no explicit destinations. 1241/// 1242void FPS::handleCompareFP(MachineBasicBlock::iterator &I) { 1243 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table); 1244 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable); 1245 MachineInstr *MI = I; 1246 1247 unsigned NumOperands = MI->getDesc().getNumOperands(); 1248 assert(NumOperands == 2 && "Illegal FUCOM* instruction!"); 1249 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2)); 1250 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1)); 1251 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0); 1252 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1); 1253 1254 // Make sure the first operand is on the top of stack, the other one can be 1255 // anywhere. 1256 moveToTop(Op0, I); 1257 1258 // Change from the pseudo instruction to the concrete instruction. 1259 MI->getOperand(0).setReg(getSTReg(Op1)); 1260 MI->RemoveOperand(1); 1261 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode()))); 1262 1263 // If any of the operands are killed by this instruction, free them. 1264 if (KillsOp0) freeStackSlotAfter(I, Op0); 1265 if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1); 1266} 1267 1268/// handleCondMovFP - Handle two address conditional move instructions. These 1269/// instructions move a st(i) register to st(0) iff a condition is true. These 1270/// instructions require that the first operand is at the top of the stack, but 1271/// otherwise don't modify the stack at all. 1272void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) { 1273 MachineInstr *MI = I; 1274 1275 unsigned Op0 = getFPReg(MI->getOperand(0)); 1276 unsigned Op1 = getFPReg(MI->getOperand(2)); 1277 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1); 1278 1279 // The first operand *must* be on the top of the stack. 1280 moveToTop(Op0, I); 1281 1282 // Change the second operand to the stack register that the operand is in. 1283 // Change from the pseudo instruction to the concrete instruction. 1284 MI->RemoveOperand(0); 1285 MI->RemoveOperand(1); 1286 MI->getOperand(0).setReg(getSTReg(Op1)); 1287 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode()))); 1288 1289 // If we kill the second operand, make sure to pop it from the stack. 1290 if (Op0 != Op1 && KillsOp1) { 1291 // Get this value off of the register stack. 1292 freeStackSlotAfter(I, Op1); 1293 } 1294} 1295 1296 1297/// handleSpecialFP - Handle special instructions which behave unlike other 1298/// floating point instructions. This is primarily intended for use by pseudo 1299/// instructions. 1300/// 1301void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) { 1302 MachineInstr *MI = I; 1303 DebugLoc dl = MI->getDebugLoc(); 1304 switch (MI->getOpcode()) { 1305 default: llvm_unreachable("Unknown SpecialFP instruction!"); 1306 case X86::FpGET_ST0_32:// Appears immediately after a call returning FP type! 1307 case X86::FpGET_ST0_64:// Appears immediately after a call returning FP type! 1308 case X86::FpGET_ST0_80:// Appears immediately after a call returning FP type! 1309 assert(StackTop == 0 && "Stack should be empty after a call!"); 1310 pushReg(getFPReg(MI->getOperand(0))); 1311 break; 1312 case X86::FpGET_ST1_32:// Appears immediately after a call returning FP type! 1313 case X86::FpGET_ST1_64:// Appears immediately after a call returning FP type! 1314 case X86::FpGET_ST1_80:{// Appears immediately after a call returning FP type! 1315 // FpGET_ST1 should occur right after a FpGET_ST0 for a call or inline asm. 1316 // The pattern we expect is: 1317 // CALL 1318 // FP1 = FpGET_ST0 1319 // FP4 = FpGET_ST1 1320 // 1321 // At this point, we've pushed FP1 on the top of stack, so it should be 1322 // present if it isn't dead. If it was dead, we already emitted a pop to 1323 // remove it from the stack and StackTop = 0. 1324 1325 // Push FP4 as top of stack next. 1326 pushReg(getFPReg(MI->getOperand(0))); 1327 1328 // If StackTop was 0 before we pushed our operand, then ST(0) must have been 1329 // dead. In this case, the ST(1) value is the only thing that is live, so 1330 // it should be on the TOS (after the pop that was emitted) and is. Just 1331 // continue in this case. 1332 if (StackTop == 1) 1333 break; 1334 1335 // Because pushReg just pushed ST(1) as TOS, we now have to swap the two top 1336 // elements so that our accounting is correct. 1337 unsigned RegOnTop = getStackEntry(0); 1338 unsigned RegNo = getStackEntry(1); 1339 1340 // Swap the slots the regs are in. 1341 std::swap(RegMap[RegNo], RegMap[RegOnTop]); 1342 1343 // Swap stack slot contents. 1344 assert(RegMap[RegOnTop] < StackTop); 1345 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]); 1346 break; 1347 } 1348 case X86::FpSET_ST0_32: 1349 case X86::FpSET_ST0_64: 1350 case X86::FpSET_ST0_80: { 1351 // FpSET_ST0_80 is generated by copyRegToReg for setting up inline asm 1352 // arguments that use an st constraint. We expect a sequence of 1353 // instructions: Fp_SET_ST0 Fp_SET_ST1? INLINEASM 1354 unsigned Op0 = getFPReg(MI->getOperand(0)); 1355 1356 if (!MI->killsRegister(X86::FP0 + Op0)) { 1357 // Duplicate Op0 into a temporary on the stack top. 1358 duplicateToTop(Op0, getScratchReg(), I); 1359 } else { 1360 // Op0 is killed, so just swap it into position. 1361 moveToTop(Op0, I); 1362 } 1363 --StackTop; // "Forget" we have something on the top of stack! 1364 break; 1365 } 1366 case X86::FpSET_ST1_32: 1367 case X86::FpSET_ST1_64: 1368 case X86::FpSET_ST1_80: { 1369 // Set up st(1) for inline asm. We are assuming that st(0) has already been 1370 // set up by FpSET_ST0, and our StackTop is off by one because of it. 1371 unsigned Op0 = getFPReg(MI->getOperand(0)); 1372 // Restore the actual StackTop from before Fp_SET_ST0. 1373 // Note we can't handle Fp_SET_ST1 without a preceeding Fp_SET_ST0, and we 1374 // are not enforcing the constraint. 1375 ++StackTop; 1376 unsigned RegOnTop = getStackEntry(0); // This reg must remain in st(0). 1377 if (!MI->killsRegister(X86::FP0 + Op0)) { 1378 duplicateToTop(Op0, getScratchReg(), I); 1379 moveToTop(RegOnTop, I); 1380 } else if (getSTReg(Op0) != X86::ST1) { 1381 // We have the wrong value at st(1). Shuffle! Untested! 1382 moveToTop(getStackEntry(1), I); 1383 moveToTop(Op0, I); 1384 moveToTop(RegOnTop, I); 1385 } 1386 assert(StackTop >= 2 && "Too few live registers"); 1387 StackTop -= 2; // "Forget" both st(0) and st(1). 1388 break; 1389 } 1390 case X86::MOV_Fp3232: 1391 case X86::MOV_Fp3264: 1392 case X86::MOV_Fp6432: 1393 case X86::MOV_Fp6464: 1394 case X86::MOV_Fp3280: 1395 case X86::MOV_Fp6480: 1396 case X86::MOV_Fp8032: 1397 case X86::MOV_Fp8064: 1398 case X86::MOV_Fp8080: { 1399 const MachineOperand &MO1 = MI->getOperand(1); 1400 unsigned SrcReg = getFPReg(MO1); 1401 1402 const MachineOperand &MO0 = MI->getOperand(0); 1403 unsigned DestReg = getFPReg(MO0); 1404 if (MI->killsRegister(X86::FP0+SrcReg)) { 1405 // If the input operand is killed, we can just change the owner of the 1406 // incoming stack slot into the result. 1407 unsigned Slot = getSlot(SrcReg); 1408 assert(Slot < 7 && DestReg < 7 && "FpMOV operands invalid!"); 1409 Stack[Slot] = DestReg; 1410 RegMap[DestReg] = Slot; 1411 1412 } else { 1413 // For FMOV we just duplicate the specified value to a new stack slot. 1414 // This could be made better, but would require substantial changes. 1415 duplicateToTop(SrcReg, DestReg, I); 1416 } 1417 } 1418 break; 1419 case TargetOpcode::INLINEASM: { 1420 // The inline asm MachineInstr currently only *uses* FP registers for the 1421 // 'f' constraint. These should be turned into the current ST(x) register 1422 // in the machine instr. Also, any kills should be explicitly popped after 1423 // the inline asm. 1424 unsigned Kills = 0; 1425 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1426 MachineOperand &Op = MI->getOperand(i); 1427 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6) 1428 continue; 1429 assert(Op.isUse() && "Only handle inline asm uses right now"); 1430 1431 unsigned FPReg = getFPReg(Op); 1432 Op.setReg(getSTReg(FPReg)); 1433 1434 // If we kill this operand, make sure to pop it from the stack after the 1435 // asm. We just remember it for now, and pop them all off at the end in 1436 // a batch. 1437 if (Op.isKill()) 1438 Kills |= 1U << FPReg; 1439 } 1440 1441 // If this asm kills any FP registers (is the last use of them) we must 1442 // explicitly emit pop instructions for them. Do this now after the asm has 1443 // executed so that the ST(x) numbers are not off (which would happen if we 1444 // did this inline with operand rewriting). 1445 // 1446 // Note: this might be a non-optimal pop sequence. We might be able to do 1447 // better by trying to pop in stack order or something. 1448 MachineBasicBlock::iterator InsertPt = MI; 1449 while (Kills) { 1450 unsigned FPReg = CountTrailingZeros_32(Kills); 1451 freeStackSlotAfter(InsertPt, FPReg); 1452 Kills &= ~(1U << FPReg); 1453 } 1454 // Don't delete the inline asm! 1455 return; 1456 } 1457 1458 case X86::RET: 1459 case X86::RETI: 1460 // If RET has an FP register use operand, pass the first one in ST(0) and 1461 // the second one in ST(1). 1462 1463 // Find the register operands. 1464 unsigned FirstFPRegOp = ~0U, SecondFPRegOp = ~0U; 1465 unsigned LiveMask = 0; 1466 1467 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1468 MachineOperand &Op = MI->getOperand(i); 1469 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6) 1470 continue; 1471 // FP Register uses must be kills unless there are two uses of the same 1472 // register, in which case only one will be a kill. 1473 assert(Op.isUse() && 1474 (Op.isKill() || // Marked kill. 1475 getFPReg(Op) == FirstFPRegOp || // Second instance. 1476 MI->killsRegister(Op.getReg())) && // Later use is marked kill. 1477 "Ret only defs operands, and values aren't live beyond it"); 1478 1479 if (FirstFPRegOp == ~0U) 1480 FirstFPRegOp = getFPReg(Op); 1481 else { 1482 assert(SecondFPRegOp == ~0U && "More than two fp operands!"); 1483 SecondFPRegOp = getFPReg(Op); 1484 } 1485 LiveMask |= (1 << getFPReg(Op)); 1486 1487 // Remove the operand so that later passes don't see it. 1488 MI->RemoveOperand(i); 1489 --i, --e; 1490 } 1491 1492 // We may have been carrying spurious live-ins, so make sure only the returned 1493 // registers are left live. 1494 adjustLiveRegs(LiveMask, MI); 1495 if (!LiveMask) return; // Quick check to see if any are possible. 1496 1497 // There are only four possibilities here: 1498 // 1) we are returning a single FP value. In this case, it has to be in 1499 // ST(0) already, so just declare success by removing the value from the 1500 // FP Stack. 1501 if (SecondFPRegOp == ~0U) { 1502 // Assert that the top of stack contains the right FP register. 1503 assert(StackTop == 1 && FirstFPRegOp == getStackEntry(0) && 1504 "Top of stack not the right register for RET!"); 1505 1506 // Ok, everything is good, mark the value as not being on the stack 1507 // anymore so that our assertion about the stack being empty at end of 1508 // block doesn't fire. 1509 StackTop = 0; 1510 return; 1511 } 1512 1513 // Otherwise, we are returning two values: 1514 // 2) If returning the same value for both, we only have one thing in the FP 1515 // stack. Consider: RET FP1, FP1 1516 if (StackTop == 1) { 1517 assert(FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry(0)&& 1518 "Stack misconfiguration for RET!"); 1519 1520 // Duplicate the TOS so that we return it twice. Just pick some other FPx 1521 // register to hold it. 1522 unsigned NewReg = getScratchReg(); 1523 duplicateToTop(FirstFPRegOp, NewReg, MI); 1524 FirstFPRegOp = NewReg; 1525 } 1526 1527 /// Okay we know we have two different FPx operands now: 1528 assert(StackTop == 2 && "Must have two values live!"); 1529 1530 /// 3) If SecondFPRegOp is currently in ST(0) and FirstFPRegOp is currently 1531 /// in ST(1). In this case, emit an fxch. 1532 if (getStackEntry(0) == SecondFPRegOp) { 1533 assert(getStackEntry(1) == FirstFPRegOp && "Unknown regs live"); 1534 moveToTop(FirstFPRegOp, MI); 1535 } 1536 1537 /// 4) Finally, FirstFPRegOp must be in ST(0) and SecondFPRegOp must be in 1538 /// ST(1). Just remove both from our understanding of the stack and return. 1539 assert(getStackEntry(0) == FirstFPRegOp && "Unknown regs live"); 1540 assert(getStackEntry(1) == SecondFPRegOp && "Unknown regs live"); 1541 StackTop = 0; 1542 return; 1543 } 1544 1545 I = MBB->erase(I); // Remove the pseudo instruction 1546 1547 // We want to leave I pointing to the previous instruction, but what if we 1548 // just erased the first instruction? 1549 if (I == MBB->begin()) { 1550 DEBUG(dbgs() << "Inserting dummy KILL\n"); 1551 I = BuildMI(*MBB, I, DebugLoc(), TII->get(TargetOpcode::KILL)); 1552 } else 1553 --I; 1554} 1555 1556// Translate a COPY instruction to a pseudo-op that handleSpecialFP understands. 1557bool FPS::translateCopy(MachineInstr *MI) { 1558 unsigned DstReg = MI->getOperand(0).getReg(); 1559 unsigned SrcReg = MI->getOperand(1).getReg(); 1560 1561 if (DstReg == X86::ST0) { 1562 MI->setDesc(TII->get(X86::FpSET_ST0_80)); 1563 MI->RemoveOperand(0); 1564 return true; 1565 } 1566 if (DstReg == X86::ST1) { 1567 MI->setDesc(TII->get(X86::FpSET_ST1_80)); 1568 MI->RemoveOperand(0); 1569 return true; 1570 } 1571 if (SrcReg == X86::ST0) { 1572 MI->setDesc(TII->get(X86::FpGET_ST0_80)); 1573 return true; 1574 } 1575 if (SrcReg == X86::ST1) { 1576 MI->setDesc(TII->get(X86::FpGET_ST1_80)); 1577 return true; 1578 } 1579 if (X86::RFP80RegClass.contains(DstReg, SrcReg)) { 1580 MI->setDesc(TII->get(X86::MOV_Fp8080)); 1581 return true; 1582 } 1583 return false; 1584} 1585