X86FloatingPoint.cpp revision 88835735f49c3fce20698a72898df83bd84bd1cd 
1//===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the pass which converts floating point instructions from
11// virtual registers into register stack instructions.  This pass uses live
12// variable information to indicate where the FPn registers are used and their
13// lifetimes.
14//
15// This pass is hampered by the lack of decent CFG manipulation routines for
16// machine code.  In particular, this wants to be able to split critical edges
17// as necessary, traverse the machine basic block CFG in depth-first order, and
18// allow there to be multiple machine basic blocks for each LLVM basicblock
19// (needed for critical edge splitting).
20//
21// In particular, this pass currently barfs on critical edges.  Because of this,
22// it requires the instruction selector to insert FP_REG_KILL instructions on
23// the exits of any basic block that has critical edges going from it, or which
24// branch to a critical basic block.
25//
26// FIXME: this is not implemented yet.  The stackifier pass only works on local
27// basic blocks.
28//
29//===----------------------------------------------------------------------===//
30
31#define DEBUG_TYPE "x86-codegen"
32#include "X86.h"
33#include "X86InstrInfo.h"
34#include "llvm/CodeGen/MachineFunctionPass.h"
35#include "llvm/CodeGen/MachineInstrBuilder.h"
36#include "llvm/CodeGen/LiveVariables.h"
37#include "llvm/CodeGen/Passes.h"
38#include "llvm/Target/TargetInstrInfo.h"
39#include "llvm/Target/TargetMachine.h"
40#include "llvm/Support/Debug.h"
41#include "llvm/Support/Compiler.h"
42#include "llvm/ADT/DepthFirstIterator.h"
43#include "llvm/ADT/SmallVector.h"
44#include "llvm/ADT/Statistic.h"
45#include "llvm/ADT/STLExtras.h"
46#include <algorithm>
47#include <set>
48using namespace llvm;
49
50STATISTIC(NumFXCH, "Number of fxch instructions inserted");
51STATISTIC(NumFP  , "Number of floating point instructions");
52
53namespace {
54  struct VISIBILITY_HIDDEN FPS : public MachineFunctionPass {
55    static char ID;
56    FPS() : MachineFunctionPass((intptr_t)&ID) {}
57
58    virtual bool runOnMachineFunction(MachineFunction &MF);
59
60    virtual const char *getPassName() const { return "X86 FP Stackifier"; }
61
62    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
63      AU.addRequired<LiveVariables>();
64      MachineFunctionPass::getAnalysisUsage(AU);
65    }
66  private:
67    const TargetInstrInfo *TII; // Machine instruction info.
68    LiveVariables     *LV;      // Live variable info for current function...
69    MachineBasicBlock *MBB;     // Current basic block
70    unsigned Stack[8];          // FP<n> Registers in each stack slot...
71    unsigned RegMap[8];         // Track which stack slot contains each register
72    unsigned StackTop;          // The current top of the FP stack.
73
74    void dumpStack() const {
75      cerr << "Stack contents:";
76      for (unsigned i = 0; i != StackTop; ++i) {
77        cerr << " FP" << Stack[i];
78        assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
79      }
80      cerr << "\n";
81    }
82  private:
83    // getSlot - Return the stack slot number a particular register number is
84    // in...
85    unsigned getSlot(unsigned RegNo) const {
86      assert(RegNo < 8 && "Regno out of range!");
87      return RegMap[RegNo];
88    }
89
90    // getStackEntry - Return the X86::FP<n> register in register ST(i)
91    unsigned getStackEntry(unsigned STi) const {
92      assert(STi < StackTop && "Access past stack top!");
93      return Stack[StackTop-1-STi];
94    }
95
96    // getSTReg - Return the X86::ST(i) register which contains the specified
97    // FP<RegNo> register
98    unsigned getSTReg(unsigned RegNo) const {
99      return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0;
100    }
101
102    // pushReg - Push the specified FP<n> register onto the stack
103    void pushReg(unsigned Reg) {
104      assert(Reg < 8 && "Register number out of range!");
105      assert(StackTop < 8 && "Stack overflow!");
106      Stack[StackTop] = Reg;
107      RegMap[Reg] = StackTop++;
108    }
109
110    bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
111    void moveToTop(unsigned RegNo, MachineBasicBlock::iterator &I) {
112      if (!isAtTop(RegNo)) {
113        unsigned STReg = getSTReg(RegNo);
114        unsigned RegOnTop = getStackEntry(0);
115
116        // Swap the slots the regs are in
117        std::swap(RegMap[RegNo], RegMap[RegOnTop]);
118
119        // Swap stack slot contents
120        assert(RegMap[RegOnTop] < StackTop);
121        std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
122
123        // Emit an fxch to update the runtime processors version of the state
124        BuildMI(*MBB, I, TII->get(X86::XCH_F)).addReg(STReg);
125        NumFXCH++;
126      }
127    }
128
129    void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) {
130      unsigned STReg = getSTReg(RegNo);
131      pushReg(AsReg);   // New register on top of stack
132
133      BuildMI(*MBB, I, TII->get(X86::LD_Frr)).addReg(STReg);
134    }
135
136    // popStackAfter - Pop the current value off of the top of the FP stack
137    // after the specified instruction.
138    void popStackAfter(MachineBasicBlock::iterator &I);
139
140    // freeStackSlotAfter - Free the specified register from the register stack,
141    // so that it is no longer in a register.  If the register is currently at
142    // the top of the stack, we just pop the current instruction, otherwise we
143    // store the current top-of-stack into the specified slot, then pop the top
144    // of stack.
145    void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
146
147    bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
148
149    void handleZeroArgFP(MachineBasicBlock::iterator &I);
150    void handleOneArgFP(MachineBasicBlock::iterator &I);
151    void handleOneArgFPRW(MachineBasicBlock::iterator &I);
152    void handleTwoArgFP(MachineBasicBlock::iterator &I);
153    void handleCompareFP(MachineBasicBlock::iterator &I);
154    void handleCondMovFP(MachineBasicBlock::iterator &I);
155    void handleSpecialFP(MachineBasicBlock::iterator &I);
156  };
157  char FPS::ID = 0;
158}
159
160FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); }
161
162/// runOnMachineFunction - Loop over all of the basic blocks, transforming FP
163/// register references into FP stack references.
164///
165bool FPS::runOnMachineFunction(MachineFunction &MF) {
166  // We only need to run this pass if there are any FP registers used in this
167  // function.  If it is all integer, there is nothing for us to do!
168  bool FPIsUsed = false;
169
170  assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!");
171  for (unsigned i = 0; i <= 6; ++i)
172    if (MF.isPhysRegUsed(X86::FP0+i)) {
173      FPIsUsed = true;
174      break;
175    }
176
177  // Early exit.
178  if (!FPIsUsed) return false;
179
180  TII = MF.getTarget().getInstrInfo();
181  LV = &getAnalysis<LiveVariables>();
182  StackTop = 0;
183
184  // Process the function in depth first order so that we process at least one
185  // of the predecessors for every reachable block in the function.
186  std::set<MachineBasicBlock*> Processed;
187  MachineBasicBlock *Entry = MF.begin();
188
189  bool Changed = false;
190  for (df_ext_iterator<MachineBasicBlock*, std::set<MachineBasicBlock*> >
191         I = df_ext_begin(Entry, Processed), E = df_ext_end(Entry, Processed);
192       I != E; ++I)
193    Changed |= processBasicBlock(MF, **I);
194
195  return Changed;
196}
197
198/// processBasicBlock - Loop over all of the instructions in the basic block,
199/// transforming FP instructions into their stack form.
200///
201bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
202  bool Changed = false;
203  MBB = &BB;
204
205  for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
206    MachineInstr *MI = I;
207    unsigned Flags = MI->getInstrDescriptor()->TSFlags;
208    if ((Flags & X86II::FPTypeMask) == X86II::NotFP)
209      continue;  // Efficiently ignore non-fp insts!
210
211    MachineInstr *PrevMI = 0;
212    if (I != BB.begin())
213        PrevMI = prior(I);
214
215    ++NumFP;  // Keep track of # of pseudo instrs
216    DOUT << "\nFPInst:\t" << *MI;
217
218    // Get dead variables list now because the MI pointer may be deleted as part
219    // of processing!
220    SmallVector<unsigned, 8> DeadRegs;
221    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
222      const MachineOperand &MO = MI->getOperand(i);
223      if (MO.isReg() && MO.isDead())
224        DeadRegs.push_back(MO.getReg());
225    }
226
227    switch (Flags & X86II::FPTypeMask) {
228    case X86II::ZeroArgFP:  handleZeroArgFP(I); break;
229    case X86II::OneArgFP:   handleOneArgFP(I);  break;  // fstp ST(0)
230    case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0))
231    case X86II::TwoArgFP:   handleTwoArgFP(I);  break;
232    case X86II::CompareFP:  handleCompareFP(I); break;
233    case X86II::CondMovFP:  handleCondMovFP(I); break;
234    case X86II::SpecialFP:  handleSpecialFP(I); break;
235    default: assert(0 && "Unknown FP Type!");
236    }
237
238    // Check to see if any of the values defined by this instruction are dead
239    // after definition.  If so, pop them.
240    for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
241      unsigned Reg = DeadRegs[i];
242      if (Reg >= X86::FP0 && Reg <= X86::FP6) {
243        DOUT << "Register FP#" << Reg-X86::FP0 << " is dead!\n";
244        freeStackSlotAfter(I, Reg-X86::FP0);
245      }
246    }
247
248    // Print out all of the instructions expanded to if -debug
249    DEBUG(
250      MachineBasicBlock::iterator PrevI(PrevMI);
251      if (I == PrevI) {
252        cerr << "Just deleted pseudo instruction\n";
253      } else {
254        MachineBasicBlock::iterator Start = I;
255        // Rewind to first instruction newly inserted.
256        while (Start != BB.begin() && prior(Start) != PrevI) --Start;
257        cerr << "Inserted instructions:\n\t";
258        Start->print(*cerr.stream(), &MF.getTarget());
259        while (++Start != next(I));
260      }
261      dumpStack();
262    );
263
264    Changed = true;
265  }
266
267  assert(StackTop == 0 && "Stack not empty at end of basic block?");
268  return Changed;
269}
270
271//===----------------------------------------------------------------------===//
272// Efficient Lookup Table Support
273//===----------------------------------------------------------------------===//
274
275namespace {
276  struct TableEntry {
277    unsigned from;
278    unsigned to;
279    bool operator<(const TableEntry &TE) const { return from < TE.from; }
280    friend bool operator<(const TableEntry &TE, unsigned V) {
281      return TE.from < V;
282    }
283    friend bool operator<(unsigned V, const TableEntry &TE) {
284      return V < TE.from;
285    }
286  };
287}
288
289static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
290  for (unsigned i = 0; i != NumEntries-1; ++i)
291    if (!(Table[i] < Table[i+1])) return false;
292  return true;
293}
294
295static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) {
296  const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
297  if (I != Table+N && I->from == Opcode)
298    return I->to;
299  return -1;
300}
301
302#define ARRAY_SIZE(TABLE)  \
303   (sizeof(TABLE)/sizeof(TABLE[0]))
304
305#ifdef NDEBUG
306#define ASSERT_SORTED(TABLE)
307#else
308#define ASSERT_SORTED(TABLE)                                              \
309  { static bool TABLE##Checked = false;                                   \
310    if (!TABLE##Checked) {                                                \
311       assert(TableIsSorted(TABLE, ARRAY_SIZE(TABLE)) &&                  \
312              "All lookup tables must be sorted for efficient access!");  \
313       TABLE##Checked = true;                                             \
314    }                                                                     \
315  }
316#endif
317
318//===----------------------------------------------------------------------===//
319// Register File -> Register Stack Mapping Methods
320//===----------------------------------------------------------------------===//
321
322// OpcodeTable - Sorted map of register instructions to their stack version.
323// The first element is an register file pseudo instruction, the second is the
324// concrete X86 instruction which uses the register stack.
325//
326static const TableEntry OpcodeTable[] = {
327  { X86::ABS_Fp32     , X86::ABS_F     },
328  { X86::ABS_Fp64     , X86::ABS_F     },
329  { X86::ABS_Fp80     , X86::ABS_F     },
330  { X86::ADD_Fp32m    , X86::ADD_F32m  },
331  { X86::ADD_Fp64m    , X86::ADD_F64m  },
332  { X86::ADD_Fp64m32  , X86::ADD_F32m  },
333  { X86::ADD_Fp80m32  , X86::ADD_F32m  },
334  { X86::ADD_Fp80m64  , X86::ADD_F64m  },
335  { X86::ADD_FpI16m32 , X86::ADD_FI16m },
336  { X86::ADD_FpI16m64 , X86::ADD_FI16m },
337  { X86::ADD_FpI16m80 , X86::ADD_FI16m },
338  { X86::ADD_FpI32m32 , X86::ADD_FI32m },
339  { X86::ADD_FpI32m64 , X86::ADD_FI32m },
340  { X86::ADD_FpI32m80 , X86::ADD_FI32m },
341  { X86::CHS_Fp32     , X86::CHS_F     },
342  { X86::CHS_Fp64     , X86::CHS_F     },
343  { X86::CHS_Fp80     , X86::CHS_F     },
344  { X86::CMOVBE_Fp32  , X86::CMOVBE_F  },
345  { X86::CMOVBE_Fp64  , X86::CMOVBE_F  },
346  { X86::CMOVBE_Fp80  , X86::CMOVBE_F  },
347  { X86::CMOVB_Fp32   , X86::CMOVB_F   },
348  { X86::CMOVB_Fp64   , X86::CMOVB_F  },
349  { X86::CMOVB_Fp80   , X86::CMOVB_F  },
350  { X86::CMOVE_Fp32   , X86::CMOVE_F  },
351  { X86::CMOVE_Fp64   , X86::CMOVE_F   },
352  { X86::CMOVE_Fp80   , X86::CMOVE_F   },
353  { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F },
354  { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F },
355  { X86::CMOVNBE_Fp80 , X86::CMOVNBE_F },
356  { X86::CMOVNB_Fp32  , X86::CMOVNB_F  },
357  { X86::CMOVNB_Fp64  , X86::CMOVNB_F  },
358  { X86::CMOVNB_Fp80  , X86::CMOVNB_F  },
359  { X86::CMOVNE_Fp32  , X86::CMOVNE_F  },
360  { X86::CMOVNE_Fp64  , X86::CMOVNE_F  },
361  { X86::CMOVNE_Fp80  , X86::CMOVNE_F  },
362  { X86::CMOVNP_Fp32  , X86::CMOVNP_F  },
363  { X86::CMOVNP_Fp64  , X86::CMOVNP_F  },
364  { X86::CMOVNP_Fp80  , X86::CMOVNP_F  },
365  { X86::CMOVP_Fp32   , X86::CMOVP_F   },
366  { X86::CMOVP_Fp64   , X86::CMOVP_F   },
367  { X86::CMOVP_Fp80   , X86::CMOVP_F   },
368  { X86::COS_Fp32     , X86::COS_F     },
369  { X86::COS_Fp64     , X86::COS_F     },
370  { X86::COS_Fp80     , X86::COS_F     },
371  { X86::DIVR_Fp32m   , X86::DIVR_F32m },
372  { X86::DIVR_Fp64m   , X86::DIVR_F64m },
373  { X86::DIVR_Fp64m32 , X86::DIVR_F32m },
374  { X86::DIVR_Fp80m32 , X86::DIVR_F32m },
375  { X86::DIVR_Fp80m64 , X86::DIVR_F64m },
376  { X86::DIVR_FpI16m32, X86::DIVR_FI16m},
377  { X86::DIVR_FpI16m64, X86::DIVR_FI16m},
378  { X86::DIVR_FpI16m80, X86::DIVR_FI16m},
379  { X86::DIVR_FpI32m32, X86::DIVR_FI32m},
380  { X86::DIVR_FpI32m64, X86::DIVR_FI32m},
381  { X86::DIVR_FpI32m80, X86::DIVR_FI32m},
382  { X86::DIV_Fp32m    , X86::DIV_F32m  },
383  { X86::DIV_Fp64m    , X86::DIV_F64m  },
384  { X86::DIV_Fp64m32  , X86::DIV_F32m  },
385  { X86::DIV_Fp80m32  , X86::DIV_F32m  },
386  { X86::DIV_Fp80m64  , X86::DIV_F64m  },
387  { X86::DIV_FpI16m32 , X86::DIV_FI16m },
388  { X86::DIV_FpI16m64 , X86::DIV_FI16m },
389  { X86::DIV_FpI16m80 , X86::DIV_FI16m },
390  { X86::DIV_FpI32m32 , X86::DIV_FI32m },
391  { X86::DIV_FpI32m64 , X86::DIV_FI32m },
392  { X86::DIV_FpI32m80 , X86::DIV_FI32m },
393  { X86::ILD_Fp16m32  , X86::ILD_F16m  },
394  { X86::ILD_Fp16m64  , X86::ILD_F16m  },
395  { X86::ILD_Fp16m80  , X86::ILD_F16m  },
396  { X86::ILD_Fp32m32  , X86::ILD_F32m  },
397  { X86::ILD_Fp32m64  , X86::ILD_F32m  },
398  { X86::ILD_Fp32m80  , X86::ILD_F32m  },
399  { X86::ILD_Fp64m32  , X86::ILD_F64m  },
400  { X86::ILD_Fp64m64  , X86::ILD_F64m  },
401  { X86::ILD_Fp64m80  , X86::ILD_F64m  },
402  { X86::ISTT_Fp16m32 , X86::ISTT_FP16m},
403  { X86::ISTT_Fp16m64 , X86::ISTT_FP16m},
404  { X86::ISTT_Fp32m32 , X86::ISTT_FP32m},
405  { X86::ISTT_Fp32m64 , X86::ISTT_FP32m},
406  { X86::ISTT_Fp64m32 , X86::ISTT_FP64m},
407  { X86::ISTT_Fp64m64 , X86::ISTT_FP64m},
408  { X86::IST_Fp16m32  , X86::IST_F16m  },
409  { X86::IST_Fp16m64  , X86::IST_F16m  },
410  { X86::IST_Fp16m80  , X86::IST_F16m  },
411  { X86::IST_Fp32m32  , X86::IST_F32m  },
412  { X86::IST_Fp32m64  , X86::IST_F32m  },
413  { X86::IST_Fp32m80  , X86::IST_F32m  },
414  { X86::IST_Fp64m32  , X86::IST_FP64m },
415  { X86::IST_Fp64m64  , X86::IST_FP64m },
416  { X86::IST_Fp64m80  , X86::IST_FP64m },
417  { X86::LD_Fp032     , X86::LD_F0     },
418  { X86::LD_Fp064     , X86::LD_F0     },
419  { X86::LD_Fp080     , X86::LD_F0     },
420  { X86::LD_Fp132     , X86::LD_F1     },
421  { X86::LD_Fp164     , X86::LD_F1     },
422  { X86::LD_Fp180     , X86::LD_F1     },
423  { X86::LD_Fp32m     , X86::LD_F32m   },
424  { X86::LD_Fp64m     , X86::LD_F64m   },
425  { X86::LD_Fp80m     , X86::LD_F80m   },
426  { X86::MUL_Fp32m    , X86::MUL_F32m  },
427  { X86::MUL_Fp64m    , X86::MUL_F64m  },
428  { X86::MUL_Fp64m32  , X86::MUL_F32m  },
429  { X86::MUL_Fp80m32  , X86::MUL_F32m  },
430  { X86::MUL_Fp80m64  , X86::MUL_F64m  },
431  { X86::MUL_FpI16m32 , X86::MUL_FI16m },
432  { X86::MUL_FpI16m64 , X86::MUL_FI16m },
433  { X86::MUL_FpI16m80 , X86::MUL_FI16m },
434  { X86::MUL_FpI32m32 , X86::MUL_FI32m },
435  { X86::MUL_FpI32m64 , X86::MUL_FI32m },
436  { X86::MUL_FpI32m80 , X86::MUL_FI32m },
437  { X86::SIN_Fp32     , X86::SIN_F     },
438  { X86::SIN_Fp64     , X86::SIN_F     },
439  { X86::SIN_Fp80     , X86::SIN_F     },
440  { X86::SQRT_Fp32    , X86::SQRT_F    },
441  { X86::SQRT_Fp64    , X86::SQRT_F    },
442  { X86::SQRT_Fp80    , X86::SQRT_F    },
443  { X86::ST_Fp32m     , X86::ST_F32m   },
444  { X86::ST_Fp64m     , X86::ST_F64m   },
445  { X86::ST_Fp64m32   , X86::ST_F32m   },
446  { X86::ST_Fp80m32   , X86::ST_F32m   },
447  { X86::ST_Fp80m64   , X86::ST_F64m   },
448  { X86::ST_FpP80m    , X86::ST_FP80m  },
449  { X86::SUBR_Fp32m   , X86::SUBR_F32m },
450  { X86::SUBR_Fp64m   , X86::SUBR_F64m },
451  { X86::SUBR_Fp64m32 , X86::SUBR_F32m },
452  { X86::SUBR_Fp80m32 , X86::SUBR_F32m },
453  { X86::SUBR_Fp80m64 , X86::SUBR_F64m },
454  { X86::SUBR_FpI16m32, X86::SUBR_FI16m},
455  { X86::SUBR_FpI16m64, X86::SUBR_FI16m},
456  { X86::SUBR_FpI16m80, X86::SUBR_FI16m},
457  { X86::SUBR_FpI32m32, X86::SUBR_FI32m},
458  { X86::SUBR_FpI32m64, X86::SUBR_FI32m},
459  { X86::SUBR_FpI32m80, X86::SUBR_FI32m},
460  { X86::SUB_Fp32m    , X86::SUB_F32m  },
461  { X86::SUB_Fp64m    , X86::SUB_F64m  },
462  { X86::SUB_Fp64m32  , X86::SUB_F32m  },
463  { X86::SUB_Fp80m32  , X86::SUB_F32m  },
464  { X86::SUB_Fp80m64  , X86::SUB_F64m  },
465  { X86::SUB_FpI16m32 , X86::SUB_FI16m },
466  { X86::SUB_FpI16m64 , X86::SUB_FI16m },
467  { X86::SUB_FpI16m80 , X86::SUB_FI16m },
468  { X86::SUB_FpI32m32 , X86::SUB_FI32m },
469  { X86::SUB_FpI32m64 , X86::SUB_FI32m },
470  { X86::SUB_FpI32m80 , X86::SUB_FI32m },
471  { X86::TST_Fp32     , X86::TST_F     },
472  { X86::TST_Fp64     , X86::TST_F     },
473  { X86::TST_Fp80     , X86::TST_F     },
474  { X86::UCOM_FpIr32  , X86::UCOM_FIr  },
475  { X86::UCOM_FpIr64  , X86::UCOM_FIr  },
476  { X86::UCOM_FpIr80  , X86::UCOM_FIr  },
477  { X86::UCOM_Fpr32   , X86::UCOM_Fr   },
478  { X86::UCOM_Fpr64   , X86::UCOM_Fr   },
479  { X86::UCOM_Fpr80   , X86::UCOM_Fr   },
480};
481
482static unsigned getConcreteOpcode(unsigned Opcode) {
483  ASSERT_SORTED(OpcodeTable);
484  int Opc = Lookup(OpcodeTable, ARRAY_SIZE(OpcodeTable), Opcode);
485  assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!");
486  return Opc;
487}
488
489//===----------------------------------------------------------------------===//
490// Helper Methods
491//===----------------------------------------------------------------------===//
492
493// PopTable - Sorted map of instructions to their popping version.  The first
494// element is an instruction, the second is the version which pops.
495//
496static const TableEntry PopTable[] = {
497  { X86::ADD_FrST0 , X86::ADD_FPrST0  },
498
499  { X86::DIVR_FrST0, X86::DIVR_FPrST0 },
500  { X86::DIV_FrST0 , X86::DIV_FPrST0  },
501
502  { X86::IST_F16m  , X86::IST_FP16m   },
503  { X86::IST_F32m  , X86::IST_FP32m   },
504
505  { X86::MUL_FrST0 , X86::MUL_FPrST0  },
506
507  { X86::ST_F32m   , X86::ST_FP32m    },
508  { X86::ST_F64m   , X86::ST_FP64m    },
509  { X86::ST_Frr    , X86::ST_FPrr     },
510
511  { X86::SUBR_FrST0, X86::SUBR_FPrST0 },
512  { X86::SUB_FrST0 , X86::SUB_FPrST0  },
513
514  { X86::UCOM_FIr  , X86::UCOM_FIPr   },
515
516  { X86::UCOM_FPr  , X86::UCOM_FPPr   },
517  { X86::UCOM_Fr   , X86::UCOM_FPr    },
518};
519
520/// popStackAfter - Pop the current value off of the top of the FP stack after
521/// the specified instruction.  This attempts to be sneaky and combine the pop
522/// into the instruction itself if possible.  The iterator is left pointing to
523/// the last instruction, be it a new pop instruction inserted, or the old
524/// instruction if it was modified in place.
525///
526void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
527  ASSERT_SORTED(PopTable);
528  assert(StackTop > 0 && "Cannot pop empty stack!");
529  RegMap[Stack[--StackTop]] = ~0;     // Update state
530
531  // Check to see if there is a popping version of this instruction...
532  int Opcode = Lookup(PopTable, ARRAY_SIZE(PopTable), I->getOpcode());
533  if (Opcode != -1) {
534    I->setInstrDescriptor(TII->get(Opcode));
535    if (Opcode == X86::UCOM_FPPr)
536      I->RemoveOperand(0);
537  } else {    // Insert an explicit pop
538    I = BuildMI(*MBB, ++I, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
539  }
540}
541
542/// freeStackSlotAfter - Free the specified register from the register stack, so
543/// that it is no longer in a register.  If the register is currently at the top
544/// of the stack, we just pop the current instruction, otherwise we store the
545/// current top-of-stack into the specified slot, then pop the top of stack.
546void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) {
547  if (getStackEntry(0) == FPRegNo) {  // already at the top of stack? easy.
548    popStackAfter(I);
549    return;
550  }
551
552  // Otherwise, store the top of stack into the dead slot, killing the operand
553  // without having to add in an explicit xchg then pop.
554  //
555  unsigned STReg    = getSTReg(FPRegNo);
556  unsigned OldSlot  = getSlot(FPRegNo);
557  unsigned TopReg   = Stack[StackTop-1];
558  Stack[OldSlot]    = TopReg;
559  RegMap[TopReg]    = OldSlot;
560  RegMap[FPRegNo]   = ~0;
561  Stack[--StackTop] = ~0;
562  I = BuildMI(*MBB, ++I, TII->get(X86::ST_FPrr)).addReg(STReg);
563}
564
565
566static unsigned getFPReg(const MachineOperand &MO) {
567  assert(MO.isRegister() && "Expected an FP register!");
568  unsigned Reg = MO.getReg();
569  assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
570  return Reg - X86::FP0;
571}
572
573
574//===----------------------------------------------------------------------===//
575// Instruction transformation implementation
576//===----------------------------------------------------------------------===//
577
578/// handleZeroArgFP - ST(0) = fld0    ST(0) = flds <mem>
579///
580void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
581  MachineInstr *MI = I;
582  unsigned DestReg = getFPReg(MI->getOperand(0));
583
584  // Change from the pseudo instruction to the concrete instruction.
585  MI->RemoveOperand(0);   // Remove the explicit ST(0) operand
586  MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode())));
587
588  // Result gets pushed on the stack.
589  pushReg(DestReg);
590}
591
592/// handleOneArgFP - fst <mem>, ST(0)
593///
594void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
595  MachineInstr *MI = I;
596  unsigned NumOps = MI->getInstrDescriptor()->numOperands;
597  assert((NumOps == 5 || NumOps == 1) &&
598         "Can only handle fst* & ftst instructions!");
599
600  // Is this the last use of the source register?
601  unsigned Reg = getFPReg(MI->getOperand(NumOps-1));
602  bool KillsSrc = LV->KillsRegister(MI, X86::FP0+Reg);
603
604  // FISTP64m is strange because there isn't a non-popping versions.
605  // If we have one _and_ we don't want to pop the operand, duplicate the value
606  // on the stack instead of moving it.  This ensure that popping the value is
607  // always ok.
608  // Ditto FISTTP16m, FISTTP32m, FISTTP64m.
609  //
610  if (!KillsSrc &&
611      (MI->getOpcode() == X86::IST_Fp64m32 ||
612       MI->getOpcode() == X86::ISTT_Fp16m32 ||
613       MI->getOpcode() == X86::ISTT_Fp32m32 ||
614       MI->getOpcode() == X86::ISTT_Fp64m32 ||
615       MI->getOpcode() == X86::IST_Fp64m64 ||
616       MI->getOpcode() == X86::ISTT_Fp16m64 ||
617       MI->getOpcode() == X86::ISTT_Fp32m64 ||
618       MI->getOpcode() == X86::ISTT_Fp64m64 ||
619       MI->getOpcode() == X86::ST_FpP80m)) {
620    duplicateToTop(Reg, 7 /*temp register*/, I);
621  } else {
622    moveToTop(Reg, I);            // Move to the top of the stack...
623  }
624
625  // Convert from the pseudo instruction to the concrete instruction.
626  MI->RemoveOperand(NumOps-1);    // Remove explicit ST(0) operand
627  MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode())));
628
629  if (MI->getOpcode() == X86::IST_FP64m ||
630      MI->getOpcode() == X86::ISTT_FP16m ||
631      MI->getOpcode() == X86::ISTT_FP32m ||
632      MI->getOpcode() == X86::ISTT_FP64m ||
633      MI->getOpcode() == X86::ST_FP80m) {
634    assert(StackTop > 0 && "Stack empty??");
635    --StackTop;
636  } else if (KillsSrc) { // Last use of operand?
637    popStackAfter(I);
638  }
639}
640
641
642/// handleOneArgFPRW: Handle instructions that read from the top of stack and
643/// replace the value with a newly computed value.  These instructions may have
644/// non-fp operands after their FP operands.
645///
646///  Examples:
647///     R1 = fchs R2
648///     R1 = fadd R2, [mem]
649///
650void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
651  MachineInstr *MI = I;
652  unsigned NumOps = MI->getInstrDescriptor()->numOperands;
653  assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
654
655  // Is this the last use of the source register?
656  unsigned Reg = getFPReg(MI->getOperand(1));
657  bool KillsSrc = LV->KillsRegister(MI, X86::FP0+Reg);
658
659  if (KillsSrc) {
660    // If this is the last use of the source register, just make sure it's on
661    // the top of the stack.
662    moveToTop(Reg, I);
663    assert(StackTop > 0 && "Stack cannot be empty!");
664    --StackTop;
665    pushReg(getFPReg(MI->getOperand(0)));
666  } else {
667    // If this is not the last use of the source register, _copy_ it to the top
668    // of the stack.
669    duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I);
670  }
671
672  // Change from the pseudo instruction to the concrete instruction.
673  MI->RemoveOperand(1);   // Drop the source operand.
674  MI->RemoveOperand(0);   // Drop the destination operand.
675  MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode())));
676}
677
678
679//===----------------------------------------------------------------------===//
680// Define tables of various ways to map pseudo instructions
681//
682
683// ForwardST0Table - Map: A = B op C  into: ST(0) = ST(0) op ST(i)
684static const TableEntry ForwardST0Table[] = {
685  { X86::ADD_Fp32  , X86::ADD_FST0r },
686  { X86::ADD_Fp64  , X86::ADD_FST0r },
687  { X86::DIV_Fp32  , X86::DIV_FST0r },
688  { X86::DIV_Fp64  , X86::DIV_FST0r },
689  { X86::MUL_Fp32  , X86::MUL_FST0r },
690  { X86::MUL_Fp64  , X86::MUL_FST0r },
691  { X86::SUB_Fp32  , X86::SUB_FST0r },
692  { X86::SUB_Fp64  , X86::SUB_FST0r },
693};
694
695// ReverseST0Table - Map: A = B op C  into: ST(0) = ST(i) op ST(0)
696static const TableEntry ReverseST0Table[] = {
697  { X86::ADD_Fp32  , X86::ADD_FST0r  },   // commutative
698  { X86::ADD_Fp64  , X86::ADD_FST0r  },   // commutative
699  { X86::DIV_Fp32  , X86::DIVR_FST0r },
700  { X86::DIV_Fp64  , X86::DIVR_FST0r },
701  { X86::MUL_Fp32  , X86::MUL_FST0r  },   // commutative
702  { X86::MUL_Fp64  , X86::MUL_FST0r  },   // commutative
703  { X86::SUB_Fp32  , X86::SUBR_FST0r },
704  { X86::SUB_Fp64  , X86::SUBR_FST0r },
705};
706
707// ForwardSTiTable - Map: A = B op C  into: ST(i) = ST(0) op ST(i)
708static const TableEntry ForwardSTiTable[] = {
709  { X86::ADD_Fp32  , X86::ADD_FrST0  },   // commutative
710  { X86::ADD_Fp64  , X86::ADD_FrST0  },   // commutative
711  { X86::DIV_Fp32  , X86::DIVR_FrST0 },
712  { X86::DIV_Fp64  , X86::DIVR_FrST0 },
713  { X86::MUL_Fp32  , X86::MUL_FrST0  },   // commutative
714  { X86::MUL_Fp64  , X86::MUL_FrST0  },   // commutative
715  { X86::SUB_Fp32  , X86::SUBR_FrST0 },
716  { X86::SUB_Fp64  , X86::SUBR_FrST0 },
717};
718
719// ReverseSTiTable - Map: A = B op C  into: ST(i) = ST(i) op ST(0)
720static const TableEntry ReverseSTiTable[] = {
721  { X86::ADD_Fp32  , X86::ADD_FrST0 },
722  { X86::ADD_Fp64  , X86::ADD_FrST0 },
723  { X86::DIV_Fp32  , X86::DIV_FrST0 },
724  { X86::DIV_Fp64  , X86::DIV_FrST0 },
725  { X86::MUL_Fp32  , X86::MUL_FrST0 },
726  { X86::MUL_Fp64  , X86::MUL_FrST0 },
727  { X86::SUB_Fp32  , X86::SUB_FrST0 },
728  { X86::SUB_Fp64  , X86::SUB_FrST0 },
729};
730
731
732/// handleTwoArgFP - Handle instructions like FADD and friends which are virtual
733/// instructions which need to be simplified and possibly transformed.
734///
735/// Result: ST(0) = fsub  ST(0), ST(i)
736///         ST(i) = fsub  ST(0), ST(i)
737///         ST(0) = fsubr ST(0), ST(i)
738///         ST(i) = fsubr ST(0), ST(i)
739///
740void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
741  ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
742  ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
743  MachineInstr *MI = I;
744
745  unsigned NumOperands = MI->getInstrDescriptor()->numOperands;
746  assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
747  unsigned Dest = getFPReg(MI->getOperand(0));
748  unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
749  unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
750  bool KillsOp0 = LV->KillsRegister(MI, X86::FP0+Op0);
751  bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1);
752
753  unsigned TOS = getStackEntry(0);
754
755  // One of our operands must be on the top of the stack.  If neither is yet, we
756  // need to move one.
757  if (Op0 != TOS && Op1 != TOS) {   // No operand at TOS?
758    // We can choose to move either operand to the top of the stack.  If one of
759    // the operands is killed by this instruction, we want that one so that we
760    // can update right on top of the old version.
761    if (KillsOp0) {
762      moveToTop(Op0, I);         // Move dead operand to TOS.
763      TOS = Op0;
764    } else if (KillsOp1) {
765      moveToTop(Op1, I);
766      TOS = Op1;
767    } else {
768      // All of the operands are live after this instruction executes, so we
769      // cannot update on top of any operand.  Because of this, we must
770      // duplicate one of the stack elements to the top.  It doesn't matter
771      // which one we pick.
772      //
773      duplicateToTop(Op0, Dest, I);
774      Op0 = TOS = Dest;
775      KillsOp0 = true;
776    }
777  } else if (!KillsOp0 && !KillsOp1) {
778    // If we DO have one of our operands at the top of the stack, but we don't
779    // have a dead operand, we must duplicate one of the operands to a new slot
780    // on the stack.
781    duplicateToTop(Op0, Dest, I);
782    Op0 = TOS = Dest;
783    KillsOp0 = true;
784  }
785
786  // Now we know that one of our operands is on the top of the stack, and at
787  // least one of our operands is killed by this instruction.
788  assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) &&
789         "Stack conditions not set up right!");
790
791  // We decide which form to use based on what is on the top of the stack, and
792  // which operand is killed by this instruction.
793  const TableEntry *InstTable;
794  bool isForward = TOS == Op0;
795  bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0);
796  if (updateST0) {
797    if (isForward)
798      InstTable = ForwardST0Table;
799    else
800      InstTable = ReverseST0Table;
801  } else {
802    if (isForward)
803      InstTable = ForwardSTiTable;
804    else
805      InstTable = ReverseSTiTable;
806  }
807
808  int Opcode = Lookup(InstTable, ARRAY_SIZE(ForwardST0Table), MI->getOpcode());
809  assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
810
811  // NotTOS - The register which is not on the top of stack...
812  unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
813
814  // Replace the old instruction with a new instruction
815  MBB->remove(I++);
816  I = BuildMI(*MBB, I, TII->get(Opcode)).addReg(getSTReg(NotTOS));
817
818  // If both operands are killed, pop one off of the stack in addition to
819  // overwriting the other one.
820  if (KillsOp0 && KillsOp1 && Op0 != Op1) {
821    assert(!updateST0 && "Should have updated other operand!");
822    popStackAfter(I);   // Pop the top of stack
823  }
824
825  // Update stack information so that we know the destination register is now on
826  // the stack.
827  unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS);
828  assert(UpdatedSlot < StackTop && Dest < 7);
829  Stack[UpdatedSlot]   = Dest;
830  RegMap[Dest]         = UpdatedSlot;
831  delete MI;   // Remove the old instruction
832}
833
834/// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP
835/// register arguments and no explicit destinations.
836///
837void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
838  ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
839  ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
840  MachineInstr *MI = I;
841
842  unsigned NumOperands = MI->getInstrDescriptor()->numOperands;
843  assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
844  unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
845  unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
846  bool KillsOp0 = LV->KillsRegister(MI, X86::FP0+Op0);
847  bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1);
848
849  // Make sure the first operand is on the top of stack, the other one can be
850  // anywhere.
851  moveToTop(Op0, I);
852
853  // Change from the pseudo instruction to the concrete instruction.
854  MI->getOperand(0).setReg(getSTReg(Op1));
855  MI->RemoveOperand(1);
856  MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode())));
857
858  // If any of the operands are killed by this instruction, free them.
859  if (KillsOp0) freeStackSlotAfter(I, Op0);
860  if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1);
861}
862
863/// handleCondMovFP - Handle two address conditional move instructions.  These
864/// instructions move a st(i) register to st(0) iff a condition is true.  These
865/// instructions require that the first operand is at the top of the stack, but
866/// otherwise don't modify the stack at all.
867void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
868  MachineInstr *MI = I;
869
870  unsigned Op0 = getFPReg(MI->getOperand(0));
871  unsigned Op1 = getFPReg(MI->getOperand(2));
872  bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1);
873
874  // The first operand *must* be on the top of the stack.
875  moveToTop(Op0, I);
876
877  // Change the second operand to the stack register that the operand is in.
878  // Change from the pseudo instruction to the concrete instruction.
879  MI->RemoveOperand(0);
880  MI->RemoveOperand(1);
881  MI->getOperand(0).setReg(getSTReg(Op1));
882  MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode())));
883
884  // If we kill the second operand, make sure to pop it from the stack.
885  if (Op0 != Op1 && KillsOp1) {
886    // Get this value off of the register stack.
887    freeStackSlotAfter(I, Op1);
888  }
889}
890
891
892/// handleSpecialFP - Handle special instructions which behave unlike other
893/// floating point instructions.  This is primarily intended for use by pseudo
894/// instructions.
895///
896void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
897  MachineInstr *MI = I;
898  switch (MI->getOpcode()) {
899  default: assert(0 && "Unknown SpecialFP instruction!");
900  case X86::FpGETRESULT32:  // Appears immediately after a call returning FP type!
901  case X86::FpGETRESULT64:  // Appears immediately after a call returning FP type!
902    assert(StackTop == 0 && "Stack should be empty after a call!");
903    pushReg(getFPReg(MI->getOperand(0)));
904    break;
905  case X86::FpSETRESULT32:
906  case X86::FpSETRESULT64:
907    assert(StackTop == 1 && "Stack should have one element on it to return!");
908    --StackTop;   // "Forget" we have something on the top of stack!
909    break;
910  case X86::MOV_Fp3232:
911  case X86::MOV_Fp3264:
912  case X86::MOV_Fp6432:
913  case X86::MOV_Fp6464:
914  case X86::MOV_Fp3280:
915  case X86::MOV_Fp6480:
916  case X86::MOV_Fp8032:
917  case X86::MOV_Fp8064:
918  case X86::MOV_Fp8080: {
919    unsigned SrcReg = getFPReg(MI->getOperand(1));
920    unsigned DestReg = getFPReg(MI->getOperand(0));
921
922    if (LV->KillsRegister(MI, X86::FP0+SrcReg)) {
923      // If the input operand is killed, we can just change the owner of the
924      // incoming stack slot into the result.
925      unsigned Slot = getSlot(SrcReg);
926      assert(Slot < 7 && DestReg < 7 && "FpMOV operands invalid!");
927      Stack[Slot] = DestReg;
928      RegMap[DestReg] = Slot;
929
930    } else {
931      // For FMOV we just duplicate the specified value to a new stack slot.
932      // This could be made better, but would require substantial changes.
933      duplicateToTop(SrcReg, DestReg, I);
934    }
935    break;
936  }
937  }
938
939  I = MBB->erase(I);  // Remove the pseudo instruction
940  --I;
941}
942