X86FloatingPoint.cpp revision 920c37afc5896201ec014041cbd270289baa25c0 
1//===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the pass which converts floating point instructions from
11// virtual registers into register stack instructions.  This pass uses live
12// variable information to indicate where the FPn registers are used and their
13// lifetimes.
14//
15// This pass is hampered by the lack of decent CFG manipulation routines for
16// machine code.  In particular, this wants to be able to split critical edges
17// as necessary, traverse the machine basic block CFG in depth-first order, and
18// allow there to be multiple machine basic blocks for each LLVM basicblock
19// (needed for critical edge splitting).
20//
21// In particular, this pass currently barfs on critical edges.  Because of this,
22// it requires the instruction selector to insert FP_REG_KILL instructions on
23// the exits of any basic block that has critical edges going from it, or which
24// branch to a critical basic block.
25//
26// FIXME: this is not implemented yet.  The stackifier pass only works on local
27// basic blocks.
28//
29//===----------------------------------------------------------------------===//
30
31#define DEBUG_TYPE "x86-codegen"
32#include "X86.h"
33#include "X86InstrInfo.h"
34#include "llvm/CodeGen/MachineFunctionPass.h"
35#include "llvm/CodeGen/MachineInstrBuilder.h"
36#include "llvm/CodeGen/MachineRegisterInfo.h"
37#include "llvm/CodeGen/Passes.h"
38#include "llvm/Target/TargetInstrInfo.h"
39#include "llvm/Target/TargetMachine.h"
40#include "llvm/Support/Debug.h"
41#include "llvm/Support/Compiler.h"
42#include "llvm/ADT/DepthFirstIterator.h"
43#include "llvm/ADT/SmallVector.h"
44#include "llvm/ADT/Statistic.h"
45#include "llvm/ADT/STLExtras.h"
46#include <algorithm>
47#include <set>
48using namespace llvm;
49
50STATISTIC(NumFXCH, "Number of fxch instructions inserted");
51STATISTIC(NumFP  , "Number of floating point instructions");
52
53namespace {
54  struct VISIBILITY_HIDDEN FPS : public MachineFunctionPass {
55    static char ID;
56    FPS() : MachineFunctionPass((intptr_t)&ID) {}
57
58    virtual bool runOnMachineFunction(MachineFunction &MF);
59
60    virtual const char *getPassName() const { return "X86 FP Stackifier"; }
61
62  private:
63    const TargetInstrInfo *TII; // Machine instruction info.
64    MachineBasicBlock *MBB;     // Current basic block
65    unsigned Stack[8];          // FP<n> Registers in each stack slot...
66    unsigned RegMap[8];         // Track which stack slot contains each register
67    unsigned StackTop;          // The current top of the FP stack.
68
69    void dumpStack() const {
70      cerr << "Stack contents:";
71      for (unsigned i = 0; i != StackTop; ++i) {
72        cerr << " FP" << Stack[i];
73        assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
74      }
75      cerr << "\n";
76    }
77  private:
78    /// isStackEmpty - Return true if the FP stack is empty.
79    bool isStackEmpty() const {
80      return StackTop == 0;
81    }
82
83    // getSlot - Return the stack slot number a particular register number is
84    // in.
85    unsigned getSlot(unsigned RegNo) const {
86      assert(RegNo < 8 && "Regno out of range!");
87      return RegMap[RegNo];
88    }
89
90    // getStackEntry - Return the X86::FP<n> register in register ST(i).
91    unsigned getStackEntry(unsigned STi) const {
92      assert(STi < StackTop && "Access past stack top!");
93      return Stack[StackTop-1-STi];
94    }
95
96    // getSTReg - Return the X86::ST(i) register which contains the specified
97    // FP<RegNo> register.
98    unsigned getSTReg(unsigned RegNo) const {
99      return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0;
100    }
101
102    // pushReg - Push the specified FP<n> register onto the stack.
103    void pushReg(unsigned Reg) {
104      assert(Reg < 8 && "Register number out of range!");
105      assert(StackTop < 8 && "Stack overflow!");
106      Stack[StackTop] = Reg;
107      RegMap[Reg] = StackTop++;
108    }
109
110    bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
111    void moveToTop(unsigned RegNo, MachineBasicBlock::iterator I) {
112      if (isAtTop(RegNo)) return;
113
114      unsigned STReg = getSTReg(RegNo);
115      unsigned RegOnTop = getStackEntry(0);
116
117      // Swap the slots the regs are in.
118      std::swap(RegMap[RegNo], RegMap[RegOnTop]);
119
120      // Swap stack slot contents.
121      assert(RegMap[RegOnTop] < StackTop);
122      std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
123
124      // Emit an fxch to update the runtime processors version of the state.
125      BuildMI(*MBB, I, TII->get(X86::XCH_F)).addReg(STReg);
126      NumFXCH++;
127    }
128
129    void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) {
130      unsigned STReg = getSTReg(RegNo);
131      pushReg(AsReg);   // New register on top of stack
132
133      BuildMI(*MBB, I, TII->get(X86::LD_Frr)).addReg(STReg);
134    }
135
136    // popStackAfter - Pop the current value off of the top of the FP stack
137    // after the specified instruction.
138    void popStackAfter(MachineBasicBlock::iterator &I);
139
140    // freeStackSlotAfter - Free the specified register from the register stack,
141    // so that it is no longer in a register.  If the register is currently at
142    // the top of the stack, we just pop the current instruction, otherwise we
143    // store the current top-of-stack into the specified slot, then pop the top
144    // of stack.
145    void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
146
147    bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
148
149    void handleZeroArgFP(MachineBasicBlock::iterator &I);
150    void handleOneArgFP(MachineBasicBlock::iterator &I);
151    void handleOneArgFPRW(MachineBasicBlock::iterator &I);
152    void handleTwoArgFP(MachineBasicBlock::iterator &I);
153    void handleCompareFP(MachineBasicBlock::iterator &I);
154    void handleCondMovFP(MachineBasicBlock::iterator &I);
155    void handleSpecialFP(MachineBasicBlock::iterator &I);
156  };
157  char FPS::ID = 0;
158}
159
160FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); }
161
162/// getFPReg - Return the X86::FPx register number for the specified operand.
163/// For example, this returns 3 for X86::FP3.
164static unsigned getFPReg(const MachineOperand &MO) {
165  assert(MO.isRegister() && "Expected an FP register!");
166  unsigned Reg = MO.getReg();
167  assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
168  return Reg - X86::FP0;
169}
170
171
172/// runOnMachineFunction - Loop over all of the basic blocks, transforming FP
173/// register references into FP stack references.
174///
175bool FPS::runOnMachineFunction(MachineFunction &MF) {
176  // We only need to run this pass if there are any FP registers used in this
177  // function.  If it is all integer, there is nothing for us to do!
178  bool FPIsUsed = false;
179
180  assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!");
181  for (unsigned i = 0; i <= 6; ++i)
182    if (MF.getRegInfo().isPhysRegUsed(X86::FP0+i)) {
183      FPIsUsed = true;
184      break;
185    }
186
187  // Early exit.
188  if (!FPIsUsed) return false;
189
190  TII = MF.getTarget().getInstrInfo();
191  StackTop = 0;
192
193  // Process the function in depth first order so that we process at least one
194  // of the predecessors for every reachable block in the function.
195  std::set<MachineBasicBlock*> Processed;
196  MachineBasicBlock *Entry = MF.begin();
197
198  bool Changed = false;
199  for (df_ext_iterator<MachineBasicBlock*, std::set<MachineBasicBlock*> >
200         I = df_ext_begin(Entry, Processed), E = df_ext_end(Entry, Processed);
201       I != E; ++I)
202    Changed |= processBasicBlock(MF, **I);
203
204  return Changed;
205}
206
207/// processBasicBlock - Loop over all of the instructions in the basic block,
208/// transforming FP instructions into their stack form.
209///
210bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
211  bool Changed = false;
212  MBB = &BB;
213
214  for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
215    MachineInstr *MI = I;
216    unsigned Flags = MI->getDesc().TSFlags;
217
218    unsigned FPInstClass = Flags & X86II::FPTypeMask;
219    if (MI->getOpcode() == TargetInstrInfo::INLINEASM)
220      FPInstClass = X86II::SpecialFP;
221
222    if (FPInstClass == X86II::NotFP)
223      continue;  // Efficiently ignore non-fp insts!
224
225    MachineInstr *PrevMI = 0;
226    if (I != BB.begin())
227      PrevMI = prior(I);
228
229    ++NumFP;  // Keep track of # of pseudo instrs
230    DOUT << "\nFPInst:\t" << *MI;
231
232    // Get dead variables list now because the MI pointer may be deleted as part
233    // of processing!
234    SmallVector<unsigned, 8> DeadRegs;
235    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
236      const MachineOperand &MO = MI->getOperand(i);
237      if (MO.isRegister() && MO.isDead())
238        DeadRegs.push_back(MO.getReg());
239    }
240
241    switch (FPInstClass) {
242    case X86II::ZeroArgFP:  handleZeroArgFP(I); break;
243    case X86II::OneArgFP:   handleOneArgFP(I);  break;  // fstp ST(0)
244    case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0))
245    case X86II::TwoArgFP:   handleTwoArgFP(I);  break;
246    case X86II::CompareFP:  handleCompareFP(I); break;
247    case X86II::CondMovFP:  handleCondMovFP(I); break;
248    case X86II::SpecialFP:  handleSpecialFP(I); break;
249    default: assert(0 && "Unknown FP Type!");
250    }
251
252    // Check to see if any of the values defined by this instruction are dead
253    // after definition.  If so, pop them.
254    for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
255      unsigned Reg = DeadRegs[i];
256      if (Reg >= X86::FP0 && Reg <= X86::FP6) {
257        DOUT << "Register FP#" << Reg-X86::FP0 << " is dead!\n";
258        freeStackSlotAfter(I, Reg-X86::FP0);
259      }
260    }
261
262    // Print out all of the instructions expanded to if -debug
263    DEBUG(
264      MachineBasicBlock::iterator PrevI(PrevMI);
265      if (I == PrevI) {
266        cerr << "Just deleted pseudo instruction\n";
267      } else {
268        MachineBasicBlock::iterator Start = I;
269        // Rewind to first instruction newly inserted.
270        while (Start != BB.begin() && prior(Start) != PrevI) --Start;
271        cerr << "Inserted instructions:\n\t";
272        Start->print(*cerr.stream(), &MF.getTarget());
273        while (++Start != next(I)) {}
274      }
275      dumpStack();
276    );
277
278    Changed = true;
279  }
280
281  assert(isStackEmpty() && "Stack not empty at end of basic block?");
282  return Changed;
283}
284
285//===----------------------------------------------------------------------===//
286// Efficient Lookup Table Support
287//===----------------------------------------------------------------------===//
288
289namespace {
290  struct TableEntry {
291    unsigned from;
292    unsigned to;
293    bool operator<(const TableEntry &TE) const { return from < TE.from; }
294    friend bool operator<(const TableEntry &TE, unsigned V) {
295      return TE.from < V;
296    }
297    friend bool operator<(unsigned V, const TableEntry &TE) {
298      return V < TE.from;
299    }
300  };
301}
302
303static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
304  for (unsigned i = 0; i != NumEntries-1; ++i)
305    if (!(Table[i] < Table[i+1])) return false;
306  return true;
307}
308
309static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) {
310  const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
311  if (I != Table+N && I->from == Opcode)
312    return I->to;
313  return -1;
314}
315
316#ifdef NDEBUG
317#define ASSERT_SORTED(TABLE)
318#else
319#define ASSERT_SORTED(TABLE)                                              \
320  { static bool TABLE##Checked = false;                                   \
321    if (!TABLE##Checked) {                                                \
322       assert(TableIsSorted(TABLE, array_lengthof(TABLE)) &&              \
323              "All lookup tables must be sorted for efficient access!");  \
324       TABLE##Checked = true;                                             \
325    }                                                                     \
326  }
327#endif
328
329//===----------------------------------------------------------------------===//
330// Register File -> Register Stack Mapping Methods
331//===----------------------------------------------------------------------===//
332
333// OpcodeTable - Sorted map of register instructions to their stack version.
334// The first element is an register file pseudo instruction, the second is the
335// concrete X86 instruction which uses the register stack.
336//
337static const TableEntry OpcodeTable[] = {
338  { X86::ABS_Fp32     , X86::ABS_F     },
339  { X86::ABS_Fp64     , X86::ABS_F     },
340  { X86::ABS_Fp80     , X86::ABS_F     },
341  { X86::ADD_Fp32m    , X86::ADD_F32m  },
342  { X86::ADD_Fp64m    , X86::ADD_F64m  },
343  { X86::ADD_Fp64m32  , X86::ADD_F32m  },
344  { X86::ADD_Fp80m32  , X86::ADD_F32m  },
345  { X86::ADD_Fp80m64  , X86::ADD_F64m  },
346  { X86::ADD_FpI16m32 , X86::ADD_FI16m },
347  { X86::ADD_FpI16m64 , X86::ADD_FI16m },
348  { X86::ADD_FpI16m80 , X86::ADD_FI16m },
349  { X86::ADD_FpI32m32 , X86::ADD_FI32m },
350  { X86::ADD_FpI32m64 , X86::ADD_FI32m },
351  { X86::ADD_FpI32m80 , X86::ADD_FI32m },
352  { X86::CHS_Fp32     , X86::CHS_F     },
353  { X86::CHS_Fp64     , X86::CHS_F     },
354  { X86::CHS_Fp80     , X86::CHS_F     },
355  { X86::CMOVBE_Fp32  , X86::CMOVBE_F  },
356  { X86::CMOVBE_Fp64  , X86::CMOVBE_F  },
357  { X86::CMOVBE_Fp80  , X86::CMOVBE_F  },
358  { X86::CMOVB_Fp32   , X86::CMOVB_F   },
359  { X86::CMOVB_Fp64   , X86::CMOVB_F  },
360  { X86::CMOVB_Fp80   , X86::CMOVB_F  },
361  { X86::CMOVE_Fp32   , X86::CMOVE_F  },
362  { X86::CMOVE_Fp64   , X86::CMOVE_F   },
363  { X86::CMOVE_Fp80   , X86::CMOVE_F   },
364  { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F },
365  { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F },
366  { X86::CMOVNBE_Fp80 , X86::CMOVNBE_F },
367  { X86::CMOVNB_Fp32  , X86::CMOVNB_F  },
368  { X86::CMOVNB_Fp64  , X86::CMOVNB_F  },
369  { X86::CMOVNB_Fp80  , X86::CMOVNB_F  },
370  { X86::CMOVNE_Fp32  , X86::CMOVNE_F  },
371  { X86::CMOVNE_Fp64  , X86::CMOVNE_F  },
372  { X86::CMOVNE_Fp80  , X86::CMOVNE_F  },
373  { X86::CMOVNP_Fp32  , X86::CMOVNP_F  },
374  { X86::CMOVNP_Fp64  , X86::CMOVNP_F  },
375  { X86::CMOVNP_Fp80  , X86::CMOVNP_F  },
376  { X86::CMOVP_Fp32   , X86::CMOVP_F   },
377  { X86::CMOVP_Fp64   , X86::CMOVP_F   },
378  { X86::CMOVP_Fp80   , X86::CMOVP_F   },
379  { X86::COS_Fp32     , X86::COS_F     },
380  { X86::COS_Fp64     , X86::COS_F     },
381  { X86::COS_Fp80     , X86::COS_F     },
382  { X86::DIVR_Fp32m   , X86::DIVR_F32m },
383  { X86::DIVR_Fp64m   , X86::DIVR_F64m },
384  { X86::DIVR_Fp64m32 , X86::DIVR_F32m },
385  { X86::DIVR_Fp80m32 , X86::DIVR_F32m },
386  { X86::DIVR_Fp80m64 , X86::DIVR_F64m },
387  { X86::DIVR_FpI16m32, X86::DIVR_FI16m},
388  { X86::DIVR_FpI16m64, X86::DIVR_FI16m},
389  { X86::DIVR_FpI16m80, X86::DIVR_FI16m},
390  { X86::DIVR_FpI32m32, X86::DIVR_FI32m},
391  { X86::DIVR_FpI32m64, X86::DIVR_FI32m},
392  { X86::DIVR_FpI32m80, X86::DIVR_FI32m},
393  { X86::DIV_Fp32m    , X86::DIV_F32m  },
394  { X86::DIV_Fp64m    , X86::DIV_F64m  },
395  { X86::DIV_Fp64m32  , X86::DIV_F32m  },
396  { X86::DIV_Fp80m32  , X86::DIV_F32m  },
397  { X86::DIV_Fp80m64  , X86::DIV_F64m  },
398  { X86::DIV_FpI16m32 , X86::DIV_FI16m },
399  { X86::DIV_FpI16m64 , X86::DIV_FI16m },
400  { X86::DIV_FpI16m80 , X86::DIV_FI16m },
401  { X86::DIV_FpI32m32 , X86::DIV_FI32m },
402  { X86::DIV_FpI32m64 , X86::DIV_FI32m },
403  { X86::DIV_FpI32m80 , X86::DIV_FI32m },
404  { X86::ILD_Fp16m32  , X86::ILD_F16m  },
405  { X86::ILD_Fp16m64  , X86::ILD_F16m  },
406  { X86::ILD_Fp16m80  , X86::ILD_F16m  },
407  { X86::ILD_Fp32m32  , X86::ILD_F32m  },
408  { X86::ILD_Fp32m64  , X86::ILD_F32m  },
409  { X86::ILD_Fp32m80  , X86::ILD_F32m  },
410  { X86::ILD_Fp64m32  , X86::ILD_F64m  },
411  { X86::ILD_Fp64m64  , X86::ILD_F64m  },
412  { X86::ILD_Fp64m80  , X86::ILD_F64m  },
413  { X86::ISTT_Fp16m32 , X86::ISTT_FP16m},
414  { X86::ISTT_Fp16m64 , X86::ISTT_FP16m},
415  { X86::ISTT_Fp16m80 , X86::ISTT_FP16m},
416  { X86::ISTT_Fp32m32 , X86::ISTT_FP32m},
417  { X86::ISTT_Fp32m64 , X86::ISTT_FP32m},
418  { X86::ISTT_Fp32m80 , X86::ISTT_FP32m},
419  { X86::ISTT_Fp64m32 , X86::ISTT_FP64m},
420  { X86::ISTT_Fp64m64 , X86::ISTT_FP64m},
421  { X86::ISTT_Fp64m80 , X86::ISTT_FP64m},
422  { X86::IST_Fp16m32  , X86::IST_F16m  },
423  { X86::IST_Fp16m64  , X86::IST_F16m  },
424  { X86::IST_Fp16m80  , X86::IST_F16m  },
425  { X86::IST_Fp32m32  , X86::IST_F32m  },
426  { X86::IST_Fp32m64  , X86::IST_F32m  },
427  { X86::IST_Fp32m80  , X86::IST_F32m  },
428  { X86::IST_Fp64m32  , X86::IST_FP64m },
429  { X86::IST_Fp64m64  , X86::IST_FP64m },
430  { X86::IST_Fp64m80  , X86::IST_FP64m },
431  { X86::LD_Fp032     , X86::LD_F0     },
432  { X86::LD_Fp064     , X86::LD_F0     },
433  { X86::LD_Fp080     , X86::LD_F0     },
434  { X86::LD_Fp132     , X86::LD_F1     },
435  { X86::LD_Fp164     , X86::LD_F1     },
436  { X86::LD_Fp180     , X86::LD_F1     },
437  { X86::LD_Fp32m     , X86::LD_F32m   },
438  { X86::LD_Fp32m64   , X86::LD_F32m   },
439  { X86::LD_Fp32m80   , X86::LD_F32m   },
440  { X86::LD_Fp64m     , X86::LD_F64m   },
441  { X86::LD_Fp64m80   , X86::LD_F64m   },
442  { X86::LD_Fp80m     , X86::LD_F80m   },
443  { X86::MUL_Fp32m    , X86::MUL_F32m  },
444  { X86::MUL_Fp64m    , X86::MUL_F64m  },
445  { X86::MUL_Fp64m32  , X86::MUL_F32m  },
446  { X86::MUL_Fp80m32  , X86::MUL_F32m  },
447  { X86::MUL_Fp80m64  , X86::MUL_F64m  },
448  { X86::MUL_FpI16m32 , X86::MUL_FI16m },
449  { X86::MUL_FpI16m64 , X86::MUL_FI16m },
450  { X86::MUL_FpI16m80 , X86::MUL_FI16m },
451  { X86::MUL_FpI32m32 , X86::MUL_FI32m },
452  { X86::MUL_FpI32m64 , X86::MUL_FI32m },
453  { X86::MUL_FpI32m80 , X86::MUL_FI32m },
454  { X86::SIN_Fp32     , X86::SIN_F     },
455  { X86::SIN_Fp64     , X86::SIN_F     },
456  { X86::SIN_Fp80     , X86::SIN_F     },
457  { X86::SQRT_Fp32    , X86::SQRT_F    },
458  { X86::SQRT_Fp64    , X86::SQRT_F    },
459  { X86::SQRT_Fp80    , X86::SQRT_F    },
460  { X86::ST_Fp32m     , X86::ST_F32m   },
461  { X86::ST_Fp64m     , X86::ST_F64m   },
462  { X86::ST_Fp64m32   , X86::ST_F32m   },
463  { X86::ST_Fp80m32   , X86::ST_F32m   },
464  { X86::ST_Fp80m64   , X86::ST_F64m   },
465  { X86::ST_FpP80m    , X86::ST_FP80m  },
466  { X86::SUBR_Fp32m   , X86::SUBR_F32m },
467  { X86::SUBR_Fp64m   , X86::SUBR_F64m },
468  { X86::SUBR_Fp64m32 , X86::SUBR_F32m },
469  { X86::SUBR_Fp80m32 , X86::SUBR_F32m },
470  { X86::SUBR_Fp80m64 , X86::SUBR_F64m },
471  { X86::SUBR_FpI16m32, X86::SUBR_FI16m},
472  { X86::SUBR_FpI16m64, X86::SUBR_FI16m},
473  { X86::SUBR_FpI16m80, X86::SUBR_FI16m},
474  { X86::SUBR_FpI32m32, X86::SUBR_FI32m},
475  { X86::SUBR_FpI32m64, X86::SUBR_FI32m},
476  { X86::SUBR_FpI32m80, X86::SUBR_FI32m},
477  { X86::SUB_Fp32m    , X86::SUB_F32m  },
478  { X86::SUB_Fp64m    , X86::SUB_F64m  },
479  { X86::SUB_Fp64m32  , X86::SUB_F32m  },
480  { X86::SUB_Fp80m32  , X86::SUB_F32m  },
481  { X86::SUB_Fp80m64  , X86::SUB_F64m  },
482  { X86::SUB_FpI16m32 , X86::SUB_FI16m },
483  { X86::SUB_FpI16m64 , X86::SUB_FI16m },
484  { X86::SUB_FpI16m80 , X86::SUB_FI16m },
485  { X86::SUB_FpI32m32 , X86::SUB_FI32m },
486  { X86::SUB_FpI32m64 , X86::SUB_FI32m },
487  { X86::SUB_FpI32m80 , X86::SUB_FI32m },
488  { X86::TST_Fp32     , X86::TST_F     },
489  { X86::TST_Fp64     , X86::TST_F     },
490  { X86::TST_Fp80     , X86::TST_F     },
491  { X86::UCOM_FpIr32  , X86::UCOM_FIr  },
492  { X86::UCOM_FpIr64  , X86::UCOM_FIr  },
493  { X86::UCOM_FpIr80  , X86::UCOM_FIr  },
494  { X86::UCOM_Fpr32   , X86::UCOM_Fr   },
495  { X86::UCOM_Fpr64   , X86::UCOM_Fr   },
496  { X86::UCOM_Fpr80   , X86::UCOM_Fr   },
497};
498
499static unsigned getConcreteOpcode(unsigned Opcode) {
500  ASSERT_SORTED(OpcodeTable);
501  int Opc = Lookup(OpcodeTable, array_lengthof(OpcodeTable), Opcode);
502  assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!");
503  return Opc;
504}
505
506//===----------------------------------------------------------------------===//
507// Helper Methods
508//===----------------------------------------------------------------------===//
509
510// PopTable - Sorted map of instructions to their popping version.  The first
511// element is an instruction, the second is the version which pops.
512//
513static const TableEntry PopTable[] = {
514  { X86::ADD_FrST0 , X86::ADD_FPrST0  },
515
516  { X86::DIVR_FrST0, X86::DIVR_FPrST0 },
517  { X86::DIV_FrST0 , X86::DIV_FPrST0  },
518
519  { X86::IST_F16m  , X86::IST_FP16m   },
520  { X86::IST_F32m  , X86::IST_FP32m   },
521
522  { X86::MUL_FrST0 , X86::MUL_FPrST0  },
523
524  { X86::ST_F32m   , X86::ST_FP32m    },
525  { X86::ST_F64m   , X86::ST_FP64m    },
526  { X86::ST_Frr    , X86::ST_FPrr     },
527
528  { X86::SUBR_FrST0, X86::SUBR_FPrST0 },
529  { X86::SUB_FrST0 , X86::SUB_FPrST0  },
530
531  { X86::UCOM_FIr  , X86::UCOM_FIPr   },
532
533  { X86::UCOM_FPr  , X86::UCOM_FPPr   },
534  { X86::UCOM_Fr   , X86::UCOM_FPr    },
535};
536
537/// popStackAfter - Pop the current value off of the top of the FP stack after
538/// the specified instruction.  This attempts to be sneaky and combine the pop
539/// into the instruction itself if possible.  The iterator is left pointing to
540/// the last instruction, be it a new pop instruction inserted, or the old
541/// instruction if it was modified in place.
542///
543void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
544  ASSERT_SORTED(PopTable);
545  assert(StackTop > 0 && "Cannot pop empty stack!");
546  RegMap[Stack[--StackTop]] = ~0;     // Update state
547
548  // Check to see if there is a popping version of this instruction...
549  int Opcode = Lookup(PopTable, array_lengthof(PopTable), I->getOpcode());
550  if (Opcode != -1) {
551    I->setDesc(TII->get(Opcode));
552    if (Opcode == X86::UCOM_FPPr)
553      I->RemoveOperand(0);
554  } else {    // Insert an explicit pop
555    I = BuildMI(*MBB, ++I, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
556  }
557}
558
559/// freeStackSlotAfter - Free the specified register from the register stack, so
560/// that it is no longer in a register.  If the register is currently at the top
561/// of the stack, we just pop the current instruction, otherwise we store the
562/// current top-of-stack into the specified slot, then pop the top of stack.
563void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) {
564  if (getStackEntry(0) == FPRegNo) {  // already at the top of stack? easy.
565    popStackAfter(I);
566    return;
567  }
568
569  // Otherwise, store the top of stack into the dead slot, killing the operand
570  // without having to add in an explicit xchg then pop.
571  //
572  unsigned STReg    = getSTReg(FPRegNo);
573  unsigned OldSlot  = getSlot(FPRegNo);
574  unsigned TopReg   = Stack[StackTop-1];
575  Stack[OldSlot]    = TopReg;
576  RegMap[TopReg]    = OldSlot;
577  RegMap[FPRegNo]   = ~0;
578  Stack[--StackTop] = ~0;
579  I = BuildMI(*MBB, ++I, TII->get(X86::ST_FPrr)).addReg(STReg);
580}
581
582
583//===----------------------------------------------------------------------===//
584// Instruction transformation implementation
585//===----------------------------------------------------------------------===//
586
587/// handleZeroArgFP - ST(0) = fld0    ST(0) = flds <mem>
588///
589void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
590  MachineInstr *MI = I;
591  unsigned DestReg = getFPReg(MI->getOperand(0));
592
593  // Change from the pseudo instruction to the concrete instruction.
594  MI->RemoveOperand(0);   // Remove the explicit ST(0) operand
595  MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
596
597  // Result gets pushed on the stack.
598  pushReg(DestReg);
599}
600
601/// handleOneArgFP - fst <mem>, ST(0)
602///
603void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
604  MachineInstr *MI = I;
605  unsigned NumOps = MI->getDesc().getNumOperands();
606  assert((NumOps == 5 || NumOps == 1) &&
607         "Can only handle fst* & ftst instructions!");
608
609  // Is this the last use of the source register?
610  unsigned Reg = getFPReg(MI->getOperand(NumOps-1));
611  bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
612
613  // FISTP64m is strange because there isn't a non-popping versions.
614  // If we have one _and_ we don't want to pop the operand, duplicate the value
615  // on the stack instead of moving it.  This ensure that popping the value is
616  // always ok.
617  // Ditto FISTTP16m, FISTTP32m, FISTTP64m, ST_FpP80m.
618  //
619  if (!KillsSrc &&
620      (MI->getOpcode() == X86::IST_Fp64m32 ||
621       MI->getOpcode() == X86::ISTT_Fp16m32 ||
622       MI->getOpcode() == X86::ISTT_Fp32m32 ||
623       MI->getOpcode() == X86::ISTT_Fp64m32 ||
624       MI->getOpcode() == X86::IST_Fp64m64 ||
625       MI->getOpcode() == X86::ISTT_Fp16m64 ||
626       MI->getOpcode() == X86::ISTT_Fp32m64 ||
627       MI->getOpcode() == X86::ISTT_Fp64m64 ||
628       MI->getOpcode() == X86::IST_Fp64m80 ||
629       MI->getOpcode() == X86::ISTT_Fp16m80 ||
630       MI->getOpcode() == X86::ISTT_Fp32m80 ||
631       MI->getOpcode() == X86::ISTT_Fp64m80 ||
632       MI->getOpcode() == X86::ST_FpP80m)) {
633    duplicateToTop(Reg, 7 /*temp register*/, I);
634  } else {
635    moveToTop(Reg, I);            // Move to the top of the stack...
636  }
637
638  // Convert from the pseudo instruction to the concrete instruction.
639  MI->RemoveOperand(NumOps-1);    // Remove explicit ST(0) operand
640  MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
641
642  if (MI->getOpcode() == X86::IST_FP64m ||
643      MI->getOpcode() == X86::ISTT_FP16m ||
644      MI->getOpcode() == X86::ISTT_FP32m ||
645      MI->getOpcode() == X86::ISTT_FP64m ||
646      MI->getOpcode() == X86::ST_FP80m) {
647    assert(StackTop > 0 && "Stack empty??");
648    --StackTop;
649  } else if (KillsSrc) { // Last use of operand?
650    popStackAfter(I);
651  }
652}
653
654
655/// handleOneArgFPRW: Handle instructions that read from the top of stack and
656/// replace the value with a newly computed value.  These instructions may have
657/// non-fp operands after their FP operands.
658///
659///  Examples:
660///     R1 = fchs R2
661///     R1 = fadd R2, [mem]
662///
663void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
664  MachineInstr *MI = I;
665  unsigned NumOps = MI->getDesc().getNumOperands();
666  assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
667
668  // Is this the last use of the source register?
669  unsigned Reg = getFPReg(MI->getOperand(1));
670  bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
671
672  if (KillsSrc) {
673    // If this is the last use of the source register, just make sure it's on
674    // the top of the stack.
675    moveToTop(Reg, I);
676    assert(StackTop > 0 && "Stack cannot be empty!");
677    --StackTop;
678    pushReg(getFPReg(MI->getOperand(0)));
679  } else {
680    // If this is not the last use of the source register, _copy_ it to the top
681    // of the stack.
682    duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I);
683  }
684
685  // Change from the pseudo instruction to the concrete instruction.
686  MI->RemoveOperand(1);   // Drop the source operand.
687  MI->RemoveOperand(0);   // Drop the destination operand.
688  MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
689}
690
691
692//===----------------------------------------------------------------------===//
693// Define tables of various ways to map pseudo instructions
694//
695
696// ForwardST0Table - Map: A = B op C  into: ST(0) = ST(0) op ST(i)
697static const TableEntry ForwardST0Table[] = {
698  { X86::ADD_Fp32  , X86::ADD_FST0r },
699  { X86::ADD_Fp64  , X86::ADD_FST0r },
700  { X86::ADD_Fp80  , X86::ADD_FST0r },
701  { X86::DIV_Fp32  , X86::DIV_FST0r },
702  { X86::DIV_Fp64  , X86::DIV_FST0r },
703  { X86::DIV_Fp80  , X86::DIV_FST0r },
704  { X86::MUL_Fp32  , X86::MUL_FST0r },
705  { X86::MUL_Fp64  , X86::MUL_FST0r },
706  { X86::MUL_Fp80  , X86::MUL_FST0r },
707  { X86::SUB_Fp32  , X86::SUB_FST0r },
708  { X86::SUB_Fp64  , X86::SUB_FST0r },
709  { X86::SUB_Fp80  , X86::SUB_FST0r },
710};
711
712// ReverseST0Table - Map: A = B op C  into: ST(0) = ST(i) op ST(0)
713static const TableEntry ReverseST0Table[] = {
714  { X86::ADD_Fp32  , X86::ADD_FST0r  },   // commutative
715  { X86::ADD_Fp64  , X86::ADD_FST0r  },   // commutative
716  { X86::ADD_Fp80  , X86::ADD_FST0r  },   // commutative
717  { X86::DIV_Fp32  , X86::DIVR_FST0r },
718  { X86::DIV_Fp64  , X86::DIVR_FST0r },
719  { X86::DIV_Fp80  , X86::DIVR_FST0r },
720  { X86::MUL_Fp32  , X86::MUL_FST0r  },   // commutative
721  { X86::MUL_Fp64  , X86::MUL_FST0r  },   // commutative
722  { X86::MUL_Fp80  , X86::MUL_FST0r  },   // commutative
723  { X86::SUB_Fp32  , X86::SUBR_FST0r },
724  { X86::SUB_Fp64  , X86::SUBR_FST0r },
725  { X86::SUB_Fp80  , X86::SUBR_FST0r },
726};
727
728// ForwardSTiTable - Map: A = B op C  into: ST(i) = ST(0) op ST(i)
729static const TableEntry ForwardSTiTable[] = {
730  { X86::ADD_Fp32  , X86::ADD_FrST0  },   // commutative
731  { X86::ADD_Fp64  , X86::ADD_FrST0  },   // commutative
732  { X86::ADD_Fp80  , X86::ADD_FrST0  },   // commutative
733  { X86::DIV_Fp32  , X86::DIVR_FrST0 },
734  { X86::DIV_Fp64  , X86::DIVR_FrST0 },
735  { X86::DIV_Fp80  , X86::DIVR_FrST0 },
736  { X86::MUL_Fp32  , X86::MUL_FrST0  },   // commutative
737  { X86::MUL_Fp64  , X86::MUL_FrST0  },   // commutative
738  { X86::MUL_Fp80  , X86::MUL_FrST0  },   // commutative
739  { X86::SUB_Fp32  , X86::SUBR_FrST0 },
740  { X86::SUB_Fp64  , X86::SUBR_FrST0 },
741  { X86::SUB_Fp80  , X86::SUBR_FrST0 },
742};
743
744// ReverseSTiTable - Map: A = B op C  into: ST(i) = ST(i) op ST(0)
745static const TableEntry ReverseSTiTable[] = {
746  { X86::ADD_Fp32  , X86::ADD_FrST0 },
747  { X86::ADD_Fp64  , X86::ADD_FrST0 },
748  { X86::ADD_Fp80  , X86::ADD_FrST0 },
749  { X86::DIV_Fp32  , X86::DIV_FrST0 },
750  { X86::DIV_Fp64  , X86::DIV_FrST0 },
751  { X86::DIV_Fp80  , X86::DIV_FrST0 },
752  { X86::MUL_Fp32  , X86::MUL_FrST0 },
753  { X86::MUL_Fp64  , X86::MUL_FrST0 },
754  { X86::MUL_Fp80  , X86::MUL_FrST0 },
755  { X86::SUB_Fp32  , X86::SUB_FrST0 },
756  { X86::SUB_Fp64  , X86::SUB_FrST0 },
757  { X86::SUB_Fp80  , X86::SUB_FrST0 },
758};
759
760
761/// handleTwoArgFP - Handle instructions like FADD and friends which are virtual
762/// instructions which need to be simplified and possibly transformed.
763///
764/// Result: ST(0) = fsub  ST(0), ST(i)
765///         ST(i) = fsub  ST(0), ST(i)
766///         ST(0) = fsubr ST(0), ST(i)
767///         ST(i) = fsubr ST(0), ST(i)
768///
769void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
770  ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
771  ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
772  MachineInstr *MI = I;
773
774  unsigned NumOperands = MI->getDesc().getNumOperands();
775  assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
776  unsigned Dest = getFPReg(MI->getOperand(0));
777  unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
778  unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
779  bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
780  bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
781
782  unsigned TOS = getStackEntry(0);
783
784  // One of our operands must be on the top of the stack.  If neither is yet, we
785  // need to move one.
786  if (Op0 != TOS && Op1 != TOS) {   // No operand at TOS?
787    // We can choose to move either operand to the top of the stack.  If one of
788    // the operands is killed by this instruction, we want that one so that we
789    // can update right on top of the old version.
790    if (KillsOp0) {
791      moveToTop(Op0, I);         // Move dead operand to TOS.
792      TOS = Op0;
793    } else if (KillsOp1) {
794      moveToTop(Op1, I);
795      TOS = Op1;
796    } else {
797      // All of the operands are live after this instruction executes, so we
798      // cannot update on top of any operand.  Because of this, we must
799      // duplicate one of the stack elements to the top.  It doesn't matter
800      // which one we pick.
801      //
802      duplicateToTop(Op0, Dest, I);
803      Op0 = TOS = Dest;
804      KillsOp0 = true;
805    }
806  } else if (!KillsOp0 && !KillsOp1) {
807    // If we DO have one of our operands at the top of the stack, but we don't
808    // have a dead operand, we must duplicate one of the operands to a new slot
809    // on the stack.
810    duplicateToTop(Op0, Dest, I);
811    Op0 = TOS = Dest;
812    KillsOp0 = true;
813  }
814
815  // Now we know that one of our operands is on the top of the stack, and at
816  // least one of our operands is killed by this instruction.
817  assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) &&
818         "Stack conditions not set up right!");
819
820  // We decide which form to use based on what is on the top of the stack, and
821  // which operand is killed by this instruction.
822  const TableEntry *InstTable;
823  bool isForward = TOS == Op0;
824  bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0);
825  if (updateST0) {
826    if (isForward)
827      InstTable = ForwardST0Table;
828    else
829      InstTable = ReverseST0Table;
830  } else {
831    if (isForward)
832      InstTable = ForwardSTiTable;
833    else
834      InstTable = ReverseSTiTable;
835  }
836
837  int Opcode = Lookup(InstTable, array_lengthof(ForwardST0Table),
838                      MI->getOpcode());
839  assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
840
841  // NotTOS - The register which is not on the top of stack...
842  unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
843
844  // Replace the old instruction with a new instruction
845  MBB->remove(I++);
846  I = BuildMI(*MBB, I, TII->get(Opcode)).addReg(getSTReg(NotTOS));
847
848  // If both operands are killed, pop one off of the stack in addition to
849  // overwriting the other one.
850  if (KillsOp0 && KillsOp1 && Op0 != Op1) {
851    assert(!updateST0 && "Should have updated other operand!");
852    popStackAfter(I);   // Pop the top of stack
853  }
854
855  // Update stack information so that we know the destination register is now on
856  // the stack.
857  unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS);
858  assert(UpdatedSlot < StackTop && Dest < 7);
859  Stack[UpdatedSlot]   = Dest;
860  RegMap[Dest]         = UpdatedSlot;
861  delete MI;   // Remove the old instruction
862}
863
864/// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP
865/// register arguments and no explicit destinations.
866///
867void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
868  ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
869  ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
870  MachineInstr *MI = I;
871
872  unsigned NumOperands = MI->getDesc().getNumOperands();
873  assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
874  unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
875  unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
876  bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
877  bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
878
879  // Make sure the first operand is on the top of stack, the other one can be
880  // anywhere.
881  moveToTop(Op0, I);
882
883  // Change from the pseudo instruction to the concrete instruction.
884  MI->getOperand(0).setReg(getSTReg(Op1));
885  MI->RemoveOperand(1);
886  MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
887
888  // If any of the operands are killed by this instruction, free them.
889  if (KillsOp0) freeStackSlotAfter(I, Op0);
890  if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1);
891}
892
893/// handleCondMovFP - Handle two address conditional move instructions.  These
894/// instructions move a st(i) register to st(0) iff a condition is true.  These
895/// instructions require that the first operand is at the top of the stack, but
896/// otherwise don't modify the stack at all.
897void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
898  MachineInstr *MI = I;
899
900  unsigned Op0 = getFPReg(MI->getOperand(0));
901  unsigned Op1 = getFPReg(MI->getOperand(2));
902  bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
903
904  // The first operand *must* be on the top of the stack.
905  moveToTop(Op0, I);
906
907  // Change the second operand to the stack register that the operand is in.
908  // Change from the pseudo instruction to the concrete instruction.
909  MI->RemoveOperand(0);
910  MI->RemoveOperand(1);
911  MI->getOperand(0).setReg(getSTReg(Op1));
912  MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
913
914  // If we kill the second operand, make sure to pop it from the stack.
915  if (Op0 != Op1 && KillsOp1) {
916    // Get this value off of the register stack.
917    freeStackSlotAfter(I, Op1);
918  }
919}
920
921
922/// handleSpecialFP - Handle special instructions which behave unlike other
923/// floating point instructions.  This is primarily intended for use by pseudo
924/// instructions.
925///
926void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
927  MachineInstr *MI = I;
928  switch (MI->getOpcode()) {
929  default: assert(0 && "Unknown SpecialFP instruction!");
930  case X86::FpGET_ST0_32:// Appears immediately after a call returning FP type!
931  case X86::FpGET_ST0_64:// Appears immediately after a call returning FP type!
932  case X86::FpGET_ST0_80:// Appears immediately after a call returning FP type!
933    assert(StackTop == 0 && "Stack should be empty after a call!");
934    pushReg(getFPReg(MI->getOperand(0)));
935    break;
936  case X86::FpGET_ST1_32:// Appears immediately after a call returning FP type!
937  case X86::FpGET_ST1_64:// Appears immediately after a call returning FP type!
938  case X86::FpGET_ST1_80:{// Appears immediately after a call returning FP type!
939    // FpGET_ST1 should occur right after a FpGET_ST0 for a call or inline asm.
940    // The pattern we expect is:
941    //  CALL
942    //  FP1 = FpGET_ST0
943    //  FP4 = FpGET_ST1
944    //
945    // At this point, we've pushed FP1 on the top of stack, so it should be
946    // present if it isn't dead.  If it was dead, we already emitted a pop to
947    // remove it from the stack and StackTop = 0.
948
949    // Push FP4 as top of stack next.
950    pushReg(getFPReg(MI->getOperand(0)));
951
952    // If StackTop was 0 before we pushed our operand, then ST(0) must have been
953    // dead.  In this case, the ST(1) value is the only thing that is live, so
954    // it should be on the TOS (after the pop that was emitted) and is.  Just
955    // continue in this case.
956    if (StackTop == 1)
957      break;
958
959    // Because pushReg just pushed ST(1) as TOS, we now have to swap the two top
960    // elements so that our accounting is correct.
961    unsigned RegOnTop = getStackEntry(0);
962    unsigned RegNo = getStackEntry(1);
963
964    // Swap the slots the regs are in.
965    std::swap(RegMap[RegNo], RegMap[RegOnTop]);
966
967    // Swap stack slot contents.
968    assert(RegMap[RegOnTop] < StackTop);
969    std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
970    break;
971  }
972  case X86::FpSET_ST0_32:
973  case X86::FpSET_ST0_64:
974  case X86::FpSET_ST0_80:
975    assert(StackTop == 1 && "Stack should have one element on it to return!");
976    --StackTop;   // "Forget" we have something on the top of stack!
977    break;
978  case X86::MOV_Fp3232:
979  case X86::MOV_Fp3264:
980  case X86::MOV_Fp6432:
981  case X86::MOV_Fp6464:
982  case X86::MOV_Fp3280:
983  case X86::MOV_Fp6480:
984  case X86::MOV_Fp8032:
985  case X86::MOV_Fp8064:
986  case X86::MOV_Fp8080: {
987    unsigned SrcReg = getFPReg(MI->getOperand(1));
988    unsigned DestReg = getFPReg(MI->getOperand(0));
989
990    if (MI->killsRegister(X86::FP0+SrcReg)) {
991      // If the input operand is killed, we can just change the owner of the
992      // incoming stack slot into the result.
993      unsigned Slot = getSlot(SrcReg);
994      assert(Slot < 7 && DestReg < 7 && "FpMOV operands invalid!");
995      Stack[Slot] = DestReg;
996      RegMap[DestReg] = Slot;
997
998    } else {
999      // For FMOV we just duplicate the specified value to a new stack slot.
1000      // This could be made better, but would require substantial changes.
1001      duplicateToTop(SrcReg, DestReg, I);
1002    }
1003    }
1004    break;
1005  case TargetInstrInfo::INLINEASM: {
1006    // The inline asm MachineInstr currently only *uses* FP registers for the
1007    // 'f' constraint.  These should be turned into the current ST(x) register
1008    // in the machine instr.  Also, any kills should be explicitly popped after
1009    // the inline asm.
1010    unsigned Kills[7];
1011    unsigned NumKills = 0;
1012    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1013      MachineOperand &Op = MI->getOperand(i);
1014      if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1015        continue;
1016      assert(Op.isUse() && "Only handle inline asm uses right now");
1017
1018      unsigned FPReg = getFPReg(Op);
1019      Op.setReg(getSTReg(FPReg));
1020
1021      // If we kill this operand, make sure to pop it from the stack after the
1022      // asm.  We just remember it for now, and pop them all off at the end in
1023      // a batch.
1024      if (Op.isKill())
1025        Kills[NumKills++] = FPReg;
1026    }
1027
1028    // If this asm kills any FP registers (is the last use of them) we must
1029    // explicitly emit pop instructions for them.  Do this now after the asm has
1030    // executed so that the ST(x) numbers are not off (which would happen if we
1031    // did this inline with operand rewriting).
1032    //
1033    // Note: this might be a non-optimal pop sequence.  We might be able to do
1034    // better by trying to pop in stack order or something.
1035    MachineBasicBlock::iterator InsertPt = MI;
1036    while (NumKills)
1037      freeStackSlotAfter(InsertPt, Kills[--NumKills]);
1038
1039    // Don't delete the inline asm!
1040    return;
1041  }
1042
1043  case X86::RET:
1044  case X86::RETI:
1045    // If RET has an FP register use operand, pass the first one in ST(0) and
1046    // the second one in ST(1).
1047    if (isStackEmpty()) return;  // Quick check to see if any are possible.
1048
1049    // Find the register operands.
1050    unsigned FirstFPRegOp = ~0U, SecondFPRegOp = ~0U;
1051
1052    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1053      MachineOperand &Op = MI->getOperand(i);
1054      if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1055        continue;
1056//      assert(Op.isUse() && Op.isKill() &&
1057//             "Ret only defs operands, and values aren't live beyond it");
1058
1059      if (FirstFPRegOp == ~0U)
1060        FirstFPRegOp = getFPReg(Op);
1061      else {
1062        assert(SecondFPRegOp == ~0U && "More than two fp operands!");
1063        SecondFPRegOp = getFPReg(Op);
1064      }
1065
1066      // Remove the operand so that later passes don't see it.
1067      MI->RemoveOperand(i);
1068      --i, --e;
1069    }
1070
1071    // There are only four possibilities here:
1072    // 1) we are returning a single FP value.  In this case, it has to be in
1073    //    ST(0) already, so just declare success by removing the value from the
1074    //    FP Stack.
1075    if (SecondFPRegOp == ~0U) {
1076      // Assert that the top of stack contains the right FP register.
1077      assert(StackTop == 1 && FirstFPRegOp == getStackEntry(0) &&
1078             "Top of stack not the right register for RET!");
1079
1080      // Ok, everything is good, mark the value as not being on the stack
1081      // anymore so that our assertion about the stack being empty at end of
1082      // block doesn't fire.
1083      StackTop = 0;
1084      return;
1085    }
1086
1087    // Otherwise, we are returning two values:
1088    // 2) If returning the same value for both, we only have one thing in the FP
1089    //    stack.  Consider:  RET FP1, FP1
1090    if (StackTop == 1) {
1091      assert(FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry(0)&&
1092             "Stack misconfiguration for RET!");
1093
1094      // Duplicate the TOS so that we return it twice.  Just pick some other FPx
1095      // register to hold it.
1096      unsigned NewReg = (FirstFPRegOp+1)%7;
1097      duplicateToTop(FirstFPRegOp, NewReg, MI);
1098      FirstFPRegOp = NewReg;
1099    }
1100
1101    /// Okay we know we have two different FPx operands now:
1102    assert(StackTop == 2 && "Must have two values live!");
1103
1104    /// 3) If SecondFPRegOp is currently in ST(0) and FirstFPRegOp is currently
1105    ///    in ST(1).  In this case, emit an fxch.
1106    if (getStackEntry(0) == SecondFPRegOp) {
1107      assert(getStackEntry(1) == FirstFPRegOp && "Unknown regs live");
1108      moveToTop(FirstFPRegOp, MI);
1109    }
1110
1111    /// 4) Finally, FirstFPRegOp must be in ST(0) and SecondFPRegOp must be in
1112    /// ST(1).  Just remove both from our understanding of the stack and return.
1113    assert(getStackEntry(0) == FirstFPRegOp && "Unknown regs live");
1114    assert(getStackEntry(1) == SecondFPRegOp && "Unknown regs live");
1115    StackTop = 0;
1116    return;
1117  }
1118
1119  I = MBB->erase(I);  // Remove the pseudo instruction
1120  --I;
1121}
1122