X86FloatingPoint.cpp revision c1bab32bc56e6d27d1223431716523bbe35e4d2e
1//===-- FloatingPoint.cpp - Floating point Reg -> Stack converter ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the pass which converts floating point instructions from 11// virtual registers into register stack instructions. This pass uses live 12// variable information to indicate where the FPn registers are used and their 13// lifetimes. 14// 15// This pass is hampered by the lack of decent CFG manipulation routines for 16// machine code. In particular, this wants to be able to split critical edges 17// as necessary, traverse the machine basic block CFG in depth-first order, and 18// allow there to be multiple machine basic blocks for each LLVM basicblock 19// (needed for critical edge splitting). 20// 21// In particular, this pass currently barfs on critical edges. Because of this, 22// it requires the instruction selector to insert FP_REG_KILL instructions on 23// the exits of any basic block that has critical edges going from it, or which 24// branch to a critical basic block. 25// 26// FIXME: this is not implemented yet. The stackifier pass only works on local 27// basic blocks. 28// 29//===----------------------------------------------------------------------===// 30 31#define DEBUG_TYPE "fp" 32#include "X86.h" 33#include "X86InstrInfo.h" 34#include "llvm/CodeGen/MachineFunctionPass.h" 35#include "llvm/CodeGen/MachineInstrBuilder.h" 36#include "llvm/CodeGen/LiveVariables.h" 37#include "llvm/CodeGen/Passes.h" 38#include "llvm/Target/TargetInstrInfo.h" 39#include "llvm/Target/TargetMachine.h" 40#include "llvm/Function.h" // FIXME: remove when using MBB CFG! 41#include "llvm/Support/CFG.h" // FIXME: remove when using MBB CFG! 42#include "Support/Debug.h" 43#include "Support/DepthFirstIterator.h" 44#include "Support/Statistic.h" 45#include "Support/STLExtras.h" 46#include <algorithm> 47#include <set> 48using namespace llvm; 49 50namespace { 51 Statistic<> NumFXCH("x86-codegen", "Number of fxch instructions inserted"); 52 Statistic<> NumFP ("x86-codegen", "Number of floating point instructions"); 53 54 struct FPS : public MachineFunctionPass { 55 virtual bool runOnMachineFunction(MachineFunction &MF); 56 57 virtual const char *getPassName() const { return "X86 FP Stackifier"; } 58 59 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 60 AU.addRequired<LiveVariables>(); 61 MachineFunctionPass::getAnalysisUsage(AU); 62 } 63 private: 64 LiveVariables *LV; // Live variable info for current function... 65 MachineBasicBlock *MBB; // Current basic block 66 unsigned Stack[8]; // FP<n> Registers in each stack slot... 67 unsigned RegMap[8]; // Track which stack slot contains each register 68 unsigned StackTop; // The current top of the FP stack. 69 70 void dumpStack() const { 71 std::cerr << "Stack contents:"; 72 for (unsigned i = 0; i != StackTop; ++i) { 73 std::cerr << " FP" << Stack[i]; 74 assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!"); 75 } 76 std::cerr << "\n"; 77 } 78 private: 79 // getSlot - Return the stack slot number a particular register number is 80 // in... 81 unsigned getSlot(unsigned RegNo) const { 82 assert(RegNo < 8 && "Regno out of range!"); 83 return RegMap[RegNo]; 84 } 85 86 // getStackEntry - Return the X86::FP<n> register in register ST(i) 87 unsigned getStackEntry(unsigned STi) const { 88 assert(STi < StackTop && "Access past stack top!"); 89 return Stack[StackTop-1-STi]; 90 } 91 92 // getSTReg - Return the X86::ST(i) register which contains the specified 93 // FP<RegNo> register 94 unsigned getSTReg(unsigned RegNo) const { 95 return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0; 96 } 97 98 // pushReg - Push the specified FP<n> register onto the stack 99 void pushReg(unsigned Reg) { 100 assert(Reg < 8 && "Register number out of range!"); 101 assert(StackTop < 8 && "Stack overflow!"); 102 Stack[StackTop] = Reg; 103 RegMap[Reg] = StackTop++; 104 } 105 106 bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; } 107 void moveToTop(unsigned RegNo, MachineBasicBlock::iterator &I) { 108 if (!isAtTop(RegNo)) { 109 unsigned Slot = getSlot(RegNo); 110 unsigned STReg = getSTReg(RegNo); 111 unsigned RegOnTop = getStackEntry(0); 112 113 // Swap the slots the regs are in 114 std::swap(RegMap[RegNo], RegMap[RegOnTop]); 115 116 // Swap stack slot contents 117 assert(RegMap[RegOnTop] < StackTop); 118 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]); 119 120 // Emit an fxch to update the runtime processors version of the state 121 MachineInstr *MI = BuildMI(X86::FXCH, 1).addReg(STReg); 122 MBB->insert(I, MI); 123 NumFXCH++; 124 } 125 } 126 127 void duplicateToTop(unsigned RegNo, unsigned AsReg, 128 MachineBasicBlock::iterator &I) { 129 unsigned STReg = getSTReg(RegNo); 130 pushReg(AsReg); // New register on top of stack 131 132 MachineInstr *MI = BuildMI(X86::FLDrr, 1).addReg(STReg); 133 MBB->insert(I, MI); 134 } 135 136 // popStackAfter - Pop the current value off of the top of the FP stack 137 // after the specified instruction. 138 void popStackAfter(MachineBasicBlock::iterator &I); 139 140 bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB); 141 142 void handleZeroArgFP(MachineBasicBlock::iterator &I); 143 void handleOneArgFP(MachineBasicBlock::iterator &I); 144 void handleOneArgFPRW(MachineBasicBlock::iterator &I); 145 void handleTwoArgFP(MachineBasicBlock::iterator &I); 146 void handleCondMovFP(MachineBasicBlock::iterator &I); 147 void handleSpecialFP(MachineBasicBlock::iterator &I); 148 }; 149} 150 151FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); } 152 153/// runOnMachineFunction - Loop over all of the basic blocks, transforming FP 154/// register references into FP stack references. 155/// 156bool FPS::runOnMachineFunction(MachineFunction &MF) { 157 LV = &getAnalysis<LiveVariables>(); 158 StackTop = 0; 159 160 // Figure out the mapping of MBB's to BB's. 161 // 162 // FIXME: Eventually we should be able to traverse the MBB CFG directly, and 163 // we will need to extend this when one llvm basic block can codegen to 164 // multiple MBBs. 165 // 166 // FIXME again: Just use the mapping established by LiveVariables! 167 // 168 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap; 169 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) 170 MBBMap[I->getBasicBlock()] = I; 171 172 // Process the function in depth first order so that we process at least one 173 // of the predecessors for every reachable block in the function. 174 std::set<const BasicBlock*> Processed; 175 const BasicBlock *Entry = MF.getFunction()->begin(); 176 177 bool Changed = false; 178 for (df_ext_iterator<const BasicBlock*, std::set<const BasicBlock*> > 179 I = df_ext_begin(Entry, Processed), E = df_ext_end(Entry, Processed); 180 I != E; ++I) 181 Changed |= processBasicBlock(MF, *MBBMap[*I]); 182 183 assert(MBBMap.size() == Processed.size() && 184 "Doesn't handle unreachable code yet!"); 185 186 return Changed; 187} 188 189/// processBasicBlock - Loop over all of the instructions in the basic block, 190/// transforming FP instructions into their stack form. 191/// 192bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) { 193 const TargetInstrInfo &TII = MF.getTarget().getInstrInfo(); 194 bool Changed = false; 195 MBB = &BB; 196 197 for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) { 198 MachineInstr *MI = I; 199 unsigned Flags = TII.get(MI->getOpcode()).TSFlags; 200 if ((Flags & X86II::FPTypeMask) == X86II::NotFP) 201 continue; // Efficiently ignore non-fp insts! 202 203 MachineInstr *PrevMI = 0; 204 if (I != BB.begin()) 205 PrevMI = prior(I); 206 207 ++NumFP; // Keep track of # of pseudo instrs 208 DEBUG(std::cerr << "\nFPInst:\t"; 209 MI->print(std::cerr, MF.getTarget())); 210 211 // Get dead variables list now because the MI pointer may be deleted as part 212 // of processing! 213 LiveVariables::killed_iterator IB = LV->dead_begin(MI); 214 LiveVariables::killed_iterator IE = LV->dead_end(MI); 215 216 DEBUG(const MRegisterInfo *MRI = MF.getTarget().getRegisterInfo(); 217 LiveVariables::killed_iterator I = LV->killed_begin(MI); 218 LiveVariables::killed_iterator E = LV->killed_end(MI); 219 if (I != E) { 220 std::cerr << "Killed Operands:"; 221 for (; I != E; ++I) 222 std::cerr << " %" << MRI->getName(I->second); 223 std::cerr << "\n"; 224 }); 225 226 switch (Flags & X86II::FPTypeMask) { 227 case X86II::ZeroArgFP: handleZeroArgFP(I); break; 228 case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0) 229 case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0)) 230 case X86II::TwoArgFP: handleTwoArgFP(I); break; 231 case X86II::CondMovFP: handleCondMovFP(I); break; 232 case X86II::SpecialFP: handleSpecialFP(I); break; 233 default: assert(0 && "Unknown FP Type!"); 234 } 235 236 // Check to see if any of the values defined by this instruction are dead 237 // after definition. If so, pop them. 238 for (; IB != IE; ++IB) { 239 unsigned Reg = IB->second; 240 if (Reg >= X86::FP0 && Reg <= X86::FP6) { 241 DEBUG(std::cerr << "Register FP#" << Reg-X86::FP0 << " is dead!\n"); 242 ++I; // Insert fxch AFTER the instruction 243 moveToTop(Reg-X86::FP0, I); // Insert fxch if necessary 244 --I; // Move to fxch or old instruction 245 popStackAfter(I); // Pop the top of the stack, killing value 246 } 247 } 248 249 // Print out all of the instructions expanded to if -debug 250 DEBUG( 251 MachineBasicBlock::iterator PrevI(PrevMI); 252 if (I == PrevI) { 253 std::cerr<< "Just deleted pseudo instruction\n"; 254 } else { 255 MachineBasicBlock::iterator Start = I; 256 // Rewind to first instruction newly inserted. 257 while (Start != BB.begin() && prior(Start) != PrevI) --Start; 258 std::cerr << "Inserted instructions:\n\t"; 259 Start->print(std::cerr, MF.getTarget()); 260 while (++Start != next(I)); 261 } 262 dumpStack(); 263 ); 264 265 Changed = true; 266 } 267 268 assert(StackTop == 0 && "Stack not empty at end of basic block?"); 269 return Changed; 270} 271 272//===----------------------------------------------------------------------===// 273// Efficient Lookup Table Support 274//===----------------------------------------------------------------------===// 275 276namespace { 277 struct TableEntry { 278 unsigned from; 279 unsigned to; 280 bool operator<(const TableEntry &TE) const { return from < TE.from; } 281 bool operator<(unsigned V) const { return from < V; } 282 }; 283} 284 285static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) { 286 for (unsigned i = 0; i != NumEntries-1; ++i) 287 if (!(Table[i] < Table[i+1])) return false; 288 return true; 289} 290 291static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) { 292 const TableEntry *I = std::lower_bound(Table, Table+N, Opcode); 293 if (I != Table+N && I->from == Opcode) 294 return I->to; 295 return -1; 296} 297 298#define ARRAY_SIZE(TABLE) \ 299 (sizeof(TABLE)/sizeof(TABLE[0])) 300 301#ifdef NDEBUG 302#define ASSERT_SORTED(TABLE) 303#else 304#define ASSERT_SORTED(TABLE) \ 305 { static bool TABLE##Checked = false; \ 306 if (!TABLE##Checked) \ 307 assert(TableIsSorted(TABLE, ARRAY_SIZE(TABLE)) && \ 308 "All lookup tables must be sorted for efficient access!"); \ 309 } 310#endif 311 312 313//===----------------------------------------------------------------------===// 314// Helper Methods 315//===----------------------------------------------------------------------===// 316 317// PopTable - Sorted map of instructions to their popping version. The first 318// element is an instruction, the second is the version which pops. 319// 320static const TableEntry PopTable[] = { 321 { X86::FADDrST0 , X86::FADDPrST0 }, 322 323 { X86::FDIVRrST0, X86::FDIVRPrST0 }, 324 { X86::FDIVrST0 , X86::FDIVPrST0 }, 325 326 { X86::FIST16m , X86::FISTP16m }, 327 { X86::FIST32m , X86::FISTP32m }, 328 329 { X86::FMULrST0 , X86::FMULPrST0 }, 330 331 { X86::FST32m , X86::FSTP32m }, 332 { X86::FST64m , X86::FSTP64m }, 333 { X86::FSTrr , X86::FSTPrr }, 334 335 { X86::FSUBRrST0, X86::FSUBRPrST0 }, 336 { X86::FSUBrST0 , X86::FSUBPrST0 }, 337 338 { X86::FUCOMPr , X86::FUCOMPPr }, 339 { X86::FUCOMr , X86::FUCOMPr }, 340}; 341 342/// popStackAfter - Pop the current value off of the top of the FP stack after 343/// the specified instruction. This attempts to be sneaky and combine the pop 344/// into the instruction itself if possible. The iterator is left pointing to 345/// the last instruction, be it a new pop instruction inserted, or the old 346/// instruction if it was modified in place. 347/// 348void FPS::popStackAfter(MachineBasicBlock::iterator &I) { 349 ASSERT_SORTED(PopTable); 350 assert(StackTop > 0 && "Cannot pop empty stack!"); 351 RegMap[Stack[--StackTop]] = ~0; // Update state 352 353 // Check to see if there is a popping version of this instruction... 354 int Opcode = Lookup(PopTable, ARRAY_SIZE(PopTable), I->getOpcode()); 355 if (Opcode != -1) { 356 I->setOpcode(Opcode); 357 if (Opcode == X86::FUCOMPPr) 358 I->RemoveOperand(0); 359 360 } else { // Insert an explicit pop 361 MachineInstr *MI = BuildMI(X86::FSTPrr, 1).addReg(X86::ST0); 362 I = MBB->insert(++I, MI); 363 } 364} 365 366static unsigned getFPReg(const MachineOperand &MO) { 367 assert(MO.isRegister() && "Expected an FP register!"); 368 unsigned Reg = MO.getReg(); 369 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!"); 370 return Reg - X86::FP0; 371} 372 373 374//===----------------------------------------------------------------------===// 375// Instruction transformation implementation 376//===----------------------------------------------------------------------===// 377 378/// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem> 379/// 380void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) { 381 MachineInstr *MI = I; 382 unsigned DestReg = getFPReg(MI->getOperand(0)); 383 MI->RemoveOperand(0); // Remove the explicit ST(0) operand 384 385 // Result gets pushed on the stack... 386 pushReg(DestReg); 387} 388 389/// handleOneArgFP - fst <mem>, ST(0) 390/// 391void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) { 392 MachineInstr *MI = I; 393 assert((MI->getNumOperands() == 5 || MI->getNumOperands() == 1) && 394 "Can only handle fst* & ftst instructions!"); 395 396 // Is this the last use of the source register? 397 unsigned Reg = getFPReg(MI->getOperand(MI->getNumOperands()-1)); 398 bool KillsSrc = false; 399 for (LiveVariables::killed_iterator KI = LV->killed_begin(MI), 400 E = LV->killed_end(MI); KI != E; ++KI) 401 KillsSrc |= KI->second == X86::FP0+Reg; 402 403 // FSTP80r and FISTP64r are strange because there are no non-popping versions. 404 // If we have one _and_ we don't want to pop the operand, duplicate the value 405 // on the stack instead of moving it. This ensure that popping the value is 406 // always ok. 407 // 408 if ((MI->getOpcode() == X86::FSTP80m || 409 MI->getOpcode() == X86::FISTP64m) && !KillsSrc) { 410 duplicateToTop(Reg, 7 /*temp register*/, I); 411 } else { 412 moveToTop(Reg, I); // Move to the top of the stack... 413 } 414 MI->RemoveOperand(MI->getNumOperands()-1); // Remove explicit ST(0) operand 415 416 if (MI->getOpcode() == X86::FSTP80m || MI->getOpcode() == X86::FISTP64m) { 417 assert(StackTop > 0 && "Stack empty??"); 418 --StackTop; 419 } else if (KillsSrc) { // Last use of operand? 420 popStackAfter(I); 421 } 422} 423 424 425/// handleOneArgFPRW - fchs - ST(0) = -ST(0) 426/// 427void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) { 428 MachineInstr *MI = I; 429 assert(MI->getNumOperands() == 2 && "Can only handle fst* instructions!"); 430 431 // Is this the last use of the source register? 432 unsigned Reg = getFPReg(MI->getOperand(1)); 433 bool KillsSrc = false; 434 for (LiveVariables::killed_iterator KI = LV->killed_begin(MI), 435 E = LV->killed_end(MI); KI != E; ++KI) 436 KillsSrc |= KI->second == X86::FP0+Reg; 437 438 if (KillsSrc) { 439 // If this is the last use of the source register, just make sure it's on 440 // the top of the stack. 441 moveToTop(Reg, I); 442 assert(StackTop > 0 && "Stack cannot be empty!"); 443 --StackTop; 444 pushReg(getFPReg(MI->getOperand(0))); 445 } else { 446 // If this is not the last use of the source register, _copy_ it to the top 447 // of the stack. 448 duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I); 449 } 450 451 MI->RemoveOperand(1); // Drop the source operand. 452 MI->RemoveOperand(0); // Drop the destination operand. 453} 454 455 456//===----------------------------------------------------------------------===// 457// Define tables of various ways to map pseudo instructions 458// 459 460// ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i) 461static const TableEntry ForwardST0Table[] = { 462 { X86::FpADD, X86::FADDST0r }, 463 { X86::FpDIV, X86::FDIVST0r }, 464 { X86::FpMUL, X86::FMULST0r }, 465 { X86::FpSUB, X86::FSUBST0r }, 466 { X86::FpUCOM, X86::FUCOMr }, 467}; 468 469// ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0) 470static const TableEntry ReverseST0Table[] = { 471 { X86::FpADD, X86::FADDST0r }, // commutative 472 { X86::FpDIV, X86::FDIVRST0r }, 473 { X86::FpMUL, X86::FMULST0r }, // commutative 474 { X86::FpSUB, X86::FSUBRST0r }, 475 { X86::FpUCOM, ~0 }, 476}; 477 478// ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i) 479static const TableEntry ForwardSTiTable[] = { 480 { X86::FpADD, X86::FADDrST0 }, // commutative 481 { X86::FpDIV, X86::FDIVRrST0 }, 482 { X86::FpMUL, X86::FMULrST0 }, // commutative 483 { X86::FpSUB, X86::FSUBRrST0 }, 484 { X86::FpUCOM, X86::FUCOMr }, 485}; 486 487// ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0) 488static const TableEntry ReverseSTiTable[] = { 489 { X86::FpADD, X86::FADDrST0 }, 490 { X86::FpDIV, X86::FDIVrST0 }, 491 { X86::FpMUL, X86::FMULrST0 }, 492 { X86::FpSUB, X86::FSUBrST0 }, 493 { X86::FpUCOM, ~0 }, 494}; 495 496 497/// handleTwoArgFP - Handle instructions like FADD and friends which are virtual 498/// instructions which need to be simplified and possibly transformed. 499/// 500/// Result: ST(0) = fsub ST(0), ST(i) 501/// ST(i) = fsub ST(0), ST(i) 502/// ST(0) = fsubr ST(0), ST(i) 503/// ST(i) = fsubr ST(0), ST(i) 504/// 505/// In addition to three address instructions, this also handles the FpUCOM 506/// instruction which only has two operands, but no destination. This 507/// instruction is also annoying because there is no "reverse" form of it 508/// available. 509/// 510void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) { 511 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table); 512 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable); 513 MachineInstr *MI = I; 514 515 unsigned NumOperands = MI->getNumOperands(); 516 assert(NumOperands == 3 || 517 (NumOperands == 2 && MI->getOpcode() == X86::FpUCOM) && 518 "Illegal TwoArgFP instruction!"); 519 unsigned Dest = getFPReg(MI->getOperand(0)); 520 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2)); 521 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1)); 522 bool KillsOp0 = false, KillsOp1 = false; 523 524 for (LiveVariables::killed_iterator KI = LV->killed_begin(MI), 525 E = LV->killed_end(MI); KI != E; ++KI) { 526 KillsOp0 |= (KI->second == X86::FP0+Op0); 527 KillsOp1 |= (KI->second == X86::FP0+Op1); 528 } 529 530 // If this is an FpUCOM instruction, we must make sure the first operand is on 531 // the top of stack, the other one can be anywhere... 532 if (MI->getOpcode() == X86::FpUCOM) 533 moveToTop(Op0, I); 534 535 unsigned TOS = getStackEntry(0); 536 537 // One of our operands must be on the top of the stack. If neither is yet, we 538 // need to move one. 539 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS? 540 // We can choose to move either operand to the top of the stack. If one of 541 // the operands is killed by this instruction, we want that one so that we 542 // can update right on top of the old version. 543 if (KillsOp0) { 544 moveToTop(Op0, I); // Move dead operand to TOS. 545 TOS = Op0; 546 } else if (KillsOp1) { 547 moveToTop(Op1, I); 548 TOS = Op1; 549 } else { 550 // All of the operands are live after this instruction executes, so we 551 // cannot update on top of any operand. Because of this, we must 552 // duplicate one of the stack elements to the top. It doesn't matter 553 // which one we pick. 554 // 555 duplicateToTop(Op0, Dest, I); 556 Op0 = TOS = Dest; 557 KillsOp0 = true; 558 } 559 } else if (!KillsOp0 && !KillsOp1 && MI->getOpcode() != X86::FpUCOM) { 560 // If we DO have one of our operands at the top of the stack, but we don't 561 // have a dead operand, we must duplicate one of the operands to a new slot 562 // on the stack. 563 duplicateToTop(Op0, Dest, I); 564 Op0 = TOS = Dest; 565 KillsOp0 = true; 566 } 567 568 // Now we know that one of our operands is on the top of the stack, and at 569 // least one of our operands is killed by this instruction. 570 assert((TOS == Op0 || TOS == Op1) && 571 (KillsOp0 || KillsOp1 || MI->getOpcode() == X86::FpUCOM) && 572 "Stack conditions not set up right!"); 573 574 // We decide which form to use based on what is on the top of the stack, and 575 // which operand is killed by this instruction. 576 const TableEntry *InstTable; 577 bool isForward = TOS == Op0; 578 bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0); 579 if (updateST0) { 580 if (isForward) 581 InstTable = ForwardST0Table; 582 else 583 InstTable = ReverseST0Table; 584 } else { 585 if (isForward) 586 InstTable = ForwardSTiTable; 587 else 588 InstTable = ReverseSTiTable; 589 } 590 591 int Opcode = Lookup(InstTable, ARRAY_SIZE(ForwardST0Table), MI->getOpcode()); 592 assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!"); 593 594 // NotTOS - The register which is not on the top of stack... 595 unsigned NotTOS = (TOS == Op0) ? Op1 : Op0; 596 597 // Replace the old instruction with a new instruction 598 MBB->remove(I++); 599 BuildMI(*MBB, I, Opcode, 1).addReg(getSTReg(NotTOS)); 600 --I; 601 602 // If both operands are killed, pop one off of the stack in addition to 603 // overwriting the other one. 604 if (KillsOp0 && KillsOp1 && Op0 != Op1) { 605 assert(!updateST0 && "Should have updated other operand!"); 606 popStackAfter(I); // Pop the top of stack 607 } 608 609 // Insert an explicit pop of the "updated" operand for FUCOM 610 if (MI->getOpcode() == X86::FpUCOM) { 611 if (KillsOp0 && !KillsOp1) 612 popStackAfter(I); // If we kill the first operand, pop it! 613 else if (KillsOp1 && Op0 != Op1) { 614 if (getStackEntry(0) == Op1) { 615 popStackAfter(I); // If it's right at the top of stack, just pop it 616 } else { 617 // Otherwise, move the top of stack into the dead slot, killing the 618 // operand without having to add in an explicit xchg then pop. 619 // 620 unsigned STReg = getSTReg(Op1); 621 unsigned OldSlot = getSlot(Op1); 622 unsigned TopReg = Stack[StackTop-1]; 623 Stack[OldSlot] = TopReg; 624 RegMap[TopReg] = OldSlot; 625 RegMap[Op1] = ~0; 626 Stack[--StackTop] = ~0; 627 628 MachineInstr *MI = BuildMI(X86::FSTPrr, 1).addReg(STReg); 629 I = MBB->insert(++I, MI); 630 } 631 } 632 } 633 634 // Update stack information so that we know the destination register is now on 635 // the stack. 636 if (MI->getOpcode() != X86::FpUCOM) { 637 unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS); 638 assert(UpdatedSlot < StackTop && Dest < 7); 639 Stack[UpdatedSlot] = Dest; 640 RegMap[Dest] = UpdatedSlot; 641 } 642 delete MI; // Remove the old instruction 643} 644 645/// handleCondMovFP - Handle two address conditional move instructions. These 646/// instructions move a st(i) register to st(0) iff a condition is true. These 647/// instructions require that the first operand is at the top of the stack, but 648/// otherwise don't modify the stack at all. 649void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) { 650 MachineInstr *MI = I; 651 652 unsigned Op0 = getFPReg(MI->getOperand(0)); 653 unsigned Op1 = getFPReg(MI->getOperand(1)); 654 655 // The first operand *must* be on the top of the stack. 656 moveToTop(Op0, I); 657 658 // Change the second operand to the stack register that the operand is in. 659 MI->RemoveOperand(0); 660 MI->getOperand(0).setReg(getSTReg(Op1)); 661 662 // If we kill the second operand, make sure to pop it from the stack. 663 for (LiveVariables::killed_iterator KI = LV->killed_begin(MI), 664 E = LV->killed_end(MI); KI != E; ++KI) 665 if (KI->second == X86::FP0+Op1) { 666 ++I; 667 moveToTop(Op1, I); // Insert fxch if necessary 668 --I; 669 popStackAfter(I); // Pop the top of the stack, killing value 670 break; 671 } 672} 673 674 675/// handleSpecialFP - Handle special instructions which behave unlike other 676/// floating point instructions. This is primarily intended for use by pseudo 677/// instructions. 678/// 679void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) { 680 MachineInstr *MI = I; 681 switch (MI->getOpcode()) { 682 default: assert(0 && "Unknown SpecialFP instruction!"); 683 case X86::FpGETRESULT: // Appears immediately after a call returning FP type! 684 assert(StackTop == 0 && "Stack should be empty after a call!"); 685 pushReg(getFPReg(MI->getOperand(0))); 686 break; 687 case X86::FpSETRESULT: 688 assert(StackTop == 1 && "Stack should have one element on it to return!"); 689 --StackTop; // "Forget" we have something on the top of stack! 690 break; 691 case X86::FpMOV: { 692 unsigned SrcReg = getFPReg(MI->getOperand(1)); 693 unsigned DestReg = getFPReg(MI->getOperand(0)); 694 bool KillsSrc = false; 695 for (LiveVariables::killed_iterator KI = LV->killed_begin(MI), 696 E = LV->killed_end(MI); KI != E; ++KI) 697 KillsSrc |= KI->second == X86::FP0+SrcReg; 698 699 if (KillsSrc) { 700 // If the input operand is killed, we can just change the owner of the 701 // incoming stack slot into the result. 702 unsigned Slot = getSlot(SrcReg); 703 assert(Slot < 7 && DestReg < 7 && "FpMOV operands invalid!"); 704 Stack[Slot] = DestReg; 705 RegMap[DestReg] = Slot; 706 707 } else { 708 // For FMOV we just duplicate the specified value to a new stack slot. 709 // This could be made better, but would require substantial changes. 710 duplicateToTop(SrcReg, DestReg, I); 711 } 712 break; 713 } 714 } 715 716 I = MBB->erase(I); // Remove the pseudo instruction 717 --I; 718} 719