X86FloatingPoint.cpp revision c23197a26f34f559ea9797de51e187087c039c42 
1//===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the pass which converts floating point instructions from
11// virtual registers into register stack instructions.  This pass uses live
12// variable information to indicate where the FPn registers are used and their
13// lifetimes.
14//
15// This pass is hampered by the lack of decent CFG manipulation routines for
16// machine code.  In particular, this wants to be able to split critical edges
17// as necessary, traverse the machine basic block CFG in depth-first order, and
18// allow there to be multiple machine basic blocks for each LLVM basicblock
19// (needed for critical edge splitting).
20//
21// In particular, this pass currently barfs on critical edges.  Because of this,
22// it requires the instruction selector to insert FP_REG_KILL instructions on
23// the exits of any basic block that has critical edges going from it, or which
24// branch to a critical basic block.
25//
26// FIXME: this is not implemented yet.  The stackifier pass only works on local
27// basic blocks.
28//
29//===----------------------------------------------------------------------===//
30
31#define DEBUG_TYPE "x86-codegen"
32#include "X86.h"
33#include "X86InstrInfo.h"
34#include "llvm/CodeGen/MachineFunctionPass.h"
35#include "llvm/CodeGen/MachineInstrBuilder.h"
36#include "llvm/CodeGen/MachineRegisterInfo.h"
37#include "llvm/CodeGen/Passes.h"
38#include "llvm/Target/TargetInstrInfo.h"
39#include "llvm/Target/TargetMachine.h"
40#include "llvm/Support/Debug.h"
41#include "llvm/Support/ErrorHandling.h"
42#include "llvm/Support/Compiler.h"
43#include "llvm/ADT/DepthFirstIterator.h"
44#include "llvm/ADT/SmallPtrSet.h"
45#include "llvm/ADT/SmallVector.h"
46#include "llvm/ADT/Statistic.h"
47#include "llvm/ADT/STLExtras.h"
48#include <algorithm>
49using namespace llvm;
50
51STATISTIC(NumFXCH, "Number of fxch instructions inserted");
52STATISTIC(NumFP  , "Number of floating point instructions");
53
54namespace {
55  struct VISIBILITY_HIDDEN FPS : public MachineFunctionPass {
56    static char ID;
57    FPS() : MachineFunctionPass(&ID) {}
58
59    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
60      AU.addPreservedID(MachineLoopInfoID);
61      AU.addPreservedID(MachineDominatorsID);
62      MachineFunctionPass::getAnalysisUsage(AU);
63    }
64
65    virtual bool runOnMachineFunction(MachineFunction &MF);
66
67    virtual const char *getPassName() const { return "X86 FP Stackifier"; }
68
69  private:
70    const TargetInstrInfo *TII; // Machine instruction info.
71    MachineBasicBlock *MBB;     // Current basic block
72    unsigned Stack[8];          // FP<n> Registers in each stack slot...
73    unsigned RegMap[8];         // Track which stack slot contains each register
74    unsigned StackTop;          // The current top of the FP stack.
75
76    void dumpStack() const {
77      cerr << "Stack contents:";
78      for (unsigned i = 0; i != StackTop; ++i) {
79        cerr << " FP" << Stack[i];
80        assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
81      }
82      cerr << "\n";
83    }
84  private:
85    /// isStackEmpty - Return true if the FP stack is empty.
86    bool isStackEmpty() const {
87      return StackTop == 0;
88    }
89
90    // getSlot - Return the stack slot number a particular register number is
91    // in.
92    unsigned getSlot(unsigned RegNo) const {
93      assert(RegNo < 8 && "Regno out of range!");
94      return RegMap[RegNo];
95    }
96
97    // getStackEntry - Return the X86::FP<n> register in register ST(i).
98    unsigned getStackEntry(unsigned STi) const {
99      assert(STi < StackTop && "Access past stack top!");
100      return Stack[StackTop-1-STi];
101    }
102
103    // getSTReg - Return the X86::ST(i) register which contains the specified
104    // FP<RegNo> register.
105    unsigned getSTReg(unsigned RegNo) const {
106      return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0;
107    }
108
109    // pushReg - Push the specified FP<n> register onto the stack.
110    void pushReg(unsigned Reg) {
111      assert(Reg < 8 && "Register number out of range!");
112      assert(StackTop < 8 && "Stack overflow!");
113      Stack[StackTop] = Reg;
114      RegMap[Reg] = StackTop++;
115    }
116
117    bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
118    void moveToTop(unsigned RegNo, MachineBasicBlock::iterator I) {
119      MachineInstr *MI = I;
120      DebugLoc dl = MI->getDebugLoc();
121      if (isAtTop(RegNo)) return;
122
123      unsigned STReg = getSTReg(RegNo);
124      unsigned RegOnTop = getStackEntry(0);
125
126      // Swap the slots the regs are in.
127      std::swap(RegMap[RegNo], RegMap[RegOnTop]);
128
129      // Swap stack slot contents.
130      assert(RegMap[RegOnTop] < StackTop);
131      std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
132
133      // Emit an fxch to update the runtime processors version of the state.
134      BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg);
135      NumFXCH++;
136    }
137
138    void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) {
139      DebugLoc dl = I->getDebugLoc();
140      unsigned STReg = getSTReg(RegNo);
141      pushReg(AsReg);   // New register on top of stack
142
143      BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg);
144    }
145
146    // popStackAfter - Pop the current value off of the top of the FP stack
147    // after the specified instruction.
148    void popStackAfter(MachineBasicBlock::iterator &I);
149
150    // freeStackSlotAfter - Free the specified register from the register stack,
151    // so that it is no longer in a register.  If the register is currently at
152    // the top of the stack, we just pop the current instruction, otherwise we
153    // store the current top-of-stack into the specified slot, then pop the top
154    // of stack.
155    void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
156
157    bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
158
159    void handleZeroArgFP(MachineBasicBlock::iterator &I);
160    void handleOneArgFP(MachineBasicBlock::iterator &I);
161    void handleOneArgFPRW(MachineBasicBlock::iterator &I);
162    void handleTwoArgFP(MachineBasicBlock::iterator &I);
163    void handleCompareFP(MachineBasicBlock::iterator &I);
164    void handleCondMovFP(MachineBasicBlock::iterator &I);
165    void handleSpecialFP(MachineBasicBlock::iterator &I);
166  };
167  char FPS::ID = 0;
168}
169
170FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); }
171
172/// getFPReg - Return the X86::FPx register number for the specified operand.
173/// For example, this returns 3 for X86::FP3.
174static unsigned getFPReg(const MachineOperand &MO) {
175  assert(MO.isReg() && "Expected an FP register!");
176  unsigned Reg = MO.getReg();
177  assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
178  return Reg - X86::FP0;
179}
180
181
182/// runOnMachineFunction - Loop over all of the basic blocks, transforming FP
183/// register references into FP stack references.
184///
185bool FPS::runOnMachineFunction(MachineFunction &MF) {
186  // We only need to run this pass if there are any FP registers used in this
187  // function.  If it is all integer, there is nothing for us to do!
188  bool FPIsUsed = false;
189
190  assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!");
191  for (unsigned i = 0; i <= 6; ++i)
192    if (MF.getRegInfo().isPhysRegUsed(X86::FP0+i)) {
193      FPIsUsed = true;
194      break;
195    }
196
197  // Early exit.
198  if (!FPIsUsed) return false;
199
200  TII = MF.getTarget().getInstrInfo();
201  StackTop = 0;
202
203  // Process the function in depth first order so that we process at least one
204  // of the predecessors for every reachable block in the function.
205  SmallPtrSet<MachineBasicBlock*, 8> Processed;
206  MachineBasicBlock *Entry = MF.begin();
207
208  bool Changed = false;
209  for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*, 8> >
210         I = df_ext_begin(Entry, Processed), E = df_ext_end(Entry, Processed);
211       I != E; ++I)
212    Changed |= processBasicBlock(MF, **I);
213
214  return Changed;
215}
216
217/// processBasicBlock - Loop over all of the instructions in the basic block,
218/// transforming FP instructions into their stack form.
219///
220bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
221  bool Changed = false;
222  MBB = &BB;
223
224  for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
225    MachineInstr *MI = I;
226    unsigned Flags = MI->getDesc().TSFlags;
227
228    unsigned FPInstClass = Flags & X86II::FPTypeMask;
229    if (MI->getOpcode() == TargetInstrInfo::INLINEASM)
230      FPInstClass = X86II::SpecialFP;
231
232    if (FPInstClass == X86II::NotFP)
233      continue;  // Efficiently ignore non-fp insts!
234
235    MachineInstr *PrevMI = 0;
236    if (I != BB.begin())
237      PrevMI = prior(I);
238
239    ++NumFP;  // Keep track of # of pseudo instrs
240    DOUT << "\nFPInst:\t" << *MI;
241
242    // Get dead variables list now because the MI pointer may be deleted as part
243    // of processing!
244    SmallVector<unsigned, 8> DeadRegs;
245    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
246      const MachineOperand &MO = MI->getOperand(i);
247      if (MO.isReg() && MO.isDead())
248        DeadRegs.push_back(MO.getReg());
249    }
250
251    switch (FPInstClass) {
252    case X86II::ZeroArgFP:  handleZeroArgFP(I); break;
253    case X86II::OneArgFP:   handleOneArgFP(I);  break;  // fstp ST(0)
254    case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0))
255    case X86II::TwoArgFP:   handleTwoArgFP(I);  break;
256    case X86II::CompareFP:  handleCompareFP(I); break;
257    case X86II::CondMovFP:  handleCondMovFP(I); break;
258    case X86II::SpecialFP:  handleSpecialFP(I); break;
259    default: llvm_unreachable("Unknown FP Type!");
260    }
261
262    // Check to see if any of the values defined by this instruction are dead
263    // after definition.  If so, pop them.
264    for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
265      unsigned Reg = DeadRegs[i];
266      if (Reg >= X86::FP0 && Reg <= X86::FP6) {
267        DOUT << "Register FP#" << Reg-X86::FP0 << " is dead!\n";
268        freeStackSlotAfter(I, Reg-X86::FP0);
269      }
270    }
271
272    // Print out all of the instructions expanded to if -debug
273    DEBUG(
274      MachineBasicBlock::iterator PrevI(PrevMI);
275      if (I == PrevI) {
276        cerr << "Just deleted pseudo instruction\n";
277      } else {
278        MachineBasicBlock::iterator Start = I;
279        // Rewind to first instruction newly inserted.
280        while (Start != BB.begin() && prior(Start) != PrevI) --Start;
281        cerr << "Inserted instructions:\n\t";
282        Start->print(*cerr.stream(), &MF.getTarget());
283        while (++Start != next(I)) {}
284      }
285      dumpStack();
286    );
287
288    Changed = true;
289  }
290
291  assert(isStackEmpty() && "Stack not empty at end of basic block?");
292  return Changed;
293}
294
295//===----------------------------------------------------------------------===//
296// Efficient Lookup Table Support
297//===----------------------------------------------------------------------===//
298
299namespace {
300  struct TableEntry {
301    unsigned from;
302    unsigned to;
303    bool operator<(const TableEntry &TE) const { return from < TE.from; }
304    friend bool operator<(const TableEntry &TE, unsigned V) {
305      return TE.from < V;
306    }
307    friend bool operator<(unsigned V, const TableEntry &TE) {
308      return V < TE.from;
309    }
310  };
311}
312
313#ifndef NDEBUG
314static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
315  for (unsigned i = 0; i != NumEntries-1; ++i)
316    if (!(Table[i] < Table[i+1])) return false;
317  return true;
318}
319#endif
320
321static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) {
322  const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
323  if (I != Table+N && I->from == Opcode)
324    return I->to;
325  return -1;
326}
327
328#ifdef NDEBUG
329#define ASSERT_SORTED(TABLE)
330#else
331#define ASSERT_SORTED(TABLE)                                              \
332  { static bool TABLE##Checked = false;                                   \
333    if (!TABLE##Checked) {                                                \
334       assert(TableIsSorted(TABLE, array_lengthof(TABLE)) &&              \
335              "All lookup tables must be sorted for efficient access!");  \
336       TABLE##Checked = true;                                             \
337    }                                                                     \
338  }
339#endif
340
341//===----------------------------------------------------------------------===//
342// Register File -> Register Stack Mapping Methods
343//===----------------------------------------------------------------------===//
344
345// OpcodeTable - Sorted map of register instructions to their stack version.
346// The first element is an register file pseudo instruction, the second is the
347// concrete X86 instruction which uses the register stack.
348//
349static const TableEntry OpcodeTable[] = {
350  { X86::ABS_Fp32     , X86::ABS_F     },
351  { X86::ABS_Fp64     , X86::ABS_F     },
352  { X86::ABS_Fp80     , X86::ABS_F     },
353  { X86::ADD_Fp32m    , X86::ADD_F32m  },
354  { X86::ADD_Fp64m    , X86::ADD_F64m  },
355  { X86::ADD_Fp64m32  , X86::ADD_F32m  },
356  { X86::ADD_Fp80m32  , X86::ADD_F32m  },
357  { X86::ADD_Fp80m64  , X86::ADD_F64m  },
358  { X86::ADD_FpI16m32 , X86::ADD_FI16m },
359  { X86::ADD_FpI16m64 , X86::ADD_FI16m },
360  { X86::ADD_FpI16m80 , X86::ADD_FI16m },
361  { X86::ADD_FpI32m32 , X86::ADD_FI32m },
362  { X86::ADD_FpI32m64 , X86::ADD_FI32m },
363  { X86::ADD_FpI32m80 , X86::ADD_FI32m },
364  { X86::CHS_Fp32     , X86::CHS_F     },
365  { X86::CHS_Fp64     , X86::CHS_F     },
366  { X86::CHS_Fp80     , X86::CHS_F     },
367  { X86::CMOVBE_Fp32  , X86::CMOVBE_F  },
368  { X86::CMOVBE_Fp64  , X86::CMOVBE_F  },
369  { X86::CMOVBE_Fp80  , X86::CMOVBE_F  },
370  { X86::CMOVB_Fp32   , X86::CMOVB_F   },
371  { X86::CMOVB_Fp64   , X86::CMOVB_F  },
372  { X86::CMOVB_Fp80   , X86::CMOVB_F  },
373  { X86::CMOVE_Fp32   , X86::CMOVE_F  },
374  { X86::CMOVE_Fp64   , X86::CMOVE_F   },
375  { X86::CMOVE_Fp80   , X86::CMOVE_F   },
376  { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F },
377  { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F },
378  { X86::CMOVNBE_Fp80 , X86::CMOVNBE_F },
379  { X86::CMOVNB_Fp32  , X86::CMOVNB_F  },
380  { X86::CMOVNB_Fp64  , X86::CMOVNB_F  },
381  { X86::CMOVNB_Fp80  , X86::CMOVNB_F  },
382  { X86::CMOVNE_Fp32  , X86::CMOVNE_F  },
383  { X86::CMOVNE_Fp64  , X86::CMOVNE_F  },
384  { X86::CMOVNE_Fp80  , X86::CMOVNE_F  },
385  { X86::CMOVNP_Fp32  , X86::CMOVNP_F  },
386  { X86::CMOVNP_Fp64  , X86::CMOVNP_F  },
387  { X86::CMOVNP_Fp80  , X86::CMOVNP_F  },
388  { X86::CMOVP_Fp32   , X86::CMOVP_F   },
389  { X86::CMOVP_Fp64   , X86::CMOVP_F   },
390  { X86::CMOVP_Fp80   , X86::CMOVP_F   },
391  { X86::COS_Fp32     , X86::COS_F     },
392  { X86::COS_Fp64     , X86::COS_F     },
393  { X86::COS_Fp80     , X86::COS_F     },
394  { X86::DIVR_Fp32m   , X86::DIVR_F32m },
395  { X86::DIVR_Fp64m   , X86::DIVR_F64m },
396  { X86::DIVR_Fp64m32 , X86::DIVR_F32m },
397  { X86::DIVR_Fp80m32 , X86::DIVR_F32m },
398  { X86::DIVR_Fp80m64 , X86::DIVR_F64m },
399  { X86::DIVR_FpI16m32, X86::DIVR_FI16m},
400  { X86::DIVR_FpI16m64, X86::DIVR_FI16m},
401  { X86::DIVR_FpI16m80, X86::DIVR_FI16m},
402  { X86::DIVR_FpI32m32, X86::DIVR_FI32m},
403  { X86::DIVR_FpI32m64, X86::DIVR_FI32m},
404  { X86::DIVR_FpI32m80, X86::DIVR_FI32m},
405  { X86::DIV_Fp32m    , X86::DIV_F32m  },
406  { X86::DIV_Fp64m    , X86::DIV_F64m  },
407  { X86::DIV_Fp64m32  , X86::DIV_F32m  },
408  { X86::DIV_Fp80m32  , X86::DIV_F32m  },
409  { X86::DIV_Fp80m64  , X86::DIV_F64m  },
410  { X86::DIV_FpI16m32 , X86::DIV_FI16m },
411  { X86::DIV_FpI16m64 , X86::DIV_FI16m },
412  { X86::DIV_FpI16m80 , X86::DIV_FI16m },
413  { X86::DIV_FpI32m32 , X86::DIV_FI32m },
414  { X86::DIV_FpI32m64 , X86::DIV_FI32m },
415  { X86::DIV_FpI32m80 , X86::DIV_FI32m },
416  { X86::ILD_Fp16m32  , X86::ILD_F16m  },
417  { X86::ILD_Fp16m64  , X86::ILD_F16m  },
418  { X86::ILD_Fp16m80  , X86::ILD_F16m  },
419  { X86::ILD_Fp32m32  , X86::ILD_F32m  },
420  { X86::ILD_Fp32m64  , X86::ILD_F32m  },
421  { X86::ILD_Fp32m80  , X86::ILD_F32m  },
422  { X86::ILD_Fp64m32  , X86::ILD_F64m  },
423  { X86::ILD_Fp64m64  , X86::ILD_F64m  },
424  { X86::ILD_Fp64m80  , X86::ILD_F64m  },
425  { X86::ISTT_Fp16m32 , X86::ISTT_FP16m},
426  { X86::ISTT_Fp16m64 , X86::ISTT_FP16m},
427  { X86::ISTT_Fp16m80 , X86::ISTT_FP16m},
428  { X86::ISTT_Fp32m32 , X86::ISTT_FP32m},
429  { X86::ISTT_Fp32m64 , X86::ISTT_FP32m},
430  { X86::ISTT_Fp32m80 , X86::ISTT_FP32m},
431  { X86::ISTT_Fp64m32 , X86::ISTT_FP64m},
432  { X86::ISTT_Fp64m64 , X86::ISTT_FP64m},
433  { X86::ISTT_Fp64m80 , X86::ISTT_FP64m},
434  { X86::IST_Fp16m32  , X86::IST_F16m  },
435  { X86::IST_Fp16m64  , X86::IST_F16m  },
436  { X86::IST_Fp16m80  , X86::IST_F16m  },
437  { X86::IST_Fp32m32  , X86::IST_F32m  },
438  { X86::IST_Fp32m64  , X86::IST_F32m  },
439  { X86::IST_Fp32m80  , X86::IST_F32m  },
440  { X86::IST_Fp64m32  , X86::IST_FP64m },
441  { X86::IST_Fp64m64  , X86::IST_FP64m },
442  { X86::IST_Fp64m80  , X86::IST_FP64m },
443  { X86::LD_Fp032     , X86::LD_F0     },
444  { X86::LD_Fp064     , X86::LD_F0     },
445  { X86::LD_Fp080     , X86::LD_F0     },
446  { X86::LD_Fp132     , X86::LD_F1     },
447  { X86::LD_Fp164     , X86::LD_F1     },
448  { X86::LD_Fp180     , X86::LD_F1     },
449  { X86::LD_Fp32m     , X86::LD_F32m   },
450  { X86::LD_Fp32m64   , X86::LD_F32m   },
451  { X86::LD_Fp32m80   , X86::LD_F32m   },
452  { X86::LD_Fp64m     , X86::LD_F64m   },
453  { X86::LD_Fp64m80   , X86::LD_F64m   },
454  { X86::LD_Fp80m     , X86::LD_F80m   },
455  { X86::MUL_Fp32m    , X86::MUL_F32m  },
456  { X86::MUL_Fp64m    , X86::MUL_F64m  },
457  { X86::MUL_Fp64m32  , X86::MUL_F32m  },
458  { X86::MUL_Fp80m32  , X86::MUL_F32m  },
459  { X86::MUL_Fp80m64  , X86::MUL_F64m  },
460  { X86::MUL_FpI16m32 , X86::MUL_FI16m },
461  { X86::MUL_FpI16m64 , X86::MUL_FI16m },
462  { X86::MUL_FpI16m80 , X86::MUL_FI16m },
463  { X86::MUL_FpI32m32 , X86::MUL_FI32m },
464  { X86::MUL_FpI32m64 , X86::MUL_FI32m },
465  { X86::MUL_FpI32m80 , X86::MUL_FI32m },
466  { X86::SIN_Fp32     , X86::SIN_F     },
467  { X86::SIN_Fp64     , X86::SIN_F     },
468  { X86::SIN_Fp80     , X86::SIN_F     },
469  { X86::SQRT_Fp32    , X86::SQRT_F    },
470  { X86::SQRT_Fp64    , X86::SQRT_F    },
471  { X86::SQRT_Fp80    , X86::SQRT_F    },
472  { X86::ST_Fp32m     , X86::ST_F32m   },
473  { X86::ST_Fp64m     , X86::ST_F64m   },
474  { X86::ST_Fp64m32   , X86::ST_F32m   },
475  { X86::ST_Fp80m32   , X86::ST_F32m   },
476  { X86::ST_Fp80m64   , X86::ST_F64m   },
477  { X86::ST_FpP80m    , X86::ST_FP80m  },
478  { X86::SUBR_Fp32m   , X86::SUBR_F32m },
479  { X86::SUBR_Fp64m   , X86::SUBR_F64m },
480  { X86::SUBR_Fp64m32 , X86::SUBR_F32m },
481  { X86::SUBR_Fp80m32 , X86::SUBR_F32m },
482  { X86::SUBR_Fp80m64 , X86::SUBR_F64m },
483  { X86::SUBR_FpI16m32, X86::SUBR_FI16m},
484  { X86::SUBR_FpI16m64, X86::SUBR_FI16m},
485  { X86::SUBR_FpI16m80, X86::SUBR_FI16m},
486  { X86::SUBR_FpI32m32, X86::SUBR_FI32m},
487  { X86::SUBR_FpI32m64, X86::SUBR_FI32m},
488  { X86::SUBR_FpI32m80, X86::SUBR_FI32m},
489  { X86::SUB_Fp32m    , X86::SUB_F32m  },
490  { X86::SUB_Fp64m    , X86::SUB_F64m  },
491  { X86::SUB_Fp64m32  , X86::SUB_F32m  },
492  { X86::SUB_Fp80m32  , X86::SUB_F32m  },
493  { X86::SUB_Fp80m64  , X86::SUB_F64m  },
494  { X86::SUB_FpI16m32 , X86::SUB_FI16m },
495  { X86::SUB_FpI16m64 , X86::SUB_FI16m },
496  { X86::SUB_FpI16m80 , X86::SUB_FI16m },
497  { X86::SUB_FpI32m32 , X86::SUB_FI32m },
498  { X86::SUB_FpI32m64 , X86::SUB_FI32m },
499  { X86::SUB_FpI32m80 , X86::SUB_FI32m },
500  { X86::TST_Fp32     , X86::TST_F     },
501  { X86::TST_Fp64     , X86::TST_F     },
502  { X86::TST_Fp80     , X86::TST_F     },
503  { X86::UCOM_FpIr32  , X86::UCOM_FIr  },
504  { X86::UCOM_FpIr64  , X86::UCOM_FIr  },
505  { X86::UCOM_FpIr80  , X86::UCOM_FIr  },
506  { X86::UCOM_Fpr32   , X86::UCOM_Fr   },
507  { X86::UCOM_Fpr64   , X86::UCOM_Fr   },
508  { X86::UCOM_Fpr80   , X86::UCOM_Fr   },
509};
510
511static unsigned getConcreteOpcode(unsigned Opcode) {
512  ASSERT_SORTED(OpcodeTable);
513  int Opc = Lookup(OpcodeTable, array_lengthof(OpcodeTable), Opcode);
514  assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!");
515  return Opc;
516}
517
518//===----------------------------------------------------------------------===//
519// Helper Methods
520//===----------------------------------------------------------------------===//
521
522// PopTable - Sorted map of instructions to their popping version.  The first
523// element is an instruction, the second is the version which pops.
524//
525static const TableEntry PopTable[] = {
526  { X86::ADD_FrST0 , X86::ADD_FPrST0  },
527
528  { X86::DIVR_FrST0, X86::DIVR_FPrST0 },
529  { X86::DIV_FrST0 , X86::DIV_FPrST0  },
530
531  { X86::IST_F16m  , X86::IST_FP16m   },
532  { X86::IST_F32m  , X86::IST_FP32m   },
533
534  { X86::MUL_FrST0 , X86::MUL_FPrST0  },
535
536  { X86::ST_F32m   , X86::ST_FP32m    },
537  { X86::ST_F64m   , X86::ST_FP64m    },
538  { X86::ST_Frr    , X86::ST_FPrr     },
539
540  { X86::SUBR_FrST0, X86::SUBR_FPrST0 },
541  { X86::SUB_FrST0 , X86::SUB_FPrST0  },
542
543  { X86::UCOM_FIr  , X86::UCOM_FIPr   },
544
545  { X86::UCOM_FPr  , X86::UCOM_FPPr   },
546  { X86::UCOM_Fr   , X86::UCOM_FPr    },
547};
548
549/// popStackAfter - Pop the current value off of the top of the FP stack after
550/// the specified instruction.  This attempts to be sneaky and combine the pop
551/// into the instruction itself if possible.  The iterator is left pointing to
552/// the last instruction, be it a new pop instruction inserted, or the old
553/// instruction if it was modified in place.
554///
555void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
556  MachineInstr* MI = I;
557  DebugLoc dl = MI->getDebugLoc();
558  ASSERT_SORTED(PopTable);
559  assert(StackTop > 0 && "Cannot pop empty stack!");
560  RegMap[Stack[--StackTop]] = ~0;     // Update state
561
562  // Check to see if there is a popping version of this instruction...
563  int Opcode = Lookup(PopTable, array_lengthof(PopTable), I->getOpcode());
564  if (Opcode != -1) {
565    I->setDesc(TII->get(Opcode));
566    if (Opcode == X86::UCOM_FPPr)
567      I->RemoveOperand(0);
568  } else {    // Insert an explicit pop
569    I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
570  }
571}
572
573/// freeStackSlotAfter - Free the specified register from the register stack, so
574/// that it is no longer in a register.  If the register is currently at the top
575/// of the stack, we just pop the current instruction, otherwise we store the
576/// current top-of-stack into the specified slot, then pop the top of stack.
577void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) {
578  if (getStackEntry(0) == FPRegNo) {  // already at the top of stack? easy.
579    popStackAfter(I);
580    return;
581  }
582
583  // Otherwise, store the top of stack into the dead slot, killing the operand
584  // without having to add in an explicit xchg then pop.
585  //
586  unsigned STReg    = getSTReg(FPRegNo);
587  unsigned OldSlot  = getSlot(FPRegNo);
588  unsigned TopReg   = Stack[StackTop-1];
589  Stack[OldSlot]    = TopReg;
590  RegMap[TopReg]    = OldSlot;
591  RegMap[FPRegNo]   = ~0;
592  Stack[--StackTop] = ~0;
593  MachineInstr *MI  = I;
594  DebugLoc dl = MI->getDebugLoc();
595  I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(STReg);
596}
597
598
599//===----------------------------------------------------------------------===//
600// Instruction transformation implementation
601//===----------------------------------------------------------------------===//
602
603/// handleZeroArgFP - ST(0) = fld0    ST(0) = flds <mem>
604///
605void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
606  MachineInstr *MI = I;
607  unsigned DestReg = getFPReg(MI->getOperand(0));
608
609  // Change from the pseudo instruction to the concrete instruction.
610  MI->RemoveOperand(0);   // Remove the explicit ST(0) operand
611  MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
612
613  // Result gets pushed on the stack.
614  pushReg(DestReg);
615}
616
617/// handleOneArgFP - fst <mem>, ST(0)
618///
619void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
620  MachineInstr *MI = I;
621  unsigned NumOps = MI->getDesc().getNumOperands();
622  assert((NumOps == X86AddrNumOperands + 1 || NumOps == 1) &&
623         "Can only handle fst* & ftst instructions!");
624
625  // Is this the last use of the source register?
626  unsigned Reg = getFPReg(MI->getOperand(NumOps-1));
627  bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
628
629  // FISTP64m is strange because there isn't a non-popping versions.
630  // If we have one _and_ we don't want to pop the operand, duplicate the value
631  // on the stack instead of moving it.  This ensure that popping the value is
632  // always ok.
633  // Ditto FISTTP16m, FISTTP32m, FISTTP64m, ST_FpP80m.
634  //
635  if (!KillsSrc &&
636      (MI->getOpcode() == X86::IST_Fp64m32 ||
637       MI->getOpcode() == X86::ISTT_Fp16m32 ||
638       MI->getOpcode() == X86::ISTT_Fp32m32 ||
639       MI->getOpcode() == X86::ISTT_Fp64m32 ||
640       MI->getOpcode() == X86::IST_Fp64m64 ||
641       MI->getOpcode() == X86::ISTT_Fp16m64 ||
642       MI->getOpcode() == X86::ISTT_Fp32m64 ||
643       MI->getOpcode() == X86::ISTT_Fp64m64 ||
644       MI->getOpcode() == X86::IST_Fp64m80 ||
645       MI->getOpcode() == X86::ISTT_Fp16m80 ||
646       MI->getOpcode() == X86::ISTT_Fp32m80 ||
647       MI->getOpcode() == X86::ISTT_Fp64m80 ||
648       MI->getOpcode() == X86::ST_FpP80m)) {
649    duplicateToTop(Reg, 7 /*temp register*/, I);
650  } else {
651    moveToTop(Reg, I);            // Move to the top of the stack...
652  }
653
654  // Convert from the pseudo instruction to the concrete instruction.
655  MI->RemoveOperand(NumOps-1);    // Remove explicit ST(0) operand
656  MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
657
658  if (MI->getOpcode() == X86::IST_FP64m ||
659      MI->getOpcode() == X86::ISTT_FP16m ||
660      MI->getOpcode() == X86::ISTT_FP32m ||
661      MI->getOpcode() == X86::ISTT_FP64m ||
662      MI->getOpcode() == X86::ST_FP80m) {
663    assert(StackTop > 0 && "Stack empty??");
664    --StackTop;
665  } else if (KillsSrc) { // Last use of operand?
666    popStackAfter(I);
667  }
668}
669
670
671/// handleOneArgFPRW: Handle instructions that read from the top of stack and
672/// replace the value with a newly computed value.  These instructions may have
673/// non-fp operands after their FP operands.
674///
675///  Examples:
676///     R1 = fchs R2
677///     R1 = fadd R2, [mem]
678///
679void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
680  MachineInstr *MI = I;
681#ifndef NDEBUG
682  unsigned NumOps = MI->getDesc().getNumOperands();
683  assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
684#endif
685
686  // Is this the last use of the source register?
687  unsigned Reg = getFPReg(MI->getOperand(1));
688  bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
689
690  if (KillsSrc) {
691    // If this is the last use of the source register, just make sure it's on
692    // the top of the stack.
693    moveToTop(Reg, I);
694    assert(StackTop > 0 && "Stack cannot be empty!");
695    --StackTop;
696    pushReg(getFPReg(MI->getOperand(0)));
697  } else {
698    // If this is not the last use of the source register, _copy_ it to the top
699    // of the stack.
700    duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I);
701  }
702
703  // Change from the pseudo instruction to the concrete instruction.
704  MI->RemoveOperand(1);   // Drop the source operand.
705  MI->RemoveOperand(0);   // Drop the destination operand.
706  MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
707}
708
709
710//===----------------------------------------------------------------------===//
711// Define tables of various ways to map pseudo instructions
712//
713
714// ForwardST0Table - Map: A = B op C  into: ST(0) = ST(0) op ST(i)
715static const TableEntry ForwardST0Table[] = {
716  { X86::ADD_Fp32  , X86::ADD_FST0r },
717  { X86::ADD_Fp64  , X86::ADD_FST0r },
718  { X86::ADD_Fp80  , X86::ADD_FST0r },
719  { X86::DIV_Fp32  , X86::DIV_FST0r },
720  { X86::DIV_Fp64  , X86::DIV_FST0r },
721  { X86::DIV_Fp80  , X86::DIV_FST0r },
722  { X86::MUL_Fp32  , X86::MUL_FST0r },
723  { X86::MUL_Fp64  , X86::MUL_FST0r },
724  { X86::MUL_Fp80  , X86::MUL_FST0r },
725  { X86::SUB_Fp32  , X86::SUB_FST0r },
726  { X86::SUB_Fp64  , X86::SUB_FST0r },
727  { X86::SUB_Fp80  , X86::SUB_FST0r },
728};
729
730// ReverseST0Table - Map: A = B op C  into: ST(0) = ST(i) op ST(0)
731static const TableEntry ReverseST0Table[] = {
732  { X86::ADD_Fp32  , X86::ADD_FST0r  },   // commutative
733  { X86::ADD_Fp64  , X86::ADD_FST0r  },   // commutative
734  { X86::ADD_Fp80  , X86::ADD_FST0r  },   // commutative
735  { X86::DIV_Fp32  , X86::DIVR_FST0r },
736  { X86::DIV_Fp64  , X86::DIVR_FST0r },
737  { X86::DIV_Fp80  , X86::DIVR_FST0r },
738  { X86::MUL_Fp32  , X86::MUL_FST0r  },   // commutative
739  { X86::MUL_Fp64  , X86::MUL_FST0r  },   // commutative
740  { X86::MUL_Fp80  , X86::MUL_FST0r  },   // commutative
741  { X86::SUB_Fp32  , X86::SUBR_FST0r },
742  { X86::SUB_Fp64  , X86::SUBR_FST0r },
743  { X86::SUB_Fp80  , X86::SUBR_FST0r },
744};
745
746// ForwardSTiTable - Map: A = B op C  into: ST(i) = ST(0) op ST(i)
747static const TableEntry ForwardSTiTable[] = {
748  { X86::ADD_Fp32  , X86::ADD_FrST0  },   // commutative
749  { X86::ADD_Fp64  , X86::ADD_FrST0  },   // commutative
750  { X86::ADD_Fp80  , X86::ADD_FrST0  },   // commutative
751  { X86::DIV_Fp32  , X86::DIVR_FrST0 },
752  { X86::DIV_Fp64  , X86::DIVR_FrST0 },
753  { X86::DIV_Fp80  , X86::DIVR_FrST0 },
754  { X86::MUL_Fp32  , X86::MUL_FrST0  },   // commutative
755  { X86::MUL_Fp64  , X86::MUL_FrST0  },   // commutative
756  { X86::MUL_Fp80  , X86::MUL_FrST0  },   // commutative
757  { X86::SUB_Fp32  , X86::SUBR_FrST0 },
758  { X86::SUB_Fp64  , X86::SUBR_FrST0 },
759  { X86::SUB_Fp80  , X86::SUBR_FrST0 },
760};
761
762// ReverseSTiTable - Map: A = B op C  into: ST(i) = ST(i) op ST(0)
763static const TableEntry ReverseSTiTable[] = {
764  { X86::ADD_Fp32  , X86::ADD_FrST0 },
765  { X86::ADD_Fp64  , X86::ADD_FrST0 },
766  { X86::ADD_Fp80  , X86::ADD_FrST0 },
767  { X86::DIV_Fp32  , X86::DIV_FrST0 },
768  { X86::DIV_Fp64  , X86::DIV_FrST0 },
769  { X86::DIV_Fp80  , X86::DIV_FrST0 },
770  { X86::MUL_Fp32  , X86::MUL_FrST0 },
771  { X86::MUL_Fp64  , X86::MUL_FrST0 },
772  { X86::MUL_Fp80  , X86::MUL_FrST0 },
773  { X86::SUB_Fp32  , X86::SUB_FrST0 },
774  { X86::SUB_Fp64  , X86::SUB_FrST0 },
775  { X86::SUB_Fp80  , X86::SUB_FrST0 },
776};
777
778
779/// handleTwoArgFP - Handle instructions like FADD and friends which are virtual
780/// instructions which need to be simplified and possibly transformed.
781///
782/// Result: ST(0) = fsub  ST(0), ST(i)
783///         ST(i) = fsub  ST(0), ST(i)
784///         ST(0) = fsubr ST(0), ST(i)
785///         ST(i) = fsubr ST(0), ST(i)
786///
787void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
788  ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
789  ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
790  MachineInstr *MI = I;
791
792  unsigned NumOperands = MI->getDesc().getNumOperands();
793  assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
794  unsigned Dest = getFPReg(MI->getOperand(0));
795  unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
796  unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
797  bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
798  bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
799  DebugLoc dl = MI->getDebugLoc();
800
801  unsigned TOS = getStackEntry(0);
802
803  // One of our operands must be on the top of the stack.  If neither is yet, we
804  // need to move one.
805  if (Op0 != TOS && Op1 != TOS) {   // No operand at TOS?
806    // We can choose to move either operand to the top of the stack.  If one of
807    // the operands is killed by this instruction, we want that one so that we
808    // can update right on top of the old version.
809    if (KillsOp0) {
810      moveToTop(Op0, I);         // Move dead operand to TOS.
811      TOS = Op0;
812    } else if (KillsOp1) {
813      moveToTop(Op1, I);
814      TOS = Op1;
815    } else {
816      // All of the operands are live after this instruction executes, so we
817      // cannot update on top of any operand.  Because of this, we must
818      // duplicate one of the stack elements to the top.  It doesn't matter
819      // which one we pick.
820      //
821      duplicateToTop(Op0, Dest, I);
822      Op0 = TOS = Dest;
823      KillsOp0 = true;
824    }
825  } else if (!KillsOp0 && !KillsOp1) {
826    // If we DO have one of our operands at the top of the stack, but we don't
827    // have a dead operand, we must duplicate one of the operands to a new slot
828    // on the stack.
829    duplicateToTop(Op0, Dest, I);
830    Op0 = TOS = Dest;
831    KillsOp0 = true;
832  }
833
834  // Now we know that one of our operands is on the top of the stack, and at
835  // least one of our operands is killed by this instruction.
836  assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) &&
837         "Stack conditions not set up right!");
838
839  // We decide which form to use based on what is on the top of the stack, and
840  // which operand is killed by this instruction.
841  const TableEntry *InstTable;
842  bool isForward = TOS == Op0;
843  bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0);
844  if (updateST0) {
845    if (isForward)
846      InstTable = ForwardST0Table;
847    else
848      InstTable = ReverseST0Table;
849  } else {
850    if (isForward)
851      InstTable = ForwardSTiTable;
852    else
853      InstTable = ReverseSTiTable;
854  }
855
856  int Opcode = Lookup(InstTable, array_lengthof(ForwardST0Table),
857                      MI->getOpcode());
858  assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
859
860  // NotTOS - The register which is not on the top of stack...
861  unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
862
863  // Replace the old instruction with a new instruction
864  MBB->remove(I++);
865  I = BuildMI(*MBB, I, dl, TII->get(Opcode)).addReg(getSTReg(NotTOS));
866
867  // If both operands are killed, pop one off of the stack in addition to
868  // overwriting the other one.
869  if (KillsOp0 && KillsOp1 && Op0 != Op1) {
870    assert(!updateST0 && "Should have updated other operand!");
871    popStackAfter(I);   // Pop the top of stack
872  }
873
874  // Update stack information so that we know the destination register is now on
875  // the stack.
876  unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS);
877  assert(UpdatedSlot < StackTop && Dest < 7);
878  Stack[UpdatedSlot]   = Dest;
879  RegMap[Dest]         = UpdatedSlot;
880  MBB->getParent()->DeleteMachineInstr(MI); // Remove the old instruction
881}
882
883/// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP
884/// register arguments and no explicit destinations.
885///
886void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
887  ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
888  ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
889  MachineInstr *MI = I;
890
891  unsigned NumOperands = MI->getDesc().getNumOperands();
892  assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
893  unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
894  unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
895  bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
896  bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
897
898  // Make sure the first operand is on the top of stack, the other one can be
899  // anywhere.
900  moveToTop(Op0, I);
901
902  // Change from the pseudo instruction to the concrete instruction.
903  MI->getOperand(0).setReg(getSTReg(Op1));
904  MI->RemoveOperand(1);
905  MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
906
907  // If any of the operands are killed by this instruction, free them.
908  if (KillsOp0) freeStackSlotAfter(I, Op0);
909  if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1);
910}
911
912/// handleCondMovFP - Handle two address conditional move instructions.  These
913/// instructions move a st(i) register to st(0) iff a condition is true.  These
914/// instructions require that the first operand is at the top of the stack, but
915/// otherwise don't modify the stack at all.
916void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
917  MachineInstr *MI = I;
918
919  unsigned Op0 = getFPReg(MI->getOperand(0));
920  unsigned Op1 = getFPReg(MI->getOperand(2));
921  bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
922
923  // The first operand *must* be on the top of the stack.
924  moveToTop(Op0, I);
925
926  // Change the second operand to the stack register that the operand is in.
927  // Change from the pseudo instruction to the concrete instruction.
928  MI->RemoveOperand(0);
929  MI->RemoveOperand(1);
930  MI->getOperand(0).setReg(getSTReg(Op1));
931  MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
932
933  // If we kill the second operand, make sure to pop it from the stack.
934  if (Op0 != Op1 && KillsOp1) {
935    // Get this value off of the register stack.
936    freeStackSlotAfter(I, Op1);
937  }
938}
939
940
941/// handleSpecialFP - Handle special instructions which behave unlike other
942/// floating point instructions.  This is primarily intended for use by pseudo
943/// instructions.
944///
945void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
946  MachineInstr *MI = I;
947  DebugLoc dl = MI->getDebugLoc();
948  switch (MI->getOpcode()) {
949  default: llvm_unreachable("Unknown SpecialFP instruction!");
950  case X86::FpGET_ST0_32:// Appears immediately after a call returning FP type!
951  case X86::FpGET_ST0_64:// Appears immediately after a call returning FP type!
952  case X86::FpGET_ST0_80:// Appears immediately after a call returning FP type!
953    assert(StackTop == 0 && "Stack should be empty after a call!");
954    pushReg(getFPReg(MI->getOperand(0)));
955    break;
956  case X86::FpGET_ST1_32:// Appears immediately after a call returning FP type!
957  case X86::FpGET_ST1_64:// Appears immediately after a call returning FP type!
958  case X86::FpGET_ST1_80:{// Appears immediately after a call returning FP type!
959    // FpGET_ST1 should occur right after a FpGET_ST0 for a call or inline asm.
960    // The pattern we expect is:
961    //  CALL
962    //  FP1 = FpGET_ST0
963    //  FP4 = FpGET_ST1
964    //
965    // At this point, we've pushed FP1 on the top of stack, so it should be
966    // present if it isn't dead.  If it was dead, we already emitted a pop to
967    // remove it from the stack and StackTop = 0.
968
969    // Push FP4 as top of stack next.
970    pushReg(getFPReg(MI->getOperand(0)));
971
972    // If StackTop was 0 before we pushed our operand, then ST(0) must have been
973    // dead.  In this case, the ST(1) value is the only thing that is live, so
974    // it should be on the TOS (after the pop that was emitted) and is.  Just
975    // continue in this case.
976    if (StackTop == 1)
977      break;
978
979    // Because pushReg just pushed ST(1) as TOS, we now have to swap the two top
980    // elements so that our accounting is correct.
981    unsigned RegOnTop = getStackEntry(0);
982    unsigned RegNo = getStackEntry(1);
983
984    // Swap the slots the regs are in.
985    std::swap(RegMap[RegNo], RegMap[RegOnTop]);
986
987    // Swap stack slot contents.
988    assert(RegMap[RegOnTop] < StackTop);
989    std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
990    break;
991  }
992  case X86::FpSET_ST0_32:
993  case X86::FpSET_ST0_64:
994  case X86::FpSET_ST0_80: {
995    unsigned Op0 = getFPReg(MI->getOperand(0));
996
997    // FpSET_ST0_80 is generated by copyRegToReg for both function return
998    // and inline assembly with the "st" constrain. In the latter case,
999    // it is possible for ST(0) to be alive after this instruction.
1000    if (!MI->killsRegister(X86::FP0 + Op0)) {
1001      // Duplicate Op0
1002      duplicateToTop(0, 7 /*temp register*/, I);
1003    } else {
1004      moveToTop(Op0, I);
1005    }
1006    --StackTop;   // "Forget" we have something on the top of stack!
1007    break;
1008  }
1009  case X86::FpSET_ST1_32:
1010  case X86::FpSET_ST1_64:
1011  case X86::FpSET_ST1_80:
1012    // StackTop can be 1 if a FpSET_ST0_* was before this. Exchange them.
1013    if (StackTop == 1) {
1014      BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(X86::ST1);
1015      NumFXCH++;
1016      StackTop = 0;
1017      break;
1018    }
1019    assert(StackTop == 2 && "Stack should have two element on it to return!");
1020    --StackTop;   // "Forget" we have something on the top of stack!
1021    break;
1022  case X86::MOV_Fp3232:
1023  case X86::MOV_Fp3264:
1024  case X86::MOV_Fp6432:
1025  case X86::MOV_Fp6464:
1026  case X86::MOV_Fp3280:
1027  case X86::MOV_Fp6480:
1028  case X86::MOV_Fp8032:
1029  case X86::MOV_Fp8064:
1030  case X86::MOV_Fp8080: {
1031    const MachineOperand &MO1 = MI->getOperand(1);
1032    unsigned SrcReg = getFPReg(MO1);
1033
1034    const MachineOperand &MO0 = MI->getOperand(0);
1035    // These can be created due to inline asm. Two address pass can introduce
1036    // copies from RFP registers to virtual registers.
1037    if (MO0.getReg() == X86::ST0 && SrcReg == 0) {
1038      assert(MO1.isKill());
1039      // Treat %ST0<def> = MOV_Fp8080 %FP0<kill>
1040      // like  FpSET_ST0_80 %FP0<kill>, %ST0<imp-def>
1041      assert((StackTop == 1 || StackTop == 2)
1042             && "Stack should have one or two element on it to return!");
1043      --StackTop;   // "Forget" we have something on the top of stack!
1044      break;
1045    } else if (MO0.getReg() == X86::ST1 && SrcReg == 1) {
1046      assert(MO1.isKill());
1047      // Treat %ST1<def> = MOV_Fp8080 %FP1<kill>
1048      // like  FpSET_ST1_80 %FP0<kill>, %ST1<imp-def>
1049      // StackTop can be 1 if a FpSET_ST0_* was before this. Exchange them.
1050      if (StackTop == 1) {
1051        BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(X86::ST1);
1052        NumFXCH++;
1053        StackTop = 0;
1054        break;
1055      }
1056      assert(StackTop == 2 && "Stack should have two element on it to return!");
1057      --StackTop;   // "Forget" we have something on the top of stack!
1058      break;
1059    }
1060
1061    unsigned DestReg = getFPReg(MO0);
1062    if (MI->killsRegister(X86::FP0+SrcReg)) {
1063      // If the input operand is killed, we can just change the owner of the
1064      // incoming stack slot into the result.
1065      unsigned Slot = getSlot(SrcReg);
1066      assert(Slot < 7 && DestReg < 7 && "FpMOV operands invalid!");
1067      Stack[Slot] = DestReg;
1068      RegMap[DestReg] = Slot;
1069
1070    } else {
1071      // For FMOV we just duplicate the specified value to a new stack slot.
1072      // This could be made better, but would require substantial changes.
1073      duplicateToTop(SrcReg, DestReg, I);
1074    }
1075    }
1076    break;
1077  case TargetInstrInfo::INLINEASM: {
1078    // The inline asm MachineInstr currently only *uses* FP registers for the
1079    // 'f' constraint.  These should be turned into the current ST(x) register
1080    // in the machine instr.  Also, any kills should be explicitly popped after
1081    // the inline asm.
1082    unsigned Kills[7];
1083    unsigned NumKills = 0;
1084    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1085      MachineOperand &Op = MI->getOperand(i);
1086      if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1087        continue;
1088      assert(Op.isUse() && "Only handle inline asm uses right now");
1089
1090      unsigned FPReg = getFPReg(Op);
1091      Op.setReg(getSTReg(FPReg));
1092
1093      // If we kill this operand, make sure to pop it from the stack after the
1094      // asm.  We just remember it for now, and pop them all off at the end in
1095      // a batch.
1096      if (Op.isKill())
1097        Kills[NumKills++] = FPReg;
1098    }
1099
1100    // If this asm kills any FP registers (is the last use of them) we must
1101    // explicitly emit pop instructions for them.  Do this now after the asm has
1102    // executed so that the ST(x) numbers are not off (which would happen if we
1103    // did this inline with operand rewriting).
1104    //
1105    // Note: this might be a non-optimal pop sequence.  We might be able to do
1106    // better by trying to pop in stack order or something.
1107    MachineBasicBlock::iterator InsertPt = MI;
1108    while (NumKills)
1109      freeStackSlotAfter(InsertPt, Kills[--NumKills]);
1110
1111    // Don't delete the inline asm!
1112    return;
1113  }
1114
1115  case X86::RET:
1116  case X86::RETI:
1117    // If RET has an FP register use operand, pass the first one in ST(0) and
1118    // the second one in ST(1).
1119    if (isStackEmpty()) return;  // Quick check to see if any are possible.
1120
1121    // Find the register operands.
1122    unsigned FirstFPRegOp = ~0U, SecondFPRegOp = ~0U;
1123
1124    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1125      MachineOperand &Op = MI->getOperand(i);
1126      if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1127        continue;
1128      // FP Register uses must be kills unless there are two uses of the same
1129      // register, in which case only one will be a kill.
1130      assert(Op.isUse() &&
1131             (Op.isKill() ||                        // Marked kill.
1132              getFPReg(Op) == FirstFPRegOp ||       // Second instance.
1133              MI->killsRegister(Op.getReg())) &&    // Later use is marked kill.
1134             "Ret only defs operands, and values aren't live beyond it");
1135
1136      if (FirstFPRegOp == ~0U)
1137        FirstFPRegOp = getFPReg(Op);
1138      else {
1139        assert(SecondFPRegOp == ~0U && "More than two fp operands!");
1140        SecondFPRegOp = getFPReg(Op);
1141      }
1142
1143      // Remove the operand so that later passes don't see it.
1144      MI->RemoveOperand(i);
1145      --i, --e;
1146    }
1147
1148    // There are only four possibilities here:
1149    // 1) we are returning a single FP value.  In this case, it has to be in
1150    //    ST(0) already, so just declare success by removing the value from the
1151    //    FP Stack.
1152    if (SecondFPRegOp == ~0U) {
1153      // Assert that the top of stack contains the right FP register.
1154      assert(StackTop == 1 && FirstFPRegOp == getStackEntry(0) &&
1155             "Top of stack not the right register for RET!");
1156
1157      // Ok, everything is good, mark the value as not being on the stack
1158      // anymore so that our assertion about the stack being empty at end of
1159      // block doesn't fire.
1160      StackTop = 0;
1161      return;
1162    }
1163
1164    // Otherwise, we are returning two values:
1165    // 2) If returning the same value for both, we only have one thing in the FP
1166    //    stack.  Consider:  RET FP1, FP1
1167    if (StackTop == 1) {
1168      assert(FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry(0)&&
1169             "Stack misconfiguration for RET!");
1170
1171      // Duplicate the TOS so that we return it twice.  Just pick some other FPx
1172      // register to hold it.
1173      unsigned NewReg = (FirstFPRegOp+1)%7;
1174      duplicateToTop(FirstFPRegOp, NewReg, MI);
1175      FirstFPRegOp = NewReg;
1176    }
1177
1178    /// Okay we know we have two different FPx operands now:
1179    assert(StackTop == 2 && "Must have two values live!");
1180
1181    /// 3) If SecondFPRegOp is currently in ST(0) and FirstFPRegOp is currently
1182    ///    in ST(1).  In this case, emit an fxch.
1183    if (getStackEntry(0) == SecondFPRegOp) {
1184      assert(getStackEntry(1) == FirstFPRegOp && "Unknown regs live");
1185      moveToTop(FirstFPRegOp, MI);
1186    }
1187
1188    /// 4) Finally, FirstFPRegOp must be in ST(0) and SecondFPRegOp must be in
1189    /// ST(1).  Just remove both from our understanding of the stack and return.
1190    assert(getStackEntry(0) == FirstFPRegOp && "Unknown regs live");
1191    assert(getStackEntry(1) == SecondFPRegOp && "Unknown regs live");
1192    StackTop = 0;
1193    return;
1194  }
1195
1196  I = MBB->erase(I);  // Remove the pseudo instruction
1197  --I;
1198}
1199