X86InstrAVX512.td revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338
1// Bitcasts between 512-bit vector types. Return the original type since 2// no instruction is needed for the conversion 3let Predicates = [HasAVX512] in { 4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>; 5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>; 6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>; 7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>; 8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>; 9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>; 10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>; 11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>; 12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>; 13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>; 14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>; 15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>; 16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>; 17 18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>; 19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>; 20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>; 21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>; 22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>; 23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>; 24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>; 25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>; 26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>; 27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>; 28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>; 29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>; 30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>; 31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>; 32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>; 33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>; 34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>; 35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>; 36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>; 37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>; 38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>; 39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>; 40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>; 41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>; 42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>; 43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>; 44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>; 45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>; 46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>; 47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>; 48 49// Bitcasts between 256-bit vector types. Return the original type since 50// no instruction is needed for the conversion 51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>; 52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>; 53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>; 54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>; 55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>; 56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>; 57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>; 58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>; 59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>; 60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>; 61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>; 62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>; 63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>; 64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>; 65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>; 66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>; 67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>; 68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>; 69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>; 70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>; 71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>; 72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>; 73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>; 74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>; 75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>; 76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>; 77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>; 78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>; 79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>; 80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>; 81} 82 83// 84// AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros. 85// 86 87let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, 88 isPseudo = 1, Predicates = [HasAVX512] in { 89def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "", 90 [(set VR512:$dst, (v16f32 immAllZerosV))]>; 91} 92 93let Predicates = [HasAVX512] in { 94def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>; 95def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>; 96def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>; 97} 98 99//===----------------------------------------------------------------------===// 100// AVX-512 - VECTOR INSERT 101// 102// -- 32x8 form -- 103let hasSideEffects = 0, ExeDomain = SSEPackedSingle in { 104def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst), 105 (ins VR512:$src1, VR128X:$src2, i8imm:$src3), 106 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", 107 []>, EVEX_4V, EVEX_V512; 108let mayLoad = 1 in 109def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst), 110 (ins VR512:$src1, f128mem:$src2, i8imm:$src3), 111 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", 112 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>; 113} 114 115// -- 64x4 fp form -- 116let hasSideEffects = 0, ExeDomain = SSEPackedDouble in { 117def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst), 118 (ins VR512:$src1, VR256X:$src2, i8imm:$src3), 119 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", 120 []>, EVEX_4V, EVEX_V512, VEX_W; 121let mayLoad = 1 in 122def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst), 123 (ins VR512:$src1, i256mem:$src2, i8imm:$src3), 124 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", 125 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>; 126} 127// -- 32x4 integer form -- 128let hasSideEffects = 0 in { 129def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst), 130 (ins VR512:$src1, VR128X:$src2, i8imm:$src3), 131 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", 132 []>, EVEX_4V, EVEX_V512; 133let mayLoad = 1 in 134def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst), 135 (ins VR512:$src1, i128mem:$src2, i8imm:$src3), 136 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", 137 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>; 138 139} 140 141let hasSideEffects = 0 in { 142// -- 64x4 form -- 143def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst), 144 (ins VR512:$src1, VR256X:$src2, i8imm:$src3), 145 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", 146 []>, EVEX_4V, EVEX_V512, VEX_W; 147let mayLoad = 1 in 148def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst), 149 (ins VR512:$src1, i256mem:$src2, i8imm:$src3), 150 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", 151 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>; 152} 153 154def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2), 155 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2, 156 (INSERT_get_vinsert128_imm VR512:$ins))>; 157def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2), 158 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2, 159 (INSERT_get_vinsert128_imm VR512:$ins))>; 160def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2), 161 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2, 162 (INSERT_get_vinsert128_imm VR512:$ins))>; 163def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2), 164 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2, 165 (INSERT_get_vinsert128_imm VR512:$ins))>; 166 167def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2), 168 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2, 169 (INSERT_get_vinsert128_imm VR512:$ins))>; 170def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), 171 (bc_v4i32 (loadv2i64 addr:$src2)), 172 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2, 173 (INSERT_get_vinsert128_imm VR512:$ins))>; 174def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2), 175 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2, 176 (INSERT_get_vinsert128_imm VR512:$ins))>; 177def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2), 178 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2, 179 (INSERT_get_vinsert128_imm VR512:$ins))>; 180 181def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2), 182 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2, 183 (INSERT_get_vinsert256_imm VR512:$ins))>; 184def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2), 185 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2, 186 (INSERT_get_vinsert256_imm VR512:$ins))>; 187def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2), 188 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2, 189 (INSERT_get_vinsert256_imm VR512:$ins))>; 190def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2), 191 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2, 192 (INSERT_get_vinsert256_imm VR512:$ins))>; 193 194def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2), 195 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2, 196 (INSERT_get_vinsert256_imm VR512:$ins))>; 197def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2), 198 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2, 199 (INSERT_get_vinsert256_imm VR512:$ins))>; 200def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2), 201 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2, 202 (INSERT_get_vinsert256_imm VR512:$ins))>; 203def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1), 204 (bc_v8i32 (loadv4i64 addr:$src2)), 205 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2, 206 (INSERT_get_vinsert256_imm VR512:$ins))>; 207 208// vinsertps - insert f32 to XMM 209def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst), 210 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3), 211 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", 212 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>, 213 EVEX_4V; 214def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst), 215 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3), 216 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", 217 [(set VR128X:$dst, (X86insrtps VR128X:$src1, 218 (v4f32 (scalar_to_vector (loadf32 addr:$src2))), 219 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>; 220 221//===----------------------------------------------------------------------===// 222// AVX-512 VECTOR EXTRACT 223//--- 224let hasSideEffects = 0, ExeDomain = SSEPackedSingle in { 225// -- 32x4 form -- 226def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst), 227 (ins VR512:$src1, i8imm:$src2), 228 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}", 229 []>, EVEX, EVEX_V512; 230def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs), 231 (ins f128mem:$dst, VR512:$src1, i8imm:$src2), 232 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}", 233 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>; 234 235// -- 64x4 form -- 236def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst), 237 (ins VR512:$src1, i8imm:$src2), 238 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}", 239 []>, EVEX, EVEX_V512, VEX_W; 240let mayStore = 1 in 241def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs), 242 (ins f256mem:$dst, VR512:$src1, i8imm:$src2), 243 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}", 244 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>; 245} 246 247let hasSideEffects = 0 in { 248// -- 32x4 form -- 249def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst), 250 (ins VR512:$src1, i8imm:$src2), 251 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}", 252 []>, EVEX, EVEX_V512; 253def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs), 254 (ins i128mem:$dst, VR512:$src1, i8imm:$src2), 255 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}", 256 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>; 257 258// -- 64x4 form -- 259def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst), 260 (ins VR512:$src1, i8imm:$src2), 261 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}", 262 []>, EVEX, EVEX_V512, VEX_W; 263let mayStore = 1 in 264def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs), 265 (ins i256mem:$dst, VR512:$src1, i8imm:$src2), 266 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}", 267 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>; 268} 269 270def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)), 271 (v4f32 (VEXTRACTF32x4rr VR512:$src1, 272 (EXTRACT_get_vextract128_imm VR128X:$ext)))>; 273 274def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)), 275 (v4i32 (VEXTRACTF32x4rr VR512:$src1, 276 (EXTRACT_get_vextract128_imm VR128X:$ext)))>; 277 278def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)), 279 (v2f64 (VEXTRACTF32x4rr VR512:$src1, 280 (EXTRACT_get_vextract128_imm VR128X:$ext)))>; 281 282def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)), 283 (v2i64 (VEXTRACTI32x4rr VR512:$src1, 284 (EXTRACT_get_vextract128_imm VR128X:$ext)))>; 285 286 287def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)), 288 (v8f32 (VEXTRACTF64x4rr VR512:$src1, 289 (EXTRACT_get_vextract256_imm VR256X:$ext)))>; 290 291def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)), 292 (v8i32 (VEXTRACTI64x4rr VR512:$src1, 293 (EXTRACT_get_vextract256_imm VR256X:$ext)))>; 294 295def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)), 296 (v4f64 (VEXTRACTF64x4rr VR512:$src1, 297 (EXTRACT_get_vextract256_imm VR256X:$ext)))>; 298 299def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)), 300 (v4i64 (VEXTRACTI64x4rr VR512:$src1, 301 (EXTRACT_get_vextract256_imm VR256X:$ext)))>; 302 303// A 256-bit subvector extract from the first 512-bit vector position 304// is a subregister copy that needs no instruction. 305def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))), 306 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>; 307def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))), 308 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>; 309def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))), 310 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>; 311def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))), 312 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>; 313 314// zmm -> xmm 315def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))), 316 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>; 317def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))), 318 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>; 319def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))), 320 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>; 321def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))), 322 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>; 323 324 325// A 128-bit subvector insert to the first 512-bit vector position 326// is a subregister copy that needs no instruction. 327def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)), 328 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), 329 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), 330 sub_ymm)>; 331def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)), 332 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), 333 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), 334 sub_ymm)>; 335def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)), 336 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), 337 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), 338 sub_ymm)>; 339def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)), 340 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), 341 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm), 342 sub_ymm)>; 343 344def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)), 345 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>; 346def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)), 347 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>; 348def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)), 349 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>; 350def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)), 351 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>; 352 353// vextractps - extract 32 bits from XMM 354def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst), 355 (ins VR128X:$src1, u32u8imm:$src2), 356 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}", 357 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>, 358 EVEX; 359 360def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs), 361 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2), 362 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}", 363 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2), 364 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>; 365 366//===---------------------------------------------------------------------===// 367// AVX-512 BROADCAST 368//--- 369multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr, 370 RegisterClass DestRC, 371 RegisterClass SrcRC, X86MemOperand x86memop> { 372 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src), 373 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), 374 []>, EVEX; 375 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src), 376 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX; 377} 378let ExeDomain = SSEPackedSingle in { 379 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512, 380 VR128X, f32mem>, 381 EVEX_V512, EVEX_CD8<32, CD8VT1>; 382} 383 384let ExeDomain = SSEPackedDouble in { 385 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512, 386 VR128X, f64mem>, 387 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>; 388} 389 390def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))), 391 (VBROADCASTSSZrm addr:$src)>; 392def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))), 393 (VBROADCASTSDZrm addr:$src)>; 394 395def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src), 396 (VBROADCASTSSZrm addr:$src)>; 397def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src), 398 (VBROADCASTSDZrm addr:$src)>; 399 400multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr, 401 RegisterClass SrcRC, RegisterClass KRC> { 402 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src), 403 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), 404 []>, EVEX, EVEX_V512; 405 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), 406 (ins KRC:$mask, SrcRC:$src), 407 !strconcat(OpcodeStr, 408 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"), 409 []>, EVEX, EVEX_V512, EVEX_KZ; 410} 411 412defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>; 413defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>, 414 VEX_W; 415 416def : Pat <(v16i32 (X86vzext VK16WM:$mask)), 417 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>; 418 419def : Pat <(v8i64 (X86vzext VK8WM:$mask)), 420 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>; 421 422def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))), 423 (VPBROADCASTDrZrr GR32:$src)>; 424def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))), 425 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>; 426def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))), 427 (VPBROADCASTQrZrr GR64:$src)>; 428def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))), 429 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>; 430 431def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))), 432 (VPBROADCASTDrZrr GR32:$src)>; 433def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))), 434 (VPBROADCASTQrZrr GR64:$src)>; 435 436def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src), 437 (v16i32 immAllZerosV), (i16 GR16:$mask))), 438 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>; 439def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src), 440 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))), 441 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>; 442 443multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr, 444 X86MemOperand x86memop, PatFrag ld_frag, 445 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT, 446 RegisterClass KRC> { 447 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src), 448 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), 449 [(set DstRC:$dst, 450 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX; 451 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask, 452 VR128X:$src), 453 !strconcat(OpcodeStr, 454 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"), 455 [(set DstRC:$dst, 456 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>, 457 EVEX, EVEX_KZ; 458 let mayLoad = 1 in { 459 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), 460 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), 461 [(set DstRC:$dst, 462 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX; 463 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask, 464 x86memop:$src), 465 !strconcat(OpcodeStr, 466 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"), 467 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask, 468 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ; 469 } 470} 471 472defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem, 473 loadi32, VR512, v16i32, v4i32, VK16WM>, 474 EVEX_V512, EVEX_CD8<32, CD8VT1>; 475defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem, 476 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W, 477 EVEX_CD8<64, CD8VT1>; 478 479def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))), 480 (VPBROADCASTDZrr VR128X:$src)>; 481def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))), 482 (VPBROADCASTQZrr VR128X:$src)>; 483 484def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))), 485 (VBROADCASTSSZrr VR128X:$src)>; 486def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))), 487 (VBROADCASTSDZrr VR128X:$src)>; 488 489def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))), 490 (VBROADCASTSSZrr VR128X:$src)>; 491def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))), 492 (VBROADCASTSDZrr VR128X:$src)>; 493 494// Provide fallback in case the load node that is used in the patterns above 495// is used by additional users, which prevents the pattern selection. 496def : Pat<(v16f32 (X86VBroadcast FR32X:$src)), 497 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>; 498def : Pat<(v8f64 (X86VBroadcast FR64X:$src)), 499 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>; 500 501 502let Predicates = [HasAVX512] in { 503def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))), 504 (EXTRACT_SUBREG 505 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM), 506 addr:$src)), sub_ymm)>; 507} 508//===----------------------------------------------------------------------===// 509// AVX-512 BROADCAST MASK TO VECTOR REGISTER 510//--- 511 512multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr, 513 RegisterClass DstRC, RegisterClass KRC, 514 ValueType OpVT, ValueType SrcVT> { 515def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src), 516 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), 517 []>, EVEX; 518} 519 520defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512, 521 VK16, v16i32, v16i1>, EVEX_V512; 522defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512, 523 VK8, v8i64, v8i1>, EVEX_V512, VEX_W; 524 525//===----------------------------------------------------------------------===// 526// AVX-512 - VPERM 527// 528// -- immediate form -- 529multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC, 530 SDNode OpNode, PatFrag mem_frag, 531 X86MemOperand x86memop, ValueType OpVT> { 532 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst), 533 (ins RC:$src1, i8imm:$src2), 534 !strconcat(OpcodeStr, 535 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), 536 [(set RC:$dst, 537 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>, 538 EVEX; 539 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst), 540 (ins x86memop:$src1, i8imm:$src2), 541 !strconcat(OpcodeStr, 542 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), 543 [(set RC:$dst, 544 (OpVT (OpNode (mem_frag addr:$src1), 545 (i8 imm:$src2))))]>, EVEX; 546} 547 548defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64, 549 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; 550let ExeDomain = SSEPackedDouble in 551defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64, 552 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; 553 554// -- VPERM - register form -- 555multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC, 556 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> { 557 558 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), 559 (ins RC:$src1, RC:$src2), 560 !strconcat(OpcodeStr, 561 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), 562 [(set RC:$dst, 563 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V; 564 565 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), 566 (ins RC:$src1, x86memop:$src2), 567 !strconcat(OpcodeStr, 568 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), 569 [(set RC:$dst, 570 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>, 571 EVEX_4V; 572} 573 574defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem, 575 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>; 576defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem, 577 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; 578let ExeDomain = SSEPackedSingle in 579defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem, 580 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>; 581let ExeDomain = SSEPackedDouble in 582defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem, 583 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; 584 585// -- VPERM2I - 3 source operands form -- 586multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC, 587 PatFrag mem_frag, X86MemOperand x86memop, 588 SDNode OpNode, ValueType OpVT> { 589let Constraints = "$src1 = $dst" in { 590 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), 591 (ins RC:$src1, RC:$src2, RC:$src3), 592 !strconcat(OpcodeStr, 593 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"), 594 [(set RC:$dst, 595 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>, 596 EVEX_4V; 597 598 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), 599 (ins RC:$src1, RC:$src2, x86memop:$src3), 600 !strconcat(OpcodeStr, 601 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"), 602 [(set RC:$dst, 603 (OpVT (OpNode RC:$src1, RC:$src2, 604 (mem_frag addr:$src3))))]>, EVEX_4V; 605 } 606} 607defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem, 608 X86VPermiv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>; 609defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem, 610 X86VPermiv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; 611defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem, 612 X86VPermiv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>; 613defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem, 614 X86VPermiv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; 615 616defm VPERMT2D : avx512_perm_3src<0x7E, "vpermt2d", VR512, memopv16i32, i512mem, 617 X86VPermv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>; 618defm VPERMT2Q : avx512_perm_3src<0x7E, "vpermt2q", VR512, memopv8i64, i512mem, 619 X86VPermv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; 620defm VPERMT2PS : avx512_perm_3src<0x7F, "vpermt2ps", VR512, memopv16f32, i512mem, 621 X86VPermv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>; 622defm VPERMT2PD : avx512_perm_3src<0x7F, "vpermt2pd", VR512, memopv8f64, i512mem, 623 X86VPermv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; 624//===----------------------------------------------------------------------===// 625// AVX-512 - BLEND using mask 626// 627multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, 628 RegisterClass KRC, RegisterClass RC, 629 X86MemOperand x86memop, PatFrag mem_frag, 630 SDNode OpNode, ValueType vt> { 631 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), 632 (ins KRC:$mask, RC:$src1, RC:$src2), 633 !strconcat(OpcodeStr, 634 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"), 635 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2), 636 (vt RC:$src1)))]>, EVEX_4V, EVEX_K; 637 let mayLoad = 1 in 638 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), 639 (ins KRC:$mask, RC:$src1, x86memop:$src2), 640 !strconcat(OpcodeStr, 641 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"), 642 []>, EVEX_4V, EVEX_K; 643} 644 645let ExeDomain = SSEPackedSingle in 646defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps", 647 VK16WM, VR512, f512mem, 648 memopv16f32, vselect, v16f32>, 649 EVEX_CD8<32, CD8VF>, EVEX_V512; 650let ExeDomain = SSEPackedDouble in 651defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd", 652 VK8WM, VR512, f512mem, 653 memopv8f64, vselect, v8f64>, 654 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512; 655 656def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1), 657 (v16f32 VR512:$src2), (i16 GR16:$mask))), 658 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), 659 VR512:$src1, VR512:$src2)>; 660 661def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1), 662 (v8f64 VR512:$src2), (i8 GR8:$mask))), 663 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), 664 VR512:$src1, VR512:$src2)>; 665 666defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd", 667 VK16WM, VR512, f512mem, 668 memopv16i32, vselect, v16i32>, 669 EVEX_CD8<32, CD8VF>, EVEX_V512; 670 671defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq", 672 VK8WM, VR512, f512mem, 673 memopv8i64, vselect, v8i64>, 674 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512; 675 676def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1), 677 (v16i32 VR512:$src2), (i16 GR16:$mask))), 678 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16), 679 VR512:$src1, VR512:$src2)>; 680 681def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1), 682 (v8i64 VR512:$src2), (i8 GR8:$mask))), 683 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8), 684 VR512:$src1, VR512:$src2)>; 685 686let Predicates = [HasAVX512] in { 687def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1), 688 (v8f32 VR256X:$src2))), 689 (EXTRACT_SUBREG 690 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM), 691 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)), 692 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>; 693 694def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1), 695 (v8i32 VR256X:$src2))), 696 (EXTRACT_SUBREG 697 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM), 698 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)), 699 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>; 700} 701//===----------------------------------------------------------------------===// 702// Compare Instructions 703//===----------------------------------------------------------------------===// 704 705// avx512_cmp_scalar - AVX512 CMPSS and CMPSD 706multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop, 707 Operand CC, SDNode OpNode, ValueType VT, 708 PatFrag ld_frag, string asm, string asm_alt> { 709 def rr : AVX512Ii8<0xC2, MRMSrcReg, 710 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm, 711 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))], 712 IIC_SSE_ALU_F32S_RR>, EVEX_4V; 713 def rm : AVX512Ii8<0xC2, MRMSrcMem, 714 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm, 715 [(set VK1:$dst, (OpNode (VT RC:$src1), 716 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V; 717 let isAsmParserOnly = 1, hasSideEffects = 0 in { 718 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg, 719 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc), 720 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V; 721 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem, 722 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc), 723 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V; 724 } 725} 726 727let Predicates = [HasAVX512] in { 728defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32, 729 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", 730 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">, 731 XS; 732defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64, 733 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}", 734 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">, 735 XD, VEX_W; 736} 737 738multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC, 739 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag, 740 SDNode OpNode, ValueType vt> { 741 def rr : AVX512BI<opc, MRMSrcReg, 742 (outs KRC:$dst), (ins RC:$src1, RC:$src2), 743 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), 744 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))], 745 IIC_SSE_ALU_F32P_RR>, EVEX_4V; 746 def rm : AVX512BI<opc, MRMSrcMem, 747 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2), 748 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), 749 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))], 750 IIC_SSE_ALU_F32P_RM>, EVEX_4V; 751} 752 753defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem, 754 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512, 755 EVEX_CD8<32, CD8VF>; 756defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem, 757 memopv8i64, X86pcmpeqm, v8i64>, T8PD, EVEX_V512, 758 VEX_W, EVEX_CD8<64, CD8VF>; 759 760defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem, 761 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512, 762 EVEX_CD8<32, CD8VF>; 763defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem, 764 memopv8i64, X86pcmpgtm, v8i64>, T8PD, EVEX_V512, 765 VEX_W, EVEX_CD8<64, CD8VF>; 766 767def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))), 768 (COPY_TO_REGCLASS (VPCMPGTDZrr 769 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)), 770 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>; 771 772def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))), 773 (COPY_TO_REGCLASS (VPCMPEQDZrr 774 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)), 775 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>; 776 777multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC, 778 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag, 779 SDNode OpNode, ValueType vt, Operand CC, string asm, 780 string asm_alt> { 781 def rri : AVX512AIi8<opc, MRMSrcReg, 782 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm, 783 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))], 784 IIC_SSE_ALU_F32P_RR>, EVEX_4V; 785 def rmi : AVX512AIi8<opc, MRMSrcMem, 786 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm, 787 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2), 788 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V; 789 // Accept explicit immediate argument form instead of comparison code. 790 let isAsmParserOnly = 1, hasSideEffects = 0 in { 791 def rri_alt : AVX512AIi8<opc, MRMSrcReg, 792 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc), 793 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V; 794 def rmi_alt : AVX512AIi8<opc, MRMSrcMem, 795 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc), 796 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V; 797 } 798} 799 800defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32, 801 X86cmpm, v16i32, AVXCC, 802 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}", 803 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">, 804 EVEX_V512, EVEX_CD8<32, CD8VF>; 805defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32, 806 X86cmpmu, v16i32, AVXCC, 807 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}", 808 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">, 809 EVEX_V512, EVEX_CD8<32, CD8VF>; 810 811defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64, 812 X86cmpm, v8i64, AVXCC, 813 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}", 814 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">, 815 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>; 816defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64, 817 X86cmpmu, v8i64, AVXCC, 818 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}", 819 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">, 820 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>; 821 822// avx512_cmp_packed - sse 1 & 2 compare packed instructions 823multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC, 824 X86MemOperand x86memop, ValueType vt, 825 string suffix, Domain d> { 826 def rri : AVX512PIi8<0xC2, MRMSrcReg, 827 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc), 828 !strconcat("vcmp${cc}", suffix, 829 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), 830 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>; 831 def rrib: AVX512PIi8<0xC2, MRMSrcReg, 832 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc), 833 !strconcat("vcmp${cc}", suffix, 834 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"), 835 [], d>, EVEX_B; 836 def rmi : AVX512PIi8<0xC2, MRMSrcMem, 837 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc), 838 !strconcat("vcmp${cc}", suffix, 839 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"), 840 [(set KRC:$dst, 841 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>; 842 843 // Accept explicit immediate argument form instead of comparison code. 844 let isAsmParserOnly = 1, hasSideEffects = 0 in { 845 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg, 846 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc), 847 !strconcat("vcmp", suffix, 848 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>; 849 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem, 850 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc), 851 !strconcat("vcmp", suffix, 852 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>; 853 } 854} 855 856defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32, 857 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512, 858 EVEX_CD8<32, CD8VF>; 859defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64, 860 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512, 861 EVEX_CD8<64, CD8VF>; 862 863def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)), 864 (COPY_TO_REGCLASS (VCMPPSZrri 865 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)), 866 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)), 867 imm:$cc), VK8)>; 868def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)), 869 (COPY_TO_REGCLASS (VPCMPDZrri 870 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)), 871 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)), 872 imm:$cc), VK8)>; 873def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)), 874 (COPY_TO_REGCLASS (VPCMPUDZrri 875 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)), 876 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)), 877 imm:$cc), VK8)>; 878 879def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1), 880 (v16f32 VR512:$src2), imm:$cc, (i16 -1), 881 FROUND_NO_EXC)), 882 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2, 883 (I8Imm imm:$cc)), GR16)>; 884 885def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1), 886 (v8f64 VR512:$src2), imm:$cc, (i8 -1), 887 FROUND_NO_EXC)), 888 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2, 889 (I8Imm imm:$cc)), GR8)>; 890 891def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1), 892 (v16f32 VR512:$src2), imm:$cc, (i16 -1), 893 FROUND_CURRENT)), 894 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2, 895 (I8Imm imm:$cc)), GR16)>; 896 897def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1), 898 (v8f64 VR512:$src2), imm:$cc, (i8 -1), 899 FROUND_CURRENT)), 900 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2, 901 (I8Imm imm:$cc)), GR8)>; 902 903// Mask register copy, including 904// - copy between mask registers 905// - load/store mask registers 906// - copy from GPR to mask register and vice versa 907// 908multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk, 909 string OpcodeStr, RegisterClass KRC, 910 ValueType vt, X86MemOperand x86memop> { 911 let hasSideEffects = 0 in { 912 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src), 913 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>; 914 let mayLoad = 1 in 915 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src), 916 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), 917 [(set KRC:$dst, (vt (load addr:$src)))]>; 918 let mayStore = 1 in 919 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src), 920 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>; 921 } 922} 923 924multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk, 925 string OpcodeStr, 926 RegisterClass KRC, RegisterClass GRC> { 927 let hasSideEffects = 0 in { 928 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src), 929 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>; 930 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src), 931 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>; 932 } 933} 934 935let Predicates = [HasAVX512] in { 936 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>, 937 VEX, PS; 938 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>, 939 VEX, PS; 940} 941 942let Predicates = [HasAVX512] in { 943 // GR16 from/to 16-bit mask 944 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))), 945 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>; 946 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))), 947 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>; 948 949 // Store kreg in memory 950 def : Pat<(store (v16i1 VK16:$src), addr:$dst), 951 (KMOVWmk addr:$dst, VK16:$src)>; 952 953 def : Pat<(store VK8:$src, addr:$dst), 954 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>; 955 956 def : Pat<(i1 (load addr:$src)), 957 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>; 958 959 def : Pat<(v8i1 (load addr:$src)), 960 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>; 961 962 def : Pat<(i1 (trunc (i32 GR32:$src))), 963 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>; 964 965 def : Pat<(i1 (trunc (i8 GR8:$src))), 966 (COPY_TO_REGCLASS 967 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))), 968 VK1)>; 969 def : Pat<(i1 (trunc (i16 GR16:$src))), 970 (COPY_TO_REGCLASS 971 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))), 972 VK1)>; 973 974 def : Pat<(i32 (zext VK1:$src)), 975 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>; 976 def : Pat<(i8 (zext VK1:$src)), 977 (EXTRACT_SUBREG 978 (AND32ri (KMOVWrk 979 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>; 980 def : Pat<(i64 (zext VK1:$src)), 981 (AND64ri8 (SUBREG_TO_REG (i64 0), 982 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>; 983 def : Pat<(i16 (zext VK1:$src)), 984 (EXTRACT_SUBREG 985 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), 986 sub_16bit)>; 987} 988// With AVX-512 only, 8-bit mask is promoted to 16-bit mask. 989let Predicates = [HasAVX512] in { 990 // GR from/to 8-bit mask without native support 991 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))), 992 (COPY_TO_REGCLASS 993 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)), 994 VK8)>; 995 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))), 996 (EXTRACT_SUBREG 997 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)), 998 sub_8bit)>; 999 1000 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))), 1001 (COPY_TO_REGCLASS VK16:$src, VK1)>; 1002 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))), 1003 (COPY_TO_REGCLASS VK8:$src, VK1)>; 1004 1005} 1006 1007// Mask unary operation 1008// - KNOT 1009multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr, 1010 RegisterClass KRC, SDPatternOperator OpNode> { 1011 let Predicates = [HasAVX512] in 1012 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src), 1013 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), 1014 [(set KRC:$dst, (OpNode KRC:$src))]>; 1015} 1016 1017multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr, 1018 SDPatternOperator OpNode> { 1019 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>, 1020 VEX, PS; 1021} 1022 1023defm KNOT : avx512_mask_unop_w<0x44, "knot", not>; 1024 1025multiclass avx512_mask_unop_int<string IntName, string InstName> { 1026 let Predicates = [HasAVX512] in 1027 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w") 1028 (i16 GR16:$src)), 1029 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr") 1030 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>; 1031} 1032defm : avx512_mask_unop_int<"knot", "KNOT">; 1033 1034def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>; 1035def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), 1036 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>; 1037 1038// With AVX-512, 8-bit mask is promoted to 16-bit mask. 1039def : Pat<(not VK8:$src), 1040 (COPY_TO_REGCLASS 1041 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>; 1042 1043// Mask binary operation 1044// - KAND, KANDN, KOR, KXNOR, KXOR 1045multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr, 1046 RegisterClass KRC, SDPatternOperator OpNode> { 1047 let Predicates = [HasAVX512] in 1048 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2), 1049 !strconcat(OpcodeStr, 1050 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), 1051 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>; 1052} 1053 1054multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr, 1055 SDPatternOperator OpNode> { 1056 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>, 1057 VEX_4V, VEX_L, PS; 1058} 1059 1060def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>; 1061def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>; 1062 1063let isCommutable = 1 in { 1064 defm KAND : avx512_mask_binop_w<0x41, "kand", and>; 1065 let isCommutable = 0 in 1066 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>; 1067 defm KOR : avx512_mask_binop_w<0x45, "kor", or>; 1068 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>; 1069 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>; 1070} 1071 1072def : Pat<(xor VK1:$src1, VK1:$src2), 1073 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16), 1074 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>; 1075 1076def : Pat<(or VK1:$src1, VK1:$src2), 1077 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16), 1078 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>; 1079 1080def : Pat<(and VK1:$src1, VK1:$src2), 1081 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16), 1082 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>; 1083 1084multiclass avx512_mask_binop_int<string IntName, string InstName> { 1085 let Predicates = [HasAVX512] in 1086 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w") 1087 (i16 GR16:$src1), (i16 GR16:$src2)), 1088 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr") 1089 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)), 1090 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>; 1091} 1092 1093defm : avx512_mask_binop_int<"kand", "KAND">; 1094defm : avx512_mask_binop_int<"kandn", "KANDN">; 1095defm : avx512_mask_binop_int<"kor", "KOR">; 1096defm : avx512_mask_binop_int<"kxnor", "KXNOR">; 1097defm : avx512_mask_binop_int<"kxor", "KXOR">; 1098 1099// With AVX-512, 8-bit mask is promoted to 16-bit mask. 1100multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> { 1101 let Predicates = [HasAVX512] in 1102 def : Pat<(OpNode VK8:$src1, VK8:$src2), 1103 (COPY_TO_REGCLASS 1104 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16), 1105 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>; 1106} 1107 1108defm : avx512_binop_pat<and, KANDWrr>; 1109defm : avx512_binop_pat<andn, KANDNWrr>; 1110defm : avx512_binop_pat<or, KORWrr>; 1111defm : avx512_binop_pat<xnor, KXNORWrr>; 1112defm : avx512_binop_pat<xor, KXORWrr>; 1113 1114// Mask unpacking 1115multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr, 1116 RegisterClass KRC> { 1117 let Predicates = [HasAVX512] in 1118 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2), 1119 !strconcat(OpcodeStr, 1120 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>; 1121} 1122 1123multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> { 1124 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>, 1125 VEX_4V, VEX_L, PD; 1126} 1127 1128defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">; 1129def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))), 1130 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16), 1131 (COPY_TO_REGCLASS VK8:$src1, VK16))>; 1132 1133 1134multiclass avx512_mask_unpck_int<string IntName, string InstName> { 1135 let Predicates = [HasAVX512] in 1136 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw") 1137 (i16 GR16:$src1), (i16 GR16:$src2)), 1138 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr") 1139 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)), 1140 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>; 1141} 1142defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">; 1143 1144// Mask bit testing 1145multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC, 1146 SDNode OpNode> { 1147 let Predicates = [HasAVX512], Defs = [EFLAGS] in 1148 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2), 1149 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"), 1150 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>; 1151} 1152 1153multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> { 1154 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>, 1155 VEX, PS; 1156} 1157 1158defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>; 1159 1160def : Pat<(X86cmp VK1:$src1, (i1 0)), 1161 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16), 1162 (COPY_TO_REGCLASS VK1:$src1, VK16))>; 1163 1164// Mask shift 1165multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC, 1166 SDNode OpNode> { 1167 let Predicates = [HasAVX512] in 1168 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm), 1169 !strconcat(OpcodeStr, 1170 " \t{$imm, $src, $dst|$dst, $src, $imm}"), 1171 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>; 1172} 1173 1174multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr, 1175 SDNode OpNode> { 1176 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>, 1177 VEX, TAPD, VEX_W; 1178} 1179 1180defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>; 1181defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>; 1182 1183// Mask setting all 0s or 1s 1184multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> { 1185 let Predicates = [HasAVX512] in 1186 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in 1187 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "", 1188 [(set KRC:$dst, (VT Val))]>; 1189} 1190 1191multiclass avx512_mask_setop_w<PatFrag Val> { 1192 defm B : avx512_mask_setop<VK8, v8i1, Val>; 1193 defm W : avx512_mask_setop<VK16, v16i1, Val>; 1194} 1195 1196defm KSET0 : avx512_mask_setop_w<immAllZerosV>; 1197defm KSET1 : avx512_mask_setop_w<immAllOnesV>; 1198 1199// With AVX-512 only, 8-bit mask is promoted to 16-bit mask. 1200let Predicates = [HasAVX512] in { 1201 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>; 1202 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>; 1203 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>; 1204 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>; 1205 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>; 1206} 1207def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))), 1208 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>; 1209 1210def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))), 1211 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>; 1212 1213def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))), 1214 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>; 1215 1216def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))), 1217 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>; 1218 1219def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))), 1220 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>; 1221//===----------------------------------------------------------------------===// 1222// AVX-512 - Aligned and unaligned load and store 1223// 1224 1225multiclass avx512_load<bits<8> opc, RegisterClass RC, RegisterClass KRC, 1226 X86MemOperand x86memop, PatFrag ld_frag, 1227 string asm, Domain d, 1228 ValueType vt, bit IsReMaterializable = 1> { 1229let hasSideEffects = 0 in { 1230 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src), 1231 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>, 1232 EVEX; 1233 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src), 1234 !strconcat(asm, 1235 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"), 1236 [], d>, EVEX, EVEX_KZ; 1237 } 1238 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in 1239 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src), 1240 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), 1241 [(set (vt RC:$dst), (ld_frag addr:$src))], d>, EVEX; 1242 let Constraints = "$src1 = $dst", hasSideEffects = 0 in { 1243 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), 1244 (ins RC:$src1, KRC:$mask, RC:$src2), 1245 !strconcat(asm, 1246 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>, 1247 EVEX, EVEX_K; 1248 let mayLoad = 1 in 1249 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), 1250 (ins RC:$src1, KRC:$mask, x86memop:$src2), 1251 !strconcat(asm, 1252 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), 1253 [], d>, EVEX, EVEX_K; 1254 } 1255 let mayLoad = 1 in 1256 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), 1257 (ins KRC:$mask, x86memop:$src2), 1258 !strconcat(asm, 1259 " \t{$src2, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src2}"), 1260 [], d>, EVEX, EVEX_KZ; 1261} 1262 1263multiclass avx512_store<bits<8> opc, RegisterClass RC, RegisterClass KRC, 1264 X86MemOperand x86memop, PatFrag store_frag, 1265 string asm, Domain d, ValueType vt> { 1266 let isAsmParserOnly = 1, hasSideEffects = 0 in { 1267 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src), 1268 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>, 1269 EVEX; 1270 let Constraints = "$src1 = $dst" in 1271 def alt_rrk : AVX512PI<opc, MRMDestReg, (outs RC:$dst), 1272 (ins RC:$src1, KRC:$mask, RC:$src2), 1273 !strconcat(asm, 1274 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>, 1275 EVEX, EVEX_K; 1276 def alt_rrkz : AVX512PI<opc, MRMDestReg, (outs RC:$dst), 1277 (ins KRC:$mask, RC:$src), 1278 !strconcat(asm, 1279 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"), 1280 [], d>, EVEX, EVEX_KZ; 1281 } 1282 let mayStore = 1 in { 1283 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src), 1284 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), 1285 [(store_frag (vt RC:$src), addr:$dst)], d>, EVEX; 1286 def mrk : AVX512PI<opc, MRMDestMem, (outs), 1287 (ins x86memop:$dst, KRC:$mask, RC:$src), 1288 !strconcat(asm, 1289 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"), 1290 [], d>, EVEX, EVEX_K; 1291 def mrkz : AVX512PI<opc, MRMDestMem, (outs), 1292 (ins x86memop:$dst, KRC:$mask, RC:$src), 1293 !strconcat(asm, 1294 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"), 1295 [], d>, EVEX, EVEX_KZ; 1296 } 1297} 1298 1299defm VMOVAPSZ : avx512_load<0x28, VR512, VK16WM, f512mem, alignedloadv16f32, 1300 "vmovaps", SSEPackedSingle, v16f32>, 1301 avx512_store<0x29, VR512, VK16WM, f512mem, alignedstore512, 1302 "vmovaps", SSEPackedSingle, v16f32>, 1303 PS, EVEX_V512, EVEX_CD8<32, CD8VF>; 1304defm VMOVAPDZ : avx512_load<0x28, VR512, VK8WM, f512mem, alignedloadv8f64, 1305 "vmovapd", SSEPackedDouble, v8f64>, 1306 avx512_store<0x29, VR512, VK8WM, f512mem, alignedstore512, 1307 "vmovapd", SSEPackedDouble, v8f64>, 1308 PD, EVEX_V512, VEX_W, 1309 EVEX_CD8<64, CD8VF>; 1310defm VMOVUPSZ : avx512_load<0x10, VR512, VK16WM, f512mem, loadv16f32, 1311 "vmovups", SSEPackedSingle, v16f32>, 1312 avx512_store<0x11, VR512, VK16WM, f512mem, store, 1313 "vmovups", SSEPackedSingle, v16f32>, 1314 PS, EVEX_V512, EVEX_CD8<32, CD8VF>; 1315defm VMOVUPDZ : avx512_load<0x10, VR512, VK8WM, f512mem, loadv8f64, 1316 "vmovupd", SSEPackedDouble, v8f64, 0>, 1317 avx512_store<0x11, VR512, VK8WM, f512mem, store, 1318 "vmovupd", SSEPackedDouble, v8f64>, 1319 PD, EVEX_V512, VEX_W, 1320 EVEX_CD8<64, CD8VF>; 1321def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr, 1322 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)), 1323 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>; 1324 1325def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr, 1326 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)), 1327 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>; 1328 1329def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src), 1330 GR16:$mask), 1331 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), 1332 VR512:$src)>; 1333def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src), 1334 GR8:$mask), 1335 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), 1336 VR512:$src)>; 1337 1338defm VMOVDQA32: avx512_load<0x6F, VR512, VK16WM, i512mem, alignedloadv16i32, 1339 "vmovdqa32", SSEPackedInt, v16i32>, 1340 avx512_store<0x7F, VR512, VK16WM, i512mem, alignedstore512, 1341 "vmovdqa32", SSEPackedInt, v16i32>, 1342 PD, EVEX_V512, EVEX_CD8<32, CD8VF>; 1343defm VMOVDQA64: avx512_load<0x6F, VR512, VK8WM, i512mem, alignedloadv8i64, 1344 "vmovdqa64", SSEPackedInt, v8i64>, 1345 avx512_store<0x7F, VR512, VK8WM, i512mem, alignedstore512, 1346 "vmovdqa64", SSEPackedInt, v8i64>, 1347 PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>; 1348defm VMOVDQU32: avx512_load<0x6F, VR512, VK16WM, i512mem, load, 1349 "vmovdqu32", SSEPackedInt, v16i32>, 1350 avx512_store<0x7F, VR512, VK16WM, i512mem, store, 1351 "vmovdqu32", SSEPackedInt, v16i32>, 1352 XS, EVEX_V512, EVEX_CD8<32, CD8VF>; 1353defm VMOVDQU64: avx512_load<0x6F, VR512, VK8WM, i512mem, load, 1354 "vmovdqu64", SSEPackedInt, v8i64>, 1355 avx512_store<0x7F, VR512, VK8WM, i512mem, store, 1356 "vmovdqu64", SSEPackedInt, v8i64>, 1357 XS, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>; 1358 1359let AddedComplexity = 20 in { 1360def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src), 1361 (bc_v8i64 (v16i32 immAllZerosV)))), 1362 (VMOVDQU64rrkz VK8WM:$mask, VR512:$src)>; 1363 1364def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)), 1365 (v8i64 VR512:$src))), 1366 (VMOVDQU64rrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)), 1367 VK8), VR512:$src)>; 1368 1369def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src), 1370 (v16i32 immAllZerosV))), 1371 (VMOVDQU32rrkz VK16WM:$mask, VR512:$src)>; 1372 1373def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV), 1374 (v16i32 VR512:$src))), 1375 (VMOVDQU32rrkz (KNOTWrr VK16WM:$mask), VR512:$src)>; 1376 1377def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1), 1378 (v16f32 VR512:$src2))), 1379 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>; 1380def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1), 1381 (v8f64 VR512:$src2))), 1382 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>; 1383def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1), 1384 (v16i32 VR512:$src2))), 1385 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>; 1386def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1), 1387 (v8i64 VR512:$src2))), 1388 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>; 1389} 1390// Move Int Doubleword to Packed Double Int 1391// 1392def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src), 1393 "vmovd\t{$src, $dst|$dst, $src}", 1394 [(set VR128X:$dst, 1395 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>, 1396 EVEX, VEX_LIG; 1397def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src), 1398 "vmovd\t{$src, $dst|$dst, $src}", 1399 [(set VR128X:$dst, 1400 (v4i32 (scalar_to_vector (loadi32 addr:$src))))], 1401 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>; 1402def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src), 1403 "vmovq\t{$src, $dst|$dst, $src}", 1404 [(set VR128X:$dst, 1405 (v2i64 (scalar_to_vector GR64:$src)))], 1406 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG; 1407let isCodeGenOnly = 1 in { 1408def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src), 1409 "vmovq\t{$src, $dst|$dst, $src}", 1410 [(set FR64:$dst, (bitconvert GR64:$src))], 1411 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>; 1412def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src), 1413 "vmovq\t{$src, $dst|$dst, $src}", 1414 [(set GR64:$dst, (bitconvert FR64:$src))], 1415 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>; 1416} 1417def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src), 1418 "vmovq\t{$src, $dst|$dst, $src}", 1419 [(store (i64 (bitconvert FR64:$src)), addr:$dst)], 1420 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>, 1421 EVEX_CD8<64, CD8VT1>; 1422 1423// Move Int Doubleword to Single Scalar 1424// 1425let isCodeGenOnly = 1 in { 1426def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src), 1427 "vmovd\t{$src, $dst|$dst, $src}", 1428 [(set FR32X:$dst, (bitconvert GR32:$src))], 1429 IIC_SSE_MOVDQ>, EVEX, VEX_LIG; 1430 1431def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src), 1432 "vmovd\t{$src, $dst|$dst, $src}", 1433 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))], 1434 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>; 1435} 1436 1437// Move doubleword from xmm register to r/m32 1438// 1439def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src), 1440 "vmovd\t{$src, $dst|$dst, $src}", 1441 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src), 1442 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, 1443 EVEX, VEX_LIG; 1444def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs), 1445 (ins i32mem:$dst, VR128X:$src), 1446 "vmovd\t{$src, $dst|$dst, $src}", 1447 [(store (i32 (vector_extract (v4i32 VR128X:$src), 1448 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>, 1449 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>; 1450 1451// Move quadword from xmm1 register to r/m64 1452// 1453def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src), 1454 "vmovq\t{$src, $dst|$dst, $src}", 1455 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src), 1456 (iPTR 0)))], 1457 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W, 1458 Requires<[HasAVX512, In64BitMode]>; 1459 1460def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs), 1461 (ins i64mem:$dst, VR128X:$src), 1462 "vmovq\t{$src, $dst|$dst, $src}", 1463 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)), 1464 addr:$dst)], IIC_SSE_MOVDQ>, 1465 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>, 1466 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>; 1467 1468// Move Scalar Single to Double Int 1469// 1470let isCodeGenOnly = 1 in { 1471def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), 1472 (ins FR32X:$src), 1473 "vmovd\t{$src, $dst|$dst, $src}", 1474 [(set GR32:$dst, (bitconvert FR32X:$src))], 1475 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG; 1476def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs), 1477 (ins i32mem:$dst, FR32X:$src), 1478 "vmovd\t{$src, $dst|$dst, $src}", 1479 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)], 1480 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>; 1481} 1482 1483// Move Quadword Int to Packed Quadword Int 1484// 1485def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), 1486 (ins i64mem:$src), 1487 "vmovq\t{$src, $dst|$dst, $src}", 1488 [(set VR128X:$dst, 1489 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, 1490 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>; 1491 1492//===----------------------------------------------------------------------===// 1493// AVX-512 MOVSS, MOVSD 1494//===----------------------------------------------------------------------===// 1495 1496multiclass avx512_move_scalar <string asm, RegisterClass RC, 1497 SDNode OpNode, ValueType vt, 1498 X86MemOperand x86memop, PatFrag mem_pat> { 1499 let hasSideEffects = 0 in { 1500 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2), 1501 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), 1502 [(set VR128X:$dst, (vt (OpNode VR128X:$src1, 1503 (scalar_to_vector RC:$src2))))], 1504 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG; 1505 let Constraints = "$src1 = $dst" in 1506 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst), 1507 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3), 1508 !strconcat(asm, 1509 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"), 1510 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K; 1511 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src), 1512 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), 1513 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>, 1514 EVEX, VEX_LIG; 1515 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src), 1516 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), 1517 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>, 1518 EVEX, VEX_LIG; 1519 } //hasSideEffects = 0 1520} 1521 1522let ExeDomain = SSEPackedSingle in 1523defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem, 1524 loadf32>, XS, EVEX_CD8<32, CD8VT1>; 1525 1526let ExeDomain = SSEPackedDouble in 1527defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem, 1528 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>; 1529 1530def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))), 1531 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X), 1532 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>; 1533 1534def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))), 1535 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X), 1536 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>; 1537 1538// For the disassembler 1539let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { 1540 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst), 1541 (ins VR128X:$src1, FR32X:$src2), 1542 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [], 1543 IIC_SSE_MOV_S_RR>, 1544 XS, EVEX_4V, VEX_LIG; 1545 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst), 1546 (ins VR128X:$src1, FR64X:$src2), 1547 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [], 1548 IIC_SSE_MOV_S_RR>, 1549 XD, EVEX_4V, VEX_LIG, VEX_W; 1550} 1551 1552let Predicates = [HasAVX512] in { 1553 let AddedComplexity = 15 in { 1554 // Move scalar to XMM zero-extended, zeroing a VR128X then do a 1555 // MOVS{S,D} to the lower bits. 1556 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))), 1557 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>; 1558 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))), 1559 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>; 1560 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))), 1561 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>; 1562 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))), 1563 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>; 1564 1565 // Move low f32 and clear high bits. 1566 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))), 1567 (SUBREG_TO_REG (i32 0), 1568 (VMOVSSZrr (v4f32 (V_SET0)), 1569 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>; 1570 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))), 1571 (SUBREG_TO_REG (i32 0), 1572 (VMOVSSZrr (v4i32 (V_SET0)), 1573 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>; 1574 } 1575 1576 let AddedComplexity = 20 in { 1577 // MOVSSrm zeros the high parts of the register; represent this 1578 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0 1579 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))), 1580 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>; 1581 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))), 1582 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>; 1583 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))), 1584 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>; 1585 1586 // MOVSDrm zeros the high parts of the register; represent this 1587 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0 1588 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))), 1589 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>; 1590 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))), 1591 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>; 1592 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))), 1593 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>; 1594 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))), 1595 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>; 1596 def : Pat<(v2f64 (X86vzload addr:$src)), 1597 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>; 1598 1599 // Represent the same patterns above but in the form they appear for 1600 // 256-bit types 1601 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef, 1602 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))), 1603 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>; 1604 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef, 1605 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))), 1606 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>; 1607 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef, 1608 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))), 1609 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>; 1610 } 1611 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef, 1612 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))), 1613 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)), 1614 FR32X:$src)), sub_xmm)>; 1615 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef, 1616 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))), 1617 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)), 1618 FR64X:$src)), sub_xmm)>; 1619 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef, 1620 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))), 1621 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>; 1622 1623 // Move low f64 and clear high bits. 1624 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))), 1625 (SUBREG_TO_REG (i32 0), 1626 (VMOVSDZrr (v2f64 (V_SET0)), 1627 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>; 1628 1629 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))), 1630 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)), 1631 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>; 1632 1633 // Extract and store. 1634 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))), 1635 addr:$dst), 1636 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>; 1637 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))), 1638 addr:$dst), 1639 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>; 1640 1641 // Shuffle with VMOVSS 1642 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)), 1643 (VMOVSSZrr (v4i32 VR128X:$src1), 1644 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>; 1645 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)), 1646 (VMOVSSZrr (v4f32 VR128X:$src1), 1647 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>; 1648 1649 // 256-bit variants 1650 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)), 1651 (SUBREG_TO_REG (i32 0), 1652 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm), 1653 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)), 1654 sub_xmm)>; 1655 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)), 1656 (SUBREG_TO_REG (i32 0), 1657 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm), 1658 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)), 1659 sub_xmm)>; 1660 1661 // Shuffle with VMOVSD 1662 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)), 1663 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>; 1664 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)), 1665 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>; 1666 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)), 1667 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>; 1668 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)), 1669 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>; 1670 1671 // 256-bit variants 1672 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)), 1673 (SUBREG_TO_REG (i32 0), 1674 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm), 1675 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)), 1676 sub_xmm)>; 1677 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)), 1678 (SUBREG_TO_REG (i32 0), 1679 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm), 1680 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)), 1681 sub_xmm)>; 1682 1683 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)), 1684 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>; 1685 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)), 1686 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>; 1687 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)), 1688 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>; 1689 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)), 1690 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>; 1691} 1692 1693let AddedComplexity = 15 in 1694def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst), 1695 (ins VR128X:$src), 1696 "vmovq\t{$src, $dst|$dst, $src}", 1697 [(set VR128X:$dst, (v2i64 (X86vzmovl 1698 (v2i64 VR128X:$src))))], 1699 IIC_SSE_MOVQ_RR>, EVEX, VEX_W; 1700 1701let AddedComplexity = 20 in 1702def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst), 1703 (ins i128mem:$src), 1704 "vmovq\t{$src, $dst|$dst, $src}", 1705 [(set VR128X:$dst, (v2i64 (X86vzmovl 1706 (loadv2i64 addr:$src))))], 1707 IIC_SSE_MOVDQ>, EVEX, VEX_W, 1708 EVEX_CD8<8, CD8VT8>; 1709 1710let Predicates = [HasAVX512] in { 1711 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part. 1712 let AddedComplexity = 20 in { 1713 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))), 1714 (VMOVDI2PDIZrm addr:$src)>; 1715 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))), 1716 (VMOV64toPQIZrr GR64:$src)>; 1717 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))), 1718 (VMOVDI2PDIZrr GR32:$src)>; 1719 1720 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))), 1721 (VMOVDI2PDIZrm addr:$src)>; 1722 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))), 1723 (VMOVDI2PDIZrm addr:$src)>; 1724 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))), 1725 (VMOVZPQILo2PQIZrm addr:$src)>; 1726 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))), 1727 (VMOVZPQILo2PQIZrr VR128X:$src)>; 1728 def : Pat<(v2i64 (X86vzload addr:$src)), 1729 (VMOVZPQILo2PQIZrm addr:$src)>; 1730 } 1731 1732 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext. 1733 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef, 1734 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))), 1735 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>; 1736 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef, 1737 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))), 1738 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>; 1739} 1740 1741def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))), 1742 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>; 1743 1744def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))), 1745 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>; 1746 1747def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))), 1748 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>; 1749 1750def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))), 1751 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>; 1752 1753//===----------------------------------------------------------------------===// 1754// AVX-512 - Integer arithmetic 1755// 1756multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode, 1757 ValueType OpVT, RegisterClass KRC, 1758 RegisterClass RC, PatFrag memop_frag, 1759 X86MemOperand x86memop, PatFrag scalar_mfrag, 1760 X86MemOperand x86scalar_mop, string BrdcstStr, 1761 OpndItins itins, bit IsCommutable = 0> { 1762 let isCommutable = IsCommutable in 1763 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst), 1764 (ins RC:$src1, RC:$src2), 1765 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), 1766 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))], 1767 itins.rr>, EVEX_4V; 1768 let AddedComplexity = 30 in { 1769 let Constraints = "$src0 = $dst" in 1770 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst), 1771 (ins RC:$src0, KRC:$mask, RC:$src1, RC:$src2), 1772 !strconcat(OpcodeStr, 1773 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"), 1774 [(set RC:$dst, (OpVT (vselect KRC:$mask, 1775 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)), 1776 RC:$src0)))], 1777 itins.rr>, EVEX_4V, EVEX_K; 1778 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst), 1779 (ins KRC:$mask, RC:$src1, RC:$src2), 1780 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" , 1781 "|$dst {${mask}} {z}, $src1, $src2}"), 1782 [(set RC:$dst, (OpVT (vselect KRC:$mask, 1783 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)), 1784 (OpVT immAllZerosV))))], 1785 itins.rr>, EVEX_4V, EVEX_KZ; 1786 } 1787 1788 let mayLoad = 1 in { 1789 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst), 1790 (ins RC:$src1, x86memop:$src2), 1791 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), 1792 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))], 1793 itins.rm>, EVEX_4V; 1794 let AddedComplexity = 30 in { 1795 let Constraints = "$src0 = $dst" in 1796 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst), 1797 (ins RC:$src0, KRC:$mask, RC:$src1, x86memop:$src2), 1798 !strconcat(OpcodeStr, 1799 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"), 1800 [(set RC:$dst, (OpVT (vselect KRC:$mask, 1801 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)), 1802 RC:$src0)))], 1803 itins.rm>, EVEX_4V, EVEX_K; 1804 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst), 1805 (ins KRC:$mask, RC:$src1, x86memop:$src2), 1806 !strconcat(OpcodeStr, 1807 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"), 1808 [(set RC:$dst, (OpVT (vselect KRC:$mask, 1809 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)), 1810 (OpVT immAllZerosV))))], 1811 itins.rm>, EVEX_4V, EVEX_KZ; 1812 } 1813 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst), 1814 (ins RC:$src1, x86scalar_mop:$src2), 1815 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr, 1816 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"), 1817 [(set RC:$dst, (OpNode RC:$src1, 1818 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))], 1819 itins.rm>, EVEX_4V, EVEX_B; 1820 let AddedComplexity = 30 in { 1821 let Constraints = "$src0 = $dst" in 1822 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst), 1823 (ins RC:$src0, KRC:$mask, RC:$src1, x86scalar_mop:$src2), 1824 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr, 1825 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", 1826 BrdcstStr, "}"), 1827 [(set RC:$dst, (OpVT (vselect KRC:$mask, 1828 (OpNode (OpVT RC:$src1), 1829 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))), 1830 RC:$src0)))], 1831 itins.rm>, EVEX_4V, EVEX_B, EVEX_K; 1832 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst), 1833 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), 1834 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr, 1835 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}", 1836 BrdcstStr, "}"), 1837 [(set RC:$dst, (OpVT (vselect KRC:$mask, 1838 (OpNode (OpVT RC:$src1), 1839 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))), 1840 (OpVT immAllZerosV))))], 1841 itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ; 1842 } 1843 } 1844} 1845 1846multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT, 1847 ValueType SrcVT, RegisterClass KRC, RegisterClass RC, 1848 PatFrag memop_frag, X86MemOperand x86memop, 1849 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop, 1850 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> { 1851 let isCommutable = IsCommutable in 1852 { 1853 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst), 1854 (ins RC:$src1, RC:$src2), 1855 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), 1856 []>, EVEX_4V; 1857 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst), 1858 (ins KRC:$mask, RC:$src1, RC:$src2), 1859 !strconcat(OpcodeStr, 1860 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"), 1861 [], itins.rr>, EVEX_4V, EVEX_K; 1862 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst), 1863 (ins KRC:$mask, RC:$src1, RC:$src2), 1864 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" , 1865 "|$dst {${mask}} {z}, $src1, $src2}"), 1866 [], itins.rr>, EVEX_4V, EVEX_KZ; 1867 } 1868 let mayLoad = 1 in { 1869 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst), 1870 (ins RC:$src1, x86memop:$src2), 1871 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), 1872 []>, EVEX_4V; 1873 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst), 1874 (ins KRC:$mask, RC:$src1, x86memop:$src2), 1875 !strconcat(OpcodeStr, 1876 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"), 1877 [], itins.rm>, EVEX_4V, EVEX_K; 1878 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst), 1879 (ins KRC:$mask, RC:$src1, x86memop:$src2), 1880 !strconcat(OpcodeStr, 1881 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"), 1882 [], itins.rm>, EVEX_4V, EVEX_KZ; 1883 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst), 1884 (ins RC:$src1, x86scalar_mop:$src2), 1885 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr, 1886 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"), 1887 [], itins.rm>, EVEX_4V, EVEX_B; 1888 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst), 1889 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), 1890 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr, 1891 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", 1892 BrdcstStr, "}"), 1893 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K; 1894 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst), 1895 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), 1896 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr, 1897 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}", 1898 BrdcstStr, "}"), 1899 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ; 1900 } 1901} 1902 1903defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VK16WM, VR512, 1904 memopv16i32, i512mem, loadi32, i32mem, "{1to16}", 1905 SSE_INTALU_ITINS_P, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>; 1906 1907defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VK16WM, VR512, 1908 memopv16i32, i512mem, loadi32, i32mem, "{1to16}", 1909 SSE_INTALU_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>; 1910 1911defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VK16WM, VR512, 1912 memopv16i32, i512mem, loadi32, i32mem, "{1to16}", 1913 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>; 1914 1915defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VK8WM, VR512, 1916 memopv8i64, i512mem, loadi64, i64mem, "{1to8}", 1917 SSE_INTALU_ITINS_P, 1>, EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W; 1918 1919defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VK8WM, VR512, 1920 memopv8i64, i512mem, loadi64, i64mem, "{1to8}", 1921 SSE_INTALU_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; 1922 1923defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512, 1924 memopv8i64, i512mem, loadi64, i64mem, "{1to8}", 1925 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512, 1926 EVEX_CD8<64, CD8VF>, VEX_W; 1927 1928defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512, 1929 memopv8i64, i512mem, loadi64, i64mem, "{1to8}", 1930 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W; 1931 1932def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))), 1933 (VPMULUDQZrr VR512:$src1, VR512:$src2)>; 1934 1935def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1), 1936 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))), 1937 (VPMULUDQZrr VR512:$src1, VR512:$src2)>; 1938def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1), 1939 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))), 1940 (VPMULDQZrr VR512:$src1, VR512:$src2)>; 1941 1942defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VK16WM, VR512, 1943 memopv16i32, i512mem, loadi32, i32mem, "{1to16}", 1944 SSE_INTALU_ITINS_P, 1>, 1945 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>; 1946defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VK8WM, VR512, 1947 memopv8i64, i512mem, loadi64, i64mem, "{1to8}", 1948 SSE_INTALU_ITINS_P, 0>, 1949 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; 1950 1951defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VK16WM, VR512, 1952 memopv16i32, i512mem, loadi32, i32mem, "{1to16}", 1953 SSE_INTALU_ITINS_P, 1>, 1954 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>; 1955defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VK8WM, VR512, 1956 memopv8i64, i512mem, loadi64, i64mem, "{1to8}", 1957 SSE_INTALU_ITINS_P, 0>, 1958 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; 1959 1960defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VK16WM, VR512, 1961 memopv16i32, i512mem, loadi32, i32mem, "{1to16}", 1962 SSE_INTALU_ITINS_P, 1>, 1963 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>; 1964defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VK8WM, VR512, 1965 memopv8i64, i512mem, loadi64, i64mem, "{1to8}", 1966 SSE_INTALU_ITINS_P, 0>, 1967 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; 1968 1969defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VK16WM, VR512, 1970 memopv16i32, i512mem, loadi32, i32mem, "{1to16}", 1971 SSE_INTALU_ITINS_P, 1>, 1972 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>; 1973defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VK8WM, VR512, 1974 memopv8i64, i512mem, loadi64, i64mem, "{1to8}", 1975 SSE_INTALU_ITINS_P, 0>, 1976 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; 1977 1978def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1), 1979 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))), 1980 (VPMAXSDZrr VR512:$src1, VR512:$src2)>; 1981def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1), 1982 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))), 1983 (VPMAXUDZrr VR512:$src1, VR512:$src2)>; 1984def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1), 1985 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))), 1986 (VPMAXSQZrr VR512:$src1, VR512:$src2)>; 1987def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1), 1988 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))), 1989 (VPMAXUQZrr VR512:$src1, VR512:$src2)>; 1990def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1), 1991 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))), 1992 (VPMINSDZrr VR512:$src1, VR512:$src2)>; 1993def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1), 1994 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))), 1995 (VPMINUDZrr VR512:$src1, VR512:$src2)>; 1996def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1), 1997 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))), 1998 (VPMINSQZrr VR512:$src1, VR512:$src2)>; 1999def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1), 2000 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))), 2001 (VPMINUQZrr VR512:$src1, VR512:$src2)>; 2002//===----------------------------------------------------------------------===// 2003// AVX-512 - Unpack Instructions 2004//===----------------------------------------------------------------------===// 2005 2006multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt, 2007 PatFrag mem_frag, RegisterClass RC, 2008 X86MemOperand x86memop, string asm, 2009 Domain d> { 2010 def rr : AVX512PI<opc, MRMSrcReg, 2011 (outs RC:$dst), (ins RC:$src1, RC:$src2), 2012 asm, [(set RC:$dst, 2013 (vt (OpNode RC:$src1, RC:$src2)))], 2014 d>, EVEX_4V; 2015 def rm : AVX512PI<opc, MRMSrcMem, 2016 (outs RC:$dst), (ins RC:$src1, x86memop:$src2), 2017 asm, [(set RC:$dst, 2018 (vt (OpNode RC:$src1, 2019 (bitconvert (mem_frag addr:$src2)))))], 2020 d>, EVEX_4V; 2021} 2022 2023defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64, 2024 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}", 2025 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>; 2026defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64, 2027 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}", 2028 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; 2029defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64, 2030 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}", 2031 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>; 2032defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64, 2033 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}", 2034 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; 2035 2036multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode, 2037 ValueType OpVT, RegisterClass RC, PatFrag memop_frag, 2038 X86MemOperand x86memop> { 2039 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst), 2040 (ins RC:$src1, RC:$src2), 2041 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2042 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))], 2043 IIC_SSE_UNPCK>, EVEX_4V; 2044 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst), 2045 (ins RC:$src1, x86memop:$src2), 2046 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2047 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), 2048 (bitconvert (memop_frag addr:$src2)))))], 2049 IIC_SSE_UNPCK>, EVEX_4V; 2050} 2051defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32, 2052 VR512, memopv16i32, i512mem>, EVEX_V512, 2053 EVEX_CD8<32, CD8VF>; 2054defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64, 2055 VR512, memopv8i64, i512mem>, EVEX_V512, 2056 VEX_W, EVEX_CD8<64, CD8VF>; 2057defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32, 2058 VR512, memopv16i32, i512mem>, EVEX_V512, 2059 EVEX_CD8<32, CD8VF>; 2060defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64, 2061 VR512, memopv8i64, i512mem>, EVEX_V512, 2062 VEX_W, EVEX_CD8<64, CD8VF>; 2063//===----------------------------------------------------------------------===// 2064// AVX-512 - PSHUFD 2065// 2066 2067multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC, 2068 SDNode OpNode, PatFrag mem_frag, 2069 X86MemOperand x86memop, ValueType OpVT> { 2070 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst), 2071 (ins RC:$src1, i8imm:$src2), 2072 !strconcat(OpcodeStr, 2073 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2074 [(set RC:$dst, 2075 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>, 2076 EVEX; 2077 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst), 2078 (ins x86memop:$src1, i8imm:$src2), 2079 !strconcat(OpcodeStr, 2080 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2081 [(set RC:$dst, 2082 (OpVT (OpNode (mem_frag addr:$src1), 2083 (i8 imm:$src2))))]>, EVEX; 2084} 2085 2086defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32, 2087 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>; 2088 2089let ExeDomain = SSEPackedSingle in 2090defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp, 2091 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512, 2092 EVEX_CD8<32, CD8VF>; 2093let ExeDomain = SSEPackedDouble in 2094defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp, 2095 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512, 2096 VEX_W, EVEX_CD8<32, CD8VF>; 2097 2098def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))), 2099 (VPERMILPSZri VR512:$src1, imm:$imm)>; 2100def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))), 2101 (VPERMILPDZri VR512:$src1, imm:$imm)>; 2102 2103//===----------------------------------------------------------------------===// 2104// AVX-512 Logical Instructions 2105//===----------------------------------------------------------------------===// 2106 2107defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VK16WM, VR512, memopv16i32, 2108 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>, 2109 EVEX_V512, EVEX_CD8<32, CD8VF>; 2110defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VK8WM, VR512, memopv8i64, 2111 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>, 2112 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; 2113defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VK16WM, VR512, memopv16i32, 2114 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>, 2115 EVEX_V512, EVEX_CD8<32, CD8VF>; 2116defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VK8WM, VR512, memopv8i64, 2117 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>, 2118 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; 2119defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VK16WM, VR512, memopv16i32, 2120 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>, 2121 EVEX_V512, EVEX_CD8<32, CD8VF>; 2122defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VK8WM, VR512, memopv8i64, 2123 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>, 2124 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; 2125defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VK16WM, VR512, 2126 memopv16i32, i512mem, loadi32, i32mem, "{1to16}", 2127 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>; 2128defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VK8WM, VR512, 2129 memopv8i64, i512mem, loadi64, i64mem, "{1to8}", 2130 SSE_BIT_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; 2131 2132//===----------------------------------------------------------------------===// 2133// AVX-512 FP arithmetic 2134//===----------------------------------------------------------------------===// 2135 2136multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode, 2137 SizeItins itins> { 2138 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X, 2139 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG, 2140 EVEX_CD8<32, CD8VT1>; 2141 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X, 2142 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG, 2143 EVEX_CD8<64, CD8VT1>; 2144} 2145 2146let isCommutable = 1 in { 2147defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>; 2148defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>; 2149defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>; 2150defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>; 2151} 2152let isCommutable = 0 in { 2153defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>; 2154defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>; 2155} 2156 2157multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode, 2158 RegisterClass KRC, 2159 RegisterClass RC, ValueType vt, 2160 X86MemOperand x86memop, PatFrag mem_frag, 2161 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag, 2162 string BrdcstStr, 2163 Domain d, OpndItins itins, bit commutable> { 2164 let isCommutable = commutable in { 2165 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), 2166 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2167 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>, 2168 EVEX_4V; 2169 2170 def rrk: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2), 2171 !strconcat(OpcodeStr, 2172 " \t{$src2, $src1, $dst {${mask}} |$dst {${mask}}, $src1, $src2}"), 2173 [], itins.rr, d>, EVEX_4V, EVEX_K; 2174 2175 def rrkz: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2), 2176 !strconcat(OpcodeStr, 2177 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"), 2178 [], itins.rr, d>, EVEX_4V, EVEX_KZ; 2179 } 2180 2181 let mayLoad = 1 in { 2182 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), 2183 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2184 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], 2185 itins.rm, d>, EVEX_4V; 2186 2187 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst), 2188 (ins RC:$src1, x86scalar_mop:$src2), 2189 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr, 2190 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"), 2191 [(set RC:$dst, (OpNode RC:$src1, 2192 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))], 2193 itins.rm, d>, EVEX_4V, EVEX_B; 2194 2195 def rmk : PI<opc, MRMSrcMem, (outs RC:$dst), 2196 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr, 2197 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"), 2198 [], itins.rm, d>, EVEX_4V, EVEX_K; 2199 2200 def rmkz : PI<opc, MRMSrcMem, (outs RC:$dst), 2201 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr, 2202 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"), 2203 [], itins.rm, d>, EVEX_4V, EVEX_KZ; 2204 2205 def rmbk : PI<opc, MRMSrcMem, (outs RC:$dst), 2206 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr, 2207 " \t{${src2}", BrdcstStr, 2208 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", BrdcstStr, "}"), 2209 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_K; 2210 2211 def rmbkz : PI<opc, MRMSrcMem, (outs RC:$dst), 2212 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr, 2213 " \t{${src2}", BrdcstStr, 2214 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}", 2215 BrdcstStr, "}"), 2216 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_KZ; 2217 } 2218} 2219 2220defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VK16WM, VR512, v16f32, f512mem, 2221 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle, 2222 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>; 2223 2224defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VK8WM, VR512, v8f64, f512mem, 2225 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble, 2226 SSE_ALU_ITINS_P.d, 1>, 2227 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>; 2228 2229defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VK16WM, VR512, v16f32, f512mem, 2230 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle, 2231 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>; 2232defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VK8WM, VR512, v8f64, f512mem, 2233 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble, 2234 SSE_ALU_ITINS_P.d, 1>, 2235 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>; 2236 2237defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VK16WM, VR512, v16f32, f512mem, 2238 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle, 2239 SSE_ALU_ITINS_P.s, 1>, 2240 EVEX_V512, PS, EVEX_CD8<32, CD8VF>; 2241defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VK16WM, VR512, v16f32, f512mem, 2242 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle, 2243 SSE_ALU_ITINS_P.s, 1>, 2244 EVEX_V512, PS, EVEX_CD8<32, CD8VF>; 2245 2246defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VK8WM, VR512, v8f64, f512mem, 2247 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble, 2248 SSE_ALU_ITINS_P.d, 1>, 2249 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>; 2250defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VK8WM, VR512, v8f64, f512mem, 2251 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble, 2252 SSE_ALU_ITINS_P.d, 1>, 2253 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>; 2254 2255defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VK16WM, VR512, v16f32, f512mem, 2256 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle, 2257 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>; 2258defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VK16WM, VR512, v16f32, f512mem, 2259 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle, 2260 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>; 2261 2262defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VK8WM, VR512, v8f64, f512mem, 2263 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble, 2264 SSE_ALU_ITINS_P.d, 0>, 2265 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>; 2266defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VK8WM, VR512, v8f64, f512mem, 2267 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble, 2268 SSE_ALU_ITINS_P.d, 0>, 2269 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>; 2270 2271def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1), 2272 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)), 2273 (i16 -1), FROUND_CURRENT)), 2274 (VMAXPSZrr VR512:$src1, VR512:$src2)>; 2275 2276def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1), 2277 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)), 2278 (i8 -1), FROUND_CURRENT)), 2279 (VMAXPDZrr VR512:$src1, VR512:$src2)>; 2280 2281def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1), 2282 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)), 2283 (i16 -1), FROUND_CURRENT)), 2284 (VMINPSZrr VR512:$src1, VR512:$src2)>; 2285 2286def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1), 2287 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)), 2288 (i8 -1), FROUND_CURRENT)), 2289 (VMINPDZrr VR512:$src1, VR512:$src2)>; 2290//===----------------------------------------------------------------------===// 2291// AVX-512 VPTESTM instructions 2292//===----------------------------------------------------------------------===// 2293 2294multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC, 2295 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag, 2296 SDNode OpNode, ValueType vt> { 2297 def rr : AVX512PI<opc, MRMSrcReg, 2298 (outs KRC:$dst), (ins RC:$src1, RC:$src2), 2299 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2300 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))], 2301 SSEPackedInt>, EVEX_4V; 2302 def rm : AVX512PI<opc, MRMSrcMem, 2303 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2), 2304 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2305 [(set KRC:$dst, (OpNode (vt RC:$src1), 2306 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V; 2307} 2308 2309defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem, 2310 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512, 2311 EVEX_CD8<32, CD8VF>; 2312defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem, 2313 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W, 2314 EVEX_CD8<64, CD8VF>; 2315 2316let Predicates = [HasCDI] in { 2317defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem, 2318 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512, 2319 EVEX_CD8<32, CD8VF>; 2320defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem, 2321 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W, 2322 EVEX_CD8<64, CD8VF>; 2323} 2324 2325def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1), 2326 (v16i32 VR512:$src2), (i16 -1))), 2327 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>; 2328 2329def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1), 2330 (v8i64 VR512:$src2), (i8 -1))), 2331 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>; 2332//===----------------------------------------------------------------------===// 2333// AVX-512 Shift instructions 2334//===----------------------------------------------------------------------===// 2335multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM, 2336 string OpcodeStr, SDNode OpNode, RegisterClass RC, 2337 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag, 2338 RegisterClass KRC> { 2339 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst), 2340 (ins RC:$src1, i8imm:$src2), 2341 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2342 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))], 2343 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V; 2344 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst), 2345 (ins KRC:$mask, RC:$src1, i8imm:$src2), 2346 !strconcat(OpcodeStr, 2347 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"), 2348 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K; 2349 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst), 2350 (ins x86memop:$src1, i8imm:$src2), 2351 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2352 [(set RC:$dst, (OpNode (mem_frag addr:$src1), 2353 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V; 2354 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst), 2355 (ins KRC:$mask, x86memop:$src1, i8imm:$src2), 2356 !strconcat(OpcodeStr, 2357 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"), 2358 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K; 2359} 2360 2361multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode, 2362 RegisterClass RC, ValueType vt, ValueType SrcVT, 2363 PatFrag bc_frag, RegisterClass KRC> { 2364 // src2 is always 128-bit 2365 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst), 2366 (ins RC:$src1, VR128X:$src2), 2367 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2368 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))], 2369 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V; 2370 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst), 2371 (ins KRC:$mask, RC:$src1, VR128X:$src2), 2372 !strconcat(OpcodeStr, 2373 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"), 2374 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K; 2375 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst), 2376 (ins RC:$src1, i128mem:$src2), 2377 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2378 [(set RC:$dst, (vt (OpNode RC:$src1, 2379 (bc_frag (memopv2i64 addr:$src2)))))], 2380 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V; 2381 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst), 2382 (ins KRC:$mask, RC:$src1, i128mem:$src2), 2383 !strconcat(OpcodeStr, 2384 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"), 2385 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K; 2386} 2387 2388defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli, 2389 VR512, v16i32, i512mem, memopv16i32, VK16WM>, 2390 EVEX_V512, EVEX_CD8<32, CD8VF>; 2391defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl, 2392 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512, 2393 EVEX_CD8<32, CD8VQ>; 2394 2395defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli, 2396 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512, 2397 EVEX_CD8<64, CD8VF>, VEX_W; 2398defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl, 2399 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512, 2400 EVEX_CD8<64, CD8VQ>, VEX_W; 2401 2402defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli, 2403 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512, 2404 EVEX_CD8<32, CD8VF>; 2405defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl, 2406 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512, 2407 EVEX_CD8<32, CD8VQ>; 2408 2409defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli, 2410 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512, 2411 EVEX_CD8<64, CD8VF>, VEX_W; 2412defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl, 2413 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512, 2414 EVEX_CD8<64, CD8VQ>, VEX_W; 2415 2416defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai, 2417 VR512, v16i32, i512mem, memopv16i32, VK16WM>, 2418 EVEX_V512, EVEX_CD8<32, CD8VF>; 2419defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra, 2420 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512, 2421 EVEX_CD8<32, CD8VQ>; 2422 2423defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai, 2424 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512, 2425 EVEX_CD8<64, CD8VF>, VEX_W; 2426defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra, 2427 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512, 2428 EVEX_CD8<64, CD8VQ>, VEX_W; 2429 2430//===-------------------------------------------------------------------===// 2431// Variable Bit Shifts 2432//===-------------------------------------------------------------------===// 2433multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode, 2434 RegisterClass RC, ValueType vt, 2435 X86MemOperand x86memop, PatFrag mem_frag> { 2436 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), 2437 (ins RC:$src1, RC:$src2), 2438 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2439 [(set RC:$dst, 2440 (vt (OpNode RC:$src1, (vt RC:$src2))))]>, 2441 EVEX_4V; 2442 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), 2443 (ins RC:$src1, x86memop:$src2), 2444 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2445 [(set RC:$dst, 2446 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>, 2447 EVEX_4V; 2448} 2449 2450defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32, 2451 i512mem, memopv16i32>, EVEX_V512, 2452 EVEX_CD8<32, CD8VF>; 2453defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64, 2454 i512mem, memopv8i64>, EVEX_V512, VEX_W, 2455 EVEX_CD8<64, CD8VF>; 2456defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32, 2457 i512mem, memopv16i32>, EVEX_V512, 2458 EVEX_CD8<32, CD8VF>; 2459defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64, 2460 i512mem, memopv8i64>, EVEX_V512, VEX_W, 2461 EVEX_CD8<64, CD8VF>; 2462defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32, 2463 i512mem, memopv16i32>, EVEX_V512, 2464 EVEX_CD8<32, CD8VF>; 2465defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64, 2466 i512mem, memopv8i64>, EVEX_V512, VEX_W, 2467 EVEX_CD8<64, CD8VF>; 2468 2469//===----------------------------------------------------------------------===// 2470// AVX-512 - MOVDDUP 2471//===----------------------------------------------------------------------===// 2472 2473multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT, 2474 X86MemOperand x86memop, PatFrag memop_frag> { 2475def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src), 2476 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), 2477 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX; 2478def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src), 2479 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), 2480 [(set RC:$dst, 2481 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX; 2482} 2483 2484defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>, 2485 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>; 2486def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))), 2487 (VMOVDDUPZrm addr:$src)>; 2488 2489//===---------------------------------------------------------------------===// 2490// Replicate Single FP - MOVSHDUP and MOVSLDUP 2491//===---------------------------------------------------------------------===// 2492multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr, 2493 ValueType vt, RegisterClass RC, PatFrag mem_frag, 2494 X86MemOperand x86memop> { 2495 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src), 2496 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), 2497 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX; 2498 let mayLoad = 1 in 2499 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src), 2500 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), 2501 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX; 2502} 2503 2504defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup", 2505 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512, 2506 EVEX_CD8<32, CD8VF>; 2507defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup", 2508 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512, 2509 EVEX_CD8<32, CD8VF>; 2510 2511def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>; 2512def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))), 2513 (VMOVSHDUPZrm addr:$src)>; 2514def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>; 2515def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))), 2516 (VMOVSLDUPZrm addr:$src)>; 2517 2518//===----------------------------------------------------------------------===// 2519// Move Low to High and High to Low packed FP Instructions 2520//===----------------------------------------------------------------------===// 2521def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst), 2522 (ins VR128X:$src1, VR128X:$src2), 2523 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}", 2524 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))], 2525 IIC_SSE_MOV_LH>, EVEX_4V; 2526def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst), 2527 (ins VR128X:$src1, VR128X:$src2), 2528 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}", 2529 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))], 2530 IIC_SSE_MOV_LH>, EVEX_4V; 2531 2532let Predicates = [HasAVX512] in { 2533 // MOVLHPS patterns 2534 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)), 2535 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>; 2536 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)), 2537 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>; 2538 2539 // MOVHLPS patterns 2540 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)), 2541 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>; 2542} 2543 2544//===----------------------------------------------------------------------===// 2545// FMA - Fused Multiply Operations 2546// 2547let Constraints = "$src1 = $dst" in { 2548multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, 2549 RegisterClass RC, X86MemOperand x86memop, 2550 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag, 2551 string BrdcstStr, SDNode OpNode, ValueType OpVT> { 2552 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst), 2553 (ins RC:$src1, RC:$src2, RC:$src3), 2554 !strconcat(OpcodeStr," \t{$src3, $src2, $dst|$dst, $src2, $src3}"), 2555 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>; 2556 2557 let mayLoad = 1 in 2558 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst), 2559 (ins RC:$src1, RC:$src2, x86memop:$src3), 2560 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"), 2561 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2, 2562 (mem_frag addr:$src3))))]>; 2563 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst), 2564 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3), 2565 !strconcat(OpcodeStr, " \t{${src3}", BrdcstStr, 2566 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"), 2567 [(set RC:$dst, (OpNode RC:$src1, RC:$src2, 2568 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B; 2569} 2570} // Constraints = "$src1 = $dst" 2571 2572let ExeDomain = SSEPackedSingle in { 2573 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem, 2574 memopv16f32, f32mem, loadf32, "{1to16}", 2575 X86Fmadd, v16f32>, EVEX_V512, 2576 EVEX_CD8<32, CD8VF>; 2577 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem, 2578 memopv16f32, f32mem, loadf32, "{1to16}", 2579 X86Fmsub, v16f32>, EVEX_V512, 2580 EVEX_CD8<32, CD8VF>; 2581 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem, 2582 memopv16f32, f32mem, loadf32, "{1to16}", 2583 X86Fmaddsub, v16f32>, 2584 EVEX_V512, EVEX_CD8<32, CD8VF>; 2585 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem, 2586 memopv16f32, f32mem, loadf32, "{1to16}", 2587 X86Fmsubadd, v16f32>, 2588 EVEX_V512, EVEX_CD8<32, CD8VF>; 2589 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem, 2590 memopv16f32, f32mem, loadf32, "{1to16}", 2591 X86Fnmadd, v16f32>, EVEX_V512, 2592 EVEX_CD8<32, CD8VF>; 2593 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem, 2594 memopv16f32, f32mem, loadf32, "{1to16}", 2595 X86Fnmsub, v16f32>, EVEX_V512, 2596 EVEX_CD8<32, CD8VF>; 2597} 2598let ExeDomain = SSEPackedDouble in { 2599 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem, 2600 memopv8f64, f64mem, loadf64, "{1to8}", 2601 X86Fmadd, v8f64>, EVEX_V512, 2602 VEX_W, EVEX_CD8<64, CD8VF>; 2603 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem, 2604 memopv8f64, f64mem, loadf64, "{1to8}", 2605 X86Fmsub, v8f64>, EVEX_V512, VEX_W, 2606 EVEX_CD8<64, CD8VF>; 2607 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem, 2608 memopv8f64, f64mem, loadf64, "{1to8}", 2609 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W, 2610 EVEX_CD8<64, CD8VF>; 2611 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem, 2612 memopv8f64, f64mem, loadf64, "{1to8}", 2613 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W, 2614 EVEX_CD8<64, CD8VF>; 2615 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem, 2616 memopv8f64, f64mem, loadf64, "{1to8}", 2617 X86Fnmadd, v8f64>, EVEX_V512, VEX_W, 2618 EVEX_CD8<64, CD8VF>; 2619 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem, 2620 memopv8f64, f64mem, loadf64, "{1to8}", 2621 X86Fnmsub, v8f64>, EVEX_V512, VEX_W, 2622 EVEX_CD8<64, CD8VF>; 2623} 2624 2625let Constraints = "$src1 = $dst" in { 2626multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, 2627 RegisterClass RC, X86MemOperand x86memop, 2628 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag, 2629 string BrdcstStr, SDNode OpNode, ValueType OpVT> { 2630 let mayLoad = 1 in 2631 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst), 2632 (ins RC:$src1, RC:$src3, x86memop:$src2), 2633 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"), 2634 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>; 2635 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst), 2636 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2), 2637 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr, 2638 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"), 2639 [(set RC:$dst, (OpNode RC:$src1, 2640 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B; 2641} 2642} // Constraints = "$src1 = $dst" 2643 2644 2645let ExeDomain = SSEPackedSingle in { 2646 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem, 2647 memopv16f32, f32mem, loadf32, "{1to16}", 2648 X86Fmadd, v16f32>, EVEX_V512, 2649 EVEX_CD8<32, CD8VF>; 2650 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem, 2651 memopv16f32, f32mem, loadf32, "{1to16}", 2652 X86Fmsub, v16f32>, EVEX_V512, 2653 EVEX_CD8<32, CD8VF>; 2654 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem, 2655 memopv16f32, f32mem, loadf32, "{1to16}", 2656 X86Fmaddsub, v16f32>, 2657 EVEX_V512, EVEX_CD8<32, CD8VF>; 2658 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem, 2659 memopv16f32, f32mem, loadf32, "{1to16}", 2660 X86Fmsubadd, v16f32>, 2661 EVEX_V512, EVEX_CD8<32, CD8VF>; 2662 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem, 2663 memopv16f32, f32mem, loadf32, "{1to16}", 2664 X86Fnmadd, v16f32>, EVEX_V512, 2665 EVEX_CD8<32, CD8VF>; 2666 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem, 2667 memopv16f32, f32mem, loadf32, "{1to16}", 2668 X86Fnmsub, v16f32>, EVEX_V512, 2669 EVEX_CD8<32, CD8VF>; 2670} 2671let ExeDomain = SSEPackedDouble in { 2672 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem, 2673 memopv8f64, f64mem, loadf64, "{1to8}", 2674 X86Fmadd, v8f64>, EVEX_V512, 2675 VEX_W, EVEX_CD8<64, CD8VF>; 2676 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem, 2677 memopv8f64, f64mem, loadf64, "{1to8}", 2678 X86Fmsub, v8f64>, EVEX_V512, VEX_W, 2679 EVEX_CD8<64, CD8VF>; 2680 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem, 2681 memopv8f64, f64mem, loadf64, "{1to8}", 2682 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W, 2683 EVEX_CD8<64, CD8VF>; 2684 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem, 2685 memopv8f64, f64mem, loadf64, "{1to8}", 2686 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W, 2687 EVEX_CD8<64, CD8VF>; 2688 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem, 2689 memopv8f64, f64mem, loadf64, "{1to8}", 2690 X86Fnmadd, v8f64>, EVEX_V512, VEX_W, 2691 EVEX_CD8<64, CD8VF>; 2692 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem, 2693 memopv8f64, f64mem, loadf64, "{1to8}", 2694 X86Fnmsub, v8f64>, EVEX_V512, VEX_W, 2695 EVEX_CD8<64, CD8VF>; 2696} 2697 2698// Scalar FMA 2699let Constraints = "$src1 = $dst" in { 2700multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode, 2701 RegisterClass RC, ValueType OpVT, 2702 X86MemOperand x86memop, Operand memop, 2703 PatFrag mem_frag> { 2704 let isCommutable = 1 in 2705 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst), 2706 (ins RC:$src1, RC:$src2, RC:$src3), 2707 !strconcat(OpcodeStr, 2708 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"), 2709 [(set RC:$dst, 2710 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>; 2711 let mayLoad = 1 in 2712 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst), 2713 (ins RC:$src1, RC:$src2, f128mem:$src3), 2714 !strconcat(OpcodeStr, 2715 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"), 2716 [(set RC:$dst, 2717 (OpVT (OpNode RC:$src2, RC:$src1, 2718 (mem_frag addr:$src3))))]>; 2719} 2720 2721} // Constraints = "$src1 = $dst" 2722 2723defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X, 2724 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>; 2725defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X, 2726 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>; 2727defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X, 2728 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>; 2729defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X, 2730 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>; 2731defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X, 2732 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>; 2733defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X, 2734 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>; 2735defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X, 2736 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>; 2737defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X, 2738 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>; 2739 2740//===----------------------------------------------------------------------===// 2741// AVX-512 Scalar convert from sign integer to float/double 2742//===----------------------------------------------------------------------===// 2743 2744multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC, 2745 X86MemOperand x86memop, string asm> { 2746let hasSideEffects = 0 in { 2747 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src), 2748 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>, 2749 EVEX_4V; 2750 let mayLoad = 1 in 2751 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), 2752 (ins DstRC:$src1, x86memop:$src), 2753 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>, 2754 EVEX_4V; 2755} // hasSideEffects = 0 2756} 2757let Predicates = [HasAVX512] in { 2758defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">, 2759 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>; 2760defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">, 2761 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>; 2762defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">, 2763 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>; 2764defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">, 2765 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>; 2766 2767def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))), 2768 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>; 2769def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))), 2770 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>; 2771def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))), 2772 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>; 2773def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))), 2774 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>; 2775 2776def : Pat<(f32 (sint_to_fp GR32:$src)), 2777 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>; 2778def : Pat<(f32 (sint_to_fp GR64:$src)), 2779 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>; 2780def : Pat<(f64 (sint_to_fp GR32:$src)), 2781 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>; 2782def : Pat<(f64 (sint_to_fp GR64:$src)), 2783 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>; 2784 2785defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">, 2786 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>; 2787defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">, 2788 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>; 2789defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">, 2790 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>; 2791defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">, 2792 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>; 2793 2794def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))), 2795 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>; 2796def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))), 2797 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>; 2798def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))), 2799 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>; 2800def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))), 2801 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>; 2802 2803def : Pat<(f32 (uint_to_fp GR32:$src)), 2804 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>; 2805def : Pat<(f32 (uint_to_fp GR64:$src)), 2806 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>; 2807def : Pat<(f64 (uint_to_fp GR32:$src)), 2808 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>; 2809def : Pat<(f64 (uint_to_fp GR64:$src)), 2810 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>; 2811} 2812 2813//===----------------------------------------------------------------------===// 2814// AVX-512 Scalar convert from float/double to integer 2815//===----------------------------------------------------------------------===// 2816multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC, 2817 Intrinsic Int, Operand memop, ComplexPattern mem_cpat, 2818 string asm> { 2819let hasSideEffects = 0 in { 2820 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), 2821 !strconcat(asm," \t{$src, $dst|$dst, $src}"), 2822 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG, 2823 Requires<[HasAVX512]>; 2824 let mayLoad = 1 in 2825 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src), 2826 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG, 2827 Requires<[HasAVX512]>; 2828} // hasSideEffects = 0 2829} 2830let Predicates = [HasAVX512] in { 2831// Convert float/double to signed/unsigned int 32/64 2832defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si, 2833 ssmem, sse_load_f32, "cvtss2si">, 2834 XS, EVEX_CD8<32, CD8VT1>; 2835defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64, 2836 ssmem, sse_load_f32, "cvtss2si">, 2837 XS, VEX_W, EVEX_CD8<32, CD8VT1>; 2838defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi, 2839 ssmem, sse_load_f32, "cvtss2usi">, 2840 XS, EVEX_CD8<32, CD8VT1>; 2841defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64, 2842 int_x86_avx512_cvtss2usi64, ssmem, 2843 sse_load_f32, "cvtss2usi">, XS, VEX_W, 2844 EVEX_CD8<32, CD8VT1>; 2845defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si, 2846 sdmem, sse_load_f64, "cvtsd2si">, 2847 XD, EVEX_CD8<64, CD8VT1>; 2848defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64, 2849 sdmem, sse_load_f64, "cvtsd2si">, 2850 XD, VEX_W, EVEX_CD8<64, CD8VT1>; 2851defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi, 2852 sdmem, sse_load_f64, "cvtsd2usi">, 2853 XD, EVEX_CD8<64, CD8VT1>; 2854defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64, 2855 int_x86_avx512_cvtsd2usi64, sdmem, 2856 sse_load_f64, "cvtsd2usi">, XD, VEX_W, 2857 EVEX_CD8<64, CD8VT1>; 2858 2859let isCodeGenOnly = 1 in { 2860 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X, 2861 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}", 2862 SSE_CVT_Scalar, 0>, XS, EVEX_4V; 2863 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X, 2864 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}", 2865 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W; 2866 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X, 2867 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}", 2868 SSE_CVT_Scalar, 0>, XD, EVEX_4V; 2869 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X, 2870 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}", 2871 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W; 2872 2873 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X, 2874 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}", 2875 SSE_CVT_Scalar, 0>, XS, EVEX_4V; 2876 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X, 2877 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}", 2878 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W; 2879 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X, 2880 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}", 2881 SSE_CVT_Scalar, 0>, XD, EVEX_4V; 2882 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X, 2883 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}", 2884 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W; 2885} // isCodeGenOnly = 1 2886 2887// Convert float/double to signed/unsigned int 32/64 with truncation 2888let isCodeGenOnly = 1 in { 2889 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si, 2890 ssmem, sse_load_f32, "cvttss2si">, 2891 XS, EVEX_CD8<32, CD8VT1>; 2892 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64, 2893 int_x86_sse_cvttss2si64, ssmem, sse_load_f32, 2894 "cvttss2si">, XS, VEX_W, 2895 EVEX_CD8<32, CD8VT1>; 2896 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si, 2897 sdmem, sse_load_f64, "cvttsd2si">, XD, 2898 EVEX_CD8<64, CD8VT1>; 2899 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64, 2900 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64, 2901 "cvttsd2si">, XD, VEX_W, 2902 EVEX_CD8<64, CD8VT1>; 2903 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32, 2904 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32, 2905 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>; 2906 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64, 2907 int_x86_avx512_cvttss2usi64, ssmem, 2908 sse_load_f32, "cvttss2usi">, XS, VEX_W, 2909 EVEX_CD8<32, CD8VT1>; 2910 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32, 2911 int_x86_avx512_cvttsd2usi, 2912 sdmem, sse_load_f64, "cvttsd2usi">, XD, 2913 EVEX_CD8<64, CD8VT1>; 2914 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64, 2915 int_x86_avx512_cvttsd2usi64, sdmem, 2916 sse_load_f64, "cvttsd2usi">, XD, VEX_W, 2917 EVEX_CD8<64, CD8VT1>; 2918} // isCodeGenOnly = 1 2919 2920multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC, 2921 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag, 2922 string asm> { 2923 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), 2924 !strconcat(asm," \t{$src, $dst|$dst, $src}"), 2925 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX; 2926 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), 2927 !strconcat(asm," \t{$src, $dst|$dst, $src}"), 2928 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX; 2929} 2930 2931defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem, 2932 loadf32, "cvttss2si">, XS, 2933 EVEX_CD8<32, CD8VT1>; 2934defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem, 2935 loadf32, "cvttss2usi">, XS, 2936 EVEX_CD8<32, CD8VT1>; 2937defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem, 2938 loadf32, "cvttss2si">, XS, VEX_W, 2939 EVEX_CD8<32, CD8VT1>; 2940defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem, 2941 loadf32, "cvttss2usi">, XS, VEX_W, 2942 EVEX_CD8<32, CD8VT1>; 2943defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem, 2944 loadf64, "cvttsd2si">, XD, 2945 EVEX_CD8<64, CD8VT1>; 2946defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem, 2947 loadf64, "cvttsd2usi">, XD, 2948 EVEX_CD8<64, CD8VT1>; 2949defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem, 2950 loadf64, "cvttsd2si">, XD, VEX_W, 2951 EVEX_CD8<64, CD8VT1>; 2952defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem, 2953 loadf64, "cvttsd2usi">, XD, VEX_W, 2954 EVEX_CD8<64, CD8VT1>; 2955} // HasAVX512 2956//===----------------------------------------------------------------------===// 2957// AVX-512 Convert form float to double and back 2958//===----------------------------------------------------------------------===// 2959let hasSideEffects = 0 in { 2960def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst), 2961 (ins FR32X:$src1, FR32X:$src2), 2962 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}", 2963 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>; 2964let mayLoad = 1 in 2965def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst), 2966 (ins FR32X:$src1, f32mem:$src2), 2967 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}", 2968 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>, 2969 EVEX_CD8<32, CD8VT1>; 2970 2971// Convert scalar double to scalar single 2972def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst), 2973 (ins FR64X:$src1, FR64X:$src2), 2974 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", 2975 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>; 2976let mayLoad = 1 in 2977def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst), 2978 (ins FR64X:$src1, f64mem:$src2), 2979 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", 2980 []>, EVEX_4V, VEX_LIG, VEX_W, 2981 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>; 2982} 2983 2984def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>, 2985 Requires<[HasAVX512]>; 2986def : Pat<(fextend (loadf32 addr:$src)), 2987 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>; 2988 2989def : Pat<(extloadf32 addr:$src), 2990 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, 2991 Requires<[HasAVX512, OptForSize]>; 2992 2993def : Pat<(extloadf32 addr:$src), 2994 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>, 2995 Requires<[HasAVX512, OptForSpeed]>; 2996 2997def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>, 2998 Requires<[HasAVX512]>; 2999 3000multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC, 3001 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag, 3002 X86MemOperand x86memop, ValueType OpVT, ValueType InVT, 3003 Domain d> { 3004let hasSideEffects = 0 in { 3005 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), 3006 !strconcat(asm," \t{$src, $dst|$dst, $src}"), 3007 [(set DstRC:$dst, 3008 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX; 3009 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc), 3010 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"), 3011 [], d>, EVEX, EVEX_B, EVEX_RC; 3012 let mayLoad = 1 in 3013 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), 3014 !strconcat(asm," \t{$src, $dst|$dst, $src}"), 3015 [(set DstRC:$dst, 3016 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX; 3017} // hasSideEffects = 0 3018} 3019 3020multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC, 3021 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag, 3022 X86MemOperand x86memop, ValueType OpVT, ValueType InVT, 3023 Domain d> { 3024let hasSideEffects = 0 in { 3025 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), 3026 !strconcat(asm," \t{$src, $dst|$dst, $src}"), 3027 [(set DstRC:$dst, 3028 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX; 3029 let mayLoad = 1 in 3030 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), 3031 !strconcat(asm," \t{$src, $dst|$dst, $src}"), 3032 [(set DstRC:$dst, 3033 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX; 3034} // hasSideEffects = 0 3035} 3036 3037defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround, 3038 memopv8f64, f512mem, v8f32, v8f64, 3039 SSEPackedSingle>, EVEX_V512, VEX_W, PD, 3040 EVEX_CD8<64, CD8VF>; 3041 3042defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend, 3043 memopv4f64, f256mem, v8f64, v8f32, 3044 SSEPackedDouble>, EVEX_V512, PS, 3045 EVEX_CD8<32, CD8VH>; 3046def : Pat<(v8f64 (extloadv8f32 addr:$src)), 3047 (VCVTPS2PDZrm addr:$src)>; 3048 3049def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src), 3050 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))), 3051 (VCVTPD2PSZrr VR512:$src)>; 3052 3053def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src), 3054 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)), 3055 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>; 3056 3057//===----------------------------------------------------------------------===// 3058// AVX-512 Vector convert from sign integer to float/double 3059//===----------------------------------------------------------------------===// 3060 3061defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp, 3062 memopv8i64, i512mem, v16f32, v16i32, 3063 SSEPackedSingle>, EVEX_V512, PS, 3064 EVEX_CD8<32, CD8VF>; 3065 3066defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp, 3067 memopv4i64, i256mem, v8f64, v8i32, 3068 SSEPackedDouble>, EVEX_V512, XS, 3069 EVEX_CD8<32, CD8VH>; 3070 3071defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint, 3072 memopv16f32, f512mem, v16i32, v16f32, 3073 SSEPackedSingle>, EVEX_V512, XS, 3074 EVEX_CD8<32, CD8VF>; 3075 3076defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint, 3077 memopv8f64, f512mem, v8i32, v8f64, 3078 SSEPackedDouble>, EVEX_V512, PD, VEX_W, 3079 EVEX_CD8<64, CD8VF>; 3080 3081defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint, 3082 memopv16f32, f512mem, v16i32, v16f32, 3083 SSEPackedSingle>, EVEX_V512, PS, 3084 EVEX_CD8<32, CD8VF>; 3085 3086// cvttps2udq (src, 0, mask-all-ones, sae-current) 3087def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src), 3088 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)), 3089 (VCVTTPS2UDQZrr VR512:$src)>; 3090 3091defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint, 3092 memopv8f64, f512mem, v8i32, v8f64, 3093 SSEPackedDouble>, EVEX_V512, PS, VEX_W, 3094 EVEX_CD8<64, CD8VF>; 3095 3096// cvttpd2udq (src, 0, mask-all-ones, sae-current) 3097def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src), 3098 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)), 3099 (VCVTTPD2UDQZrr VR512:$src)>; 3100 3101defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp, 3102 memopv4i64, f256mem, v8f64, v8i32, 3103 SSEPackedDouble>, EVEX_V512, XS, 3104 EVEX_CD8<32, CD8VH>; 3105 3106defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp, 3107 memopv16i32, f512mem, v16f32, v16i32, 3108 SSEPackedSingle>, EVEX_V512, XD, 3109 EVEX_CD8<32, CD8VF>; 3110 3111def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))), 3112 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr 3113 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>; 3114 3115 3116def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src), 3117 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)), 3118 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>; 3119def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src), 3120 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))), 3121 (VCVTDQ2PDZrr VR256X:$src)>; 3122def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src), 3123 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)), 3124 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>; 3125def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src), 3126 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))), 3127 (VCVTUDQ2PDZrr VR256X:$src)>; 3128 3129multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC, 3130 RegisterClass DstRC, PatFrag mem_frag, 3131 X86MemOperand x86memop, Domain d> { 3132let hasSideEffects = 0 in { 3133 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), 3134 !strconcat(asm," \t{$src, $dst|$dst, $src}"), 3135 [], d>, EVEX; 3136 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc), 3137 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"), 3138 [], d>, EVEX, EVEX_B, EVEX_RC; 3139 let mayLoad = 1 in 3140 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), 3141 !strconcat(asm," \t{$src, $dst|$dst, $src}"), 3142 [], d>, EVEX; 3143} // hasSideEffects = 0 3144} 3145 3146defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512, 3147 memopv16f32, f512mem, SSEPackedSingle>, PD, 3148 EVEX_V512, EVEX_CD8<32, CD8VF>; 3149defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X, 3150 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W, 3151 EVEX_V512, EVEX_CD8<64, CD8VF>; 3152 3153def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src), 3154 (v16i32 immAllZerosV), (i16 -1), imm:$rc)), 3155 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>; 3156 3157def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src), 3158 (v8i32 immAllZerosV), (i8 -1), imm:$rc)), 3159 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>; 3160 3161defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512, 3162 memopv16f32, f512mem, SSEPackedSingle>, 3163 PS, EVEX_V512, EVEX_CD8<32, CD8VF>; 3164defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X, 3165 memopv8f64, f512mem, SSEPackedDouble>, VEX_W, 3166 PS, EVEX_V512, EVEX_CD8<64, CD8VF>; 3167 3168def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src), 3169 (v16i32 immAllZerosV), (i16 -1), imm:$rc)), 3170 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>; 3171 3172def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src), 3173 (v8i32 immAllZerosV), (i8 -1), imm:$rc)), 3174 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>; 3175 3176let Predicates = [HasAVX512] in { 3177 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))), 3178 (VCVTPD2PSZrm addr:$src)>; 3179 def : Pat<(v8f64 (extloadv8f32 addr:$src)), 3180 (VCVTPS2PDZrm addr:$src)>; 3181} 3182 3183//===----------------------------------------------------------------------===// 3184// Half precision conversion instructions 3185//===----------------------------------------------------------------------===// 3186multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC, 3187 X86MemOperand x86memop> { 3188 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src), 3189 "vcvtph2ps\t{$src, $dst|$dst, $src}", 3190 []>, EVEX; 3191 let hasSideEffects = 0, mayLoad = 1 in 3192 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src), 3193 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX; 3194} 3195 3196multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC, 3197 X86MemOperand x86memop> { 3198 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst), 3199 (ins srcRC:$src1, i32i8imm:$src2), 3200 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", 3201 []>, EVEX; 3202 let hasSideEffects = 0, mayStore = 1 in 3203 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs), 3204 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2), 3205 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX; 3206} 3207 3208defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512, 3209 EVEX_CD8<32, CD8VH>; 3210defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512, 3211 EVEX_CD8<32, CD8VH>; 3212 3213def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src), 3214 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))), 3215 (VCVTPS2PHZrr VR512:$src, imm:$rc)>; 3216 3217def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src), 3218 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))), 3219 (VCVTPH2PSZrr VR256X:$src)>; 3220 3221let Defs = [EFLAGS], Predicates = [HasAVX512] in { 3222 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32, 3223 "ucomiss">, PS, EVEX, VEX_LIG, 3224 EVEX_CD8<32, CD8VT1>; 3225 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64, 3226 "ucomisd">, PD, EVEX, 3227 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>; 3228 let Pattern = []<dag> in { 3229 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load, 3230 "comiss">, PS, EVEX, VEX_LIG, 3231 EVEX_CD8<32, CD8VT1>; 3232 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load, 3233 "comisd">, PD, EVEX, 3234 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>; 3235 } 3236 let isCodeGenOnly = 1 in { 3237 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem, 3238 load, "ucomiss">, PS, EVEX, VEX_LIG, 3239 EVEX_CD8<32, CD8VT1>; 3240 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem, 3241 load, "ucomisd">, PD, EVEX, 3242 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>; 3243 3244 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem, 3245 load, "comiss">, PS, EVEX, VEX_LIG, 3246 EVEX_CD8<32, CD8VT1>; 3247 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem, 3248 load, "comisd">, PD, EVEX, 3249 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>; 3250 } 3251} 3252 3253/// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd 3254multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC, 3255 X86MemOperand x86memop> { 3256 let hasSideEffects = 0 in { 3257 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), 3258 (ins RC:$src1, RC:$src2), 3259 !strconcat(OpcodeStr, 3260 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V; 3261 let mayLoad = 1 in { 3262 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), 3263 (ins RC:$src1, x86memop:$src2), 3264 !strconcat(OpcodeStr, 3265 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V; 3266 } 3267} 3268} 3269 3270defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>, 3271 EVEX_CD8<32, CD8VT1>; 3272defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>, 3273 VEX_W, EVEX_CD8<64, CD8VT1>; 3274defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>, 3275 EVEX_CD8<32, CD8VT1>; 3276defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>, 3277 VEX_W, EVEX_CD8<64, CD8VT1>; 3278 3279def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1), 3280 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))), 3281 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X), 3282 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>; 3283 3284def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1), 3285 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))), 3286 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X), 3287 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>; 3288 3289def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1), 3290 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))), 3291 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X), 3292 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>; 3293 3294def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1), 3295 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))), 3296 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X), 3297 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>; 3298 3299/// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd 3300multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode, 3301 RegisterClass RC, X86MemOperand x86memop, 3302 PatFrag mem_frag, ValueType OpVt> { 3303 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src), 3304 !strconcat(OpcodeStr, 3305 " \t{$src, $dst|$dst, $src}"), 3306 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>, 3307 EVEX; 3308 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src), 3309 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), 3310 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>, 3311 EVEX; 3312} 3313defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem, 3314 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>; 3315defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem, 3316 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>; 3317defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem, 3318 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>; 3319defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem, 3320 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>; 3321 3322def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src), 3323 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))), 3324 (VRSQRT14PSZr VR512:$src)>; 3325def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src), 3326 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))), 3327 (VRSQRT14PDZr VR512:$src)>; 3328 3329def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src), 3330 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))), 3331 (VRCP14PSZr VR512:$src)>; 3332def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src), 3333 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))), 3334 (VRCP14PDZr VR512:$src)>; 3335 3336/// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd 3337multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC, 3338 X86MemOperand x86memop> { 3339 let hasSideEffects = 0, Predicates = [HasERI] in { 3340 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), 3341 (ins RC:$src1, RC:$src2), 3342 !strconcat(OpcodeStr, 3343 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V; 3344 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), 3345 (ins RC:$src1, RC:$src2), 3346 !strconcat(OpcodeStr, 3347 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"), 3348 []>, EVEX_4V, EVEX_B; 3349 let mayLoad = 1 in { 3350 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), 3351 (ins RC:$src1, x86memop:$src2), 3352 !strconcat(OpcodeStr, 3353 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V; 3354 } 3355} 3356} 3357 3358defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>, 3359 EVEX_CD8<32, CD8VT1>; 3360defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>, 3361 VEX_W, EVEX_CD8<64, CD8VT1>; 3362defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>, 3363 EVEX_CD8<32, CD8VT1>; 3364defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>, 3365 VEX_W, EVEX_CD8<64, CD8VT1>; 3366 3367def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1), 3368 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1), 3369 FROUND_NO_EXC)), 3370 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X), 3371 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>; 3372 3373def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1), 3374 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1), 3375 FROUND_NO_EXC)), 3376 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X), 3377 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>; 3378 3379def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1), 3380 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1), 3381 FROUND_NO_EXC)), 3382 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X), 3383 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>; 3384 3385def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1), 3386 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1), 3387 FROUND_NO_EXC)), 3388 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X), 3389 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>; 3390 3391/// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd 3392multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, 3393 RegisterClass RC, X86MemOperand x86memop> { 3394 let hasSideEffects = 0, Predicates = [HasERI] in { 3395 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src), 3396 !strconcat(OpcodeStr, 3397 " \t{$src, $dst|$dst, $src}"), 3398 []>, EVEX; 3399 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src), 3400 !strconcat(OpcodeStr, 3401 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"), 3402 []>, EVEX, EVEX_B; 3403 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src), 3404 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), 3405 []>, EVEX; 3406 } 3407} 3408defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>, 3409 EVEX_V512, EVEX_CD8<32, CD8VF>; 3410defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>, 3411 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>; 3412defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>, 3413 EVEX_V512, EVEX_CD8<32, CD8VF>; 3414defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>, 3415 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>; 3416 3417def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src), 3418 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)), 3419 (VRSQRT28PSZrb VR512:$src)>; 3420def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src), 3421 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)), 3422 (VRSQRT28PDZrb VR512:$src)>; 3423 3424def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src), 3425 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)), 3426 (VRCP28PSZrb VR512:$src)>; 3427def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src), 3428 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)), 3429 (VRCP28PDZrb VR512:$src)>; 3430 3431multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode, 3432 Intrinsic V16F32Int, Intrinsic V8F64Int, 3433 OpndItins itins_s, OpndItins itins_d> { 3434 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src), 3435 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"), 3436 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>, 3437 EVEX, EVEX_V512; 3438 3439 let mayLoad = 1 in 3440 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src), 3441 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"), 3442 [(set VR512:$dst, 3443 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))], 3444 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>; 3445 3446 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src), 3447 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"), 3448 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>, 3449 EVEX, EVEX_V512; 3450 3451 let mayLoad = 1 in 3452 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src), 3453 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"), 3454 [(set VR512:$dst, (OpNode 3455 (v8f64 (bitconvert (memopv16f32 addr:$src)))))], 3456 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>; 3457 3458let isCodeGenOnly = 1 in { 3459 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src), 3460 !strconcat(OpcodeStr, 3461 "ps\t{$src, $dst|$dst, $src}"), 3462 [(set VR512:$dst, (V16F32Int VR512:$src))]>, 3463 EVEX, EVEX_V512; 3464 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src), 3465 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"), 3466 [(set VR512:$dst, 3467 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX, 3468 EVEX_V512, EVEX_CD8<32, CD8VF>; 3469 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src), 3470 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"), 3471 [(set VR512:$dst, (V8F64Int VR512:$src))]>, 3472 EVEX, EVEX_V512, VEX_W; 3473 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src), 3474 !strconcat(OpcodeStr, 3475 "pd\t{$src, $dst|$dst, $src}"), 3476 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>, 3477 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; 3478} // isCodeGenOnly = 1 3479} 3480 3481multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr, 3482 Intrinsic F32Int, Intrinsic F64Int, 3483 OpndItins itins_s, OpndItins itins_d> { 3484 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst), 3485 (ins FR32X:$src1, FR32X:$src2), 3486 !strconcat(OpcodeStr, 3487 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 3488 [], itins_s.rr>, XS, EVEX_4V; 3489 let isCodeGenOnly = 1 in 3490 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst), 3491 (ins VR128X:$src1, VR128X:$src2), 3492 !strconcat(OpcodeStr, 3493 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 3494 [(set VR128X:$dst, 3495 (F32Int VR128X:$src1, VR128X:$src2))], 3496 itins_s.rr>, XS, EVEX_4V; 3497 let mayLoad = 1 in { 3498 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst), 3499 (ins FR32X:$src1, f32mem:$src2), 3500 !strconcat(OpcodeStr, 3501 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 3502 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>; 3503 let isCodeGenOnly = 1 in 3504 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst), 3505 (ins VR128X:$src1, ssmem:$src2), 3506 !strconcat(OpcodeStr, 3507 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 3508 [(set VR128X:$dst, 3509 (F32Int VR128X:$src1, sse_load_f32:$src2))], 3510 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>; 3511 } 3512 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst), 3513 (ins FR64X:$src1, FR64X:$src2), 3514 !strconcat(OpcodeStr, 3515 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, 3516 XD, EVEX_4V, VEX_W; 3517 let isCodeGenOnly = 1 in 3518 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst), 3519 (ins VR128X:$src1, VR128X:$src2), 3520 !strconcat(OpcodeStr, 3521 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 3522 [(set VR128X:$dst, 3523 (F64Int VR128X:$src1, VR128X:$src2))], 3524 itins_s.rr>, XD, EVEX_4V, VEX_W; 3525 let mayLoad = 1 in { 3526 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst), 3527 (ins FR64X:$src1, f64mem:$src2), 3528 !strconcat(OpcodeStr, 3529 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, 3530 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>; 3531 let isCodeGenOnly = 1 in 3532 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst), 3533 (ins VR128X:$src1, sdmem:$src2), 3534 !strconcat(OpcodeStr, 3535 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 3536 [(set VR128X:$dst, 3537 (F64Int VR128X:$src1, sse_load_f64:$src2))]>, 3538 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>; 3539 } 3540} 3541 3542 3543defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt", 3544 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd, 3545 SSE_SQRTSS, SSE_SQRTSD>, 3546 avx512_sqrt_packed<0x51, "vsqrt", fsqrt, 3547 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512, 3548 SSE_SQRTPS, SSE_SQRTPD>; 3549 3550let Predicates = [HasAVX512] in { 3551 def : Pat<(f32 (fsqrt FR32X:$src)), 3552 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>; 3553 def : Pat<(f32 (fsqrt (load addr:$src))), 3554 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>, 3555 Requires<[OptForSize]>; 3556 def : Pat<(f64 (fsqrt FR64X:$src)), 3557 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>; 3558 def : Pat<(f64 (fsqrt (load addr:$src))), 3559 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>, 3560 Requires<[OptForSize]>; 3561 3562 def : Pat<(f32 (X86frsqrt FR32X:$src)), 3563 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>; 3564 def : Pat<(f32 (X86frsqrt (load addr:$src))), 3565 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>, 3566 Requires<[OptForSize]>; 3567 3568 def : Pat<(f32 (X86frcp FR32X:$src)), 3569 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>; 3570 def : Pat<(f32 (X86frcp (load addr:$src))), 3571 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>, 3572 Requires<[OptForSize]>; 3573 3574 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src), 3575 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)), 3576 (COPY_TO_REGCLASS VR128X:$src, FR32)), 3577 VR128X)>; 3578 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src), 3579 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>; 3580 3581 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src), 3582 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)), 3583 (COPY_TO_REGCLASS VR128X:$src, FR64)), 3584 VR128X)>; 3585 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src), 3586 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>; 3587} 3588 3589 3590multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr, 3591 X86MemOperand x86memop, RegisterClass RC, 3592 PatFrag mem_frag32, PatFrag mem_frag64, 3593 Intrinsic V4F32Int, Intrinsic V2F64Int, 3594 CD8VForm VForm> { 3595let ExeDomain = SSEPackedSingle in { 3596 // Intrinsic operation, reg. 3597 // Vector intrinsic operation, reg 3598 def PSr : AVX512AIi8<opcps, MRMSrcReg, 3599 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2), 3600 !strconcat(OpcodeStr, 3601 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 3602 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>; 3603 3604 // Vector intrinsic operation, mem 3605 def PSm : AVX512AIi8<opcps, MRMSrcMem, 3606 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2), 3607 !strconcat(OpcodeStr, 3608 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 3609 [(set RC:$dst, 3610 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>, 3611 EVEX_CD8<32, VForm>; 3612} // ExeDomain = SSEPackedSingle 3613 3614let ExeDomain = SSEPackedDouble in { 3615 // Vector intrinsic operation, reg 3616 def PDr : AVX512AIi8<opcpd, MRMSrcReg, 3617 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2), 3618 !strconcat(OpcodeStr, 3619 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 3620 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>; 3621 3622 // Vector intrinsic operation, mem 3623 def PDm : AVX512AIi8<opcpd, MRMSrcMem, 3624 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2), 3625 !strconcat(OpcodeStr, 3626 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 3627 [(set RC:$dst, 3628 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>, 3629 EVEX_CD8<64, VForm>; 3630} // ExeDomain = SSEPackedDouble 3631} 3632 3633multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd, 3634 string OpcodeStr, 3635 Intrinsic F32Int, 3636 Intrinsic F64Int> { 3637let ExeDomain = GenericDomain in { 3638 // Operation, reg. 3639 let hasSideEffects = 0 in 3640 def SSr : AVX512AIi8<opcss, MRMSrcReg, 3641 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3), 3642 !strconcat(OpcodeStr, 3643 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 3644 []>; 3645 3646 // Intrinsic operation, reg. 3647 let isCodeGenOnly = 1 in 3648 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg, 3649 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3), 3650 !strconcat(OpcodeStr, 3651 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 3652 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>; 3653 3654 // Intrinsic operation, mem. 3655 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst), 3656 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3), 3657 !strconcat(OpcodeStr, 3658 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 3659 [(set VR128X:$dst, (F32Int VR128X:$src1, 3660 sse_load_f32:$src2, imm:$src3))]>, 3661 EVEX_CD8<32, CD8VT1>; 3662 3663 // Operation, reg. 3664 let hasSideEffects = 0 in 3665 def SDr : AVX512AIi8<opcsd, MRMSrcReg, 3666 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3), 3667 !strconcat(OpcodeStr, 3668 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 3669 []>, VEX_W; 3670 3671 // Intrinsic operation, reg. 3672 let isCodeGenOnly = 1 in 3673 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg, 3674 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3), 3675 !strconcat(OpcodeStr, 3676 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 3677 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>, 3678 VEX_W; 3679 3680 // Intrinsic operation, mem. 3681 def SDm : AVX512AIi8<opcsd, MRMSrcMem, 3682 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3), 3683 !strconcat(OpcodeStr, 3684 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 3685 [(set VR128X:$dst, 3686 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>, 3687 VEX_W, EVEX_CD8<64, CD8VT1>; 3688} // ExeDomain = GenericDomain 3689} 3690 3691multiclass avx512_rndscale<bits<8> opc, string OpcodeStr, 3692 X86MemOperand x86memop, RegisterClass RC, 3693 PatFrag mem_frag, Domain d> { 3694let ExeDomain = d in { 3695 // Intrinsic operation, reg. 3696 // Vector intrinsic operation, reg 3697 def r : AVX512AIi8<opc, MRMSrcReg, 3698 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2), 3699 !strconcat(OpcodeStr, 3700 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), 3701 []>, EVEX; 3702 3703 // Vector intrinsic operation, mem 3704 def m : AVX512AIi8<opc, MRMSrcMem, 3705 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2), 3706 !strconcat(OpcodeStr, 3707 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), 3708 []>, EVEX; 3709} // ExeDomain 3710} 3711 3712 3713defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512, 3714 memopv16f32, SSEPackedSingle>, EVEX_V512, 3715 EVEX_CD8<32, CD8VF>; 3716 3717def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1), 3718 imm:$src2, (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), 3719 FROUND_CURRENT)), 3720 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>; 3721 3722 3723defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512, 3724 memopv8f64, SSEPackedDouble>, EVEX_V512, 3725 VEX_W, EVEX_CD8<64, CD8VF>; 3726 3727def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1), 3728 imm:$src2, (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), 3729 FROUND_CURRENT)), 3730 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>; 3731 3732multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, 3733 Operand x86memop, RegisterClass RC, Domain d> { 3734let ExeDomain = d in { 3735 def r : AVX512AIi8<opc, MRMSrcReg, 3736 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3), 3737 !strconcat(OpcodeStr, 3738 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), 3739 []>, EVEX_4V; 3740 3741 def m : AVX512AIi8<opc, MRMSrcMem, 3742 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3), 3743 !strconcat(OpcodeStr, 3744 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), 3745 []>, EVEX_4V; 3746} // ExeDomain 3747} 3748 3749defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X, 3750 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>; 3751 3752defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X, 3753 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>; 3754 3755def : Pat<(ffloor FR32X:$src), 3756 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>; 3757def : Pat<(f64 (ffloor FR64X:$src)), 3758 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>; 3759def : Pat<(f32 (fnearbyint FR32X:$src)), 3760 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>; 3761def : Pat<(f64 (fnearbyint FR64X:$src)), 3762 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>; 3763def : Pat<(f32 (fceil FR32X:$src)), 3764 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>; 3765def : Pat<(f64 (fceil FR64X:$src)), 3766 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>; 3767def : Pat<(f32 (frint FR32X:$src)), 3768 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>; 3769def : Pat<(f64 (frint FR64X:$src)), 3770 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>; 3771def : Pat<(f32 (ftrunc FR32X:$src)), 3772 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>; 3773def : Pat<(f64 (ftrunc FR64X:$src)), 3774 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>; 3775 3776def : Pat<(v16f32 (ffloor VR512:$src)), 3777 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>; 3778def : Pat<(v16f32 (fnearbyint VR512:$src)), 3779 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>; 3780def : Pat<(v16f32 (fceil VR512:$src)), 3781 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>; 3782def : Pat<(v16f32 (frint VR512:$src)), 3783 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>; 3784def : Pat<(v16f32 (ftrunc VR512:$src)), 3785 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>; 3786 3787def : Pat<(v8f64 (ffloor VR512:$src)), 3788 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>; 3789def : Pat<(v8f64 (fnearbyint VR512:$src)), 3790 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>; 3791def : Pat<(v8f64 (fceil VR512:$src)), 3792 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>; 3793def : Pat<(v8f64 (frint VR512:$src)), 3794 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>; 3795def : Pat<(v8f64 (ftrunc VR512:$src)), 3796 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>; 3797 3798//------------------------------------------------- 3799// Integer truncate and extend operations 3800//------------------------------------------------- 3801 3802multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr, 3803 RegisterClass dstRC, RegisterClass srcRC, 3804 RegisterClass KRC, X86MemOperand x86memop> { 3805 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst), 3806 (ins srcRC:$src), 3807 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"), 3808 []>, EVEX; 3809 3810 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst), 3811 (ins KRC:$mask, srcRC:$src), 3812 !strconcat(OpcodeStr, 3813 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"), 3814 []>, EVEX, EVEX_KZ; 3815 3816 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src), 3817 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), 3818 []>, EVEX; 3819} 3820defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM, 3821 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>; 3822defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM, 3823 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>; 3824defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM, 3825 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>; 3826defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM, 3827 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>; 3828defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM, 3829 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>; 3830defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM, 3831 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>; 3832defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM, 3833 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>; 3834defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM, 3835 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>; 3836defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM, 3837 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>; 3838defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM, 3839 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>; 3840defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM, 3841 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>; 3842defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM, 3843 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>; 3844defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM, 3845 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>; 3846defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM, 3847 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>; 3848defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM, 3849 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>; 3850 3851def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>; 3852def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>; 3853def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>; 3854def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>; 3855def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>; 3856 3857def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))), 3858 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>; 3859def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))), 3860 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>; 3861def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))), 3862 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>; 3863def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))), 3864 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>; 3865 3866 3867multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC, 3868 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag, 3869 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> { 3870 3871 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), 3872 (ins SrcRC:$src), 3873 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), 3874 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX; 3875 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), 3876 (ins x86memop:$src), 3877 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"), 3878 [(set DstRC:$dst, 3879 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>, 3880 EVEX; 3881} 3882 3883defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext, 3884 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512, 3885 EVEX_CD8<8, CD8VQ>; 3886defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext, 3887 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512, 3888 EVEX_CD8<8, CD8VO>; 3889defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext, 3890 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512, 3891 EVEX_CD8<16, CD8VH>; 3892defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext, 3893 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512, 3894 EVEX_CD8<16, CD8VQ>; 3895defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext, 3896 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512, 3897 EVEX_CD8<32, CD8VH>; 3898 3899defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext, 3900 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512, 3901 EVEX_CD8<8, CD8VQ>; 3902defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext, 3903 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512, 3904 EVEX_CD8<8, CD8VO>; 3905defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext, 3906 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512, 3907 EVEX_CD8<16, CD8VH>; 3908defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext, 3909 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512, 3910 EVEX_CD8<16, CD8VQ>; 3911defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext, 3912 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512, 3913 EVEX_CD8<32, CD8VH>; 3914 3915//===----------------------------------------------------------------------===// 3916// GATHER - SCATTER Operations 3917 3918multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC, 3919 RegisterClass RC, X86MemOperand memop> { 3920let mayLoad = 1, 3921 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in 3922 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb), 3923 (ins RC:$src1, KRC:$mask, memop:$src2), 3924 !strconcat(OpcodeStr, 3925 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), 3926 []>, EVEX, EVEX_K; 3927} 3928 3929let ExeDomain = SSEPackedDouble in { 3930defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>, 3931 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>; 3932defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>, 3933 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>; 3934} 3935 3936let ExeDomain = SSEPackedSingle in { 3937defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>, 3938 EVEX_V512, EVEX_CD8<32, CD8VT1>; 3939defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>, 3940 EVEX_V512, EVEX_CD8<32, CD8VT1>; 3941} 3942 3943defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>, 3944 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>; 3945defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>, 3946 EVEX_V512, EVEX_CD8<32, CD8VT1>; 3947 3948defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>, 3949 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>; 3950defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>, 3951 EVEX_V512, EVEX_CD8<32, CD8VT1>; 3952 3953multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC, 3954 RegisterClass RC, X86MemOperand memop> { 3955let mayStore = 1, Constraints = "$mask = $mask_wb" in 3956 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb), 3957 (ins memop:$dst, KRC:$mask, RC:$src2), 3958 !strconcat(OpcodeStr, 3959 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), 3960 []>, EVEX, EVEX_K; 3961} 3962 3963let ExeDomain = SSEPackedDouble in { 3964defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>, 3965 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>; 3966defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>, 3967 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>; 3968} 3969 3970let ExeDomain = SSEPackedSingle in { 3971defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>, 3972 EVEX_V512, EVEX_CD8<32, CD8VT1>; 3973defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>, 3974 EVEX_V512, EVEX_CD8<32, CD8VT1>; 3975} 3976 3977defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>, 3978 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>; 3979defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>, 3980 EVEX_V512, EVEX_CD8<32, CD8VT1>; 3981 3982defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>, 3983 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>; 3984defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>, 3985 EVEX_V512, EVEX_CD8<32, CD8VT1>; 3986 3987//===----------------------------------------------------------------------===// 3988// VSHUFPS - VSHUFPD Operations 3989 3990multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop, 3991 ValueType vt, string OpcodeStr, PatFrag mem_frag, 3992 Domain d> { 3993 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst), 3994 (ins RC:$src1, x86memop:$src2, i8imm:$src3), 3995 !strconcat(OpcodeStr, 3996 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 3997 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2), 3998 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>, 3999 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>; 4000 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst), 4001 (ins RC:$src1, RC:$src2, i8imm:$src3), 4002 !strconcat(OpcodeStr, 4003 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 4004 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2, 4005 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>, 4006 EVEX_4V, Sched<[WriteShuffle]>; 4007} 4008 4009defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32, 4010 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>; 4011defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64, 4012 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>; 4013 4014def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))), 4015 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>; 4016def : Pat<(v16i32 (X86Shufp VR512:$src1, 4017 (memopv16i32 addr:$src2), (i8 imm:$imm))), 4018 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>; 4019 4020def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))), 4021 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>; 4022def : Pat<(v8i64 (X86Shufp VR512:$src1, 4023 (memopv8i64 addr:$src2), (i8 imm:$imm))), 4024 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>; 4025 4026multiclass avx512_alignr<string OpcodeStr, RegisterClass RC, 4027 X86MemOperand x86memop> { 4028 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst), 4029 (ins RC:$src1, RC:$src2, i8imm:$src3), 4030 !strconcat(OpcodeStr, 4031 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 4032 []>, EVEX_4V; 4033 let mayLoad = 1 in 4034 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst), 4035 (ins RC:$src1, x86memop:$src2, i8imm:$src3), 4036 !strconcat(OpcodeStr, 4037 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 4038 []>, EVEX_4V; 4039} 4040defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>, 4041 EVEX_V512, EVEX_CD8<32, CD8VF>; 4042defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>, 4043 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>; 4044 4045def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))), 4046 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>; 4047def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))), 4048 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>; 4049def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))), 4050 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>; 4051def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))), 4052 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>; 4053 4054// Helper fragments to match sext vXi1 to vXiY. 4055def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>; 4056def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>; 4057 4058multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT, 4059 RegisterClass KRC, RegisterClass RC, 4060 X86MemOperand x86memop, X86MemOperand x86scalar_mop, 4061 string BrdcstStr> { 4062 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src), 4063 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), 4064 []>, EVEX; 4065 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src), 4066 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"), 4067 []>, EVEX, EVEX_K; 4068 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src), 4069 !strconcat(OpcodeStr, 4070 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"), 4071 []>, EVEX, EVEX_KZ; 4072 let mayLoad = 1 in { 4073 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), 4074 (ins x86memop:$src), 4075 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), 4076 []>, EVEX; 4077 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), 4078 (ins KRC:$mask, x86memop:$src), 4079 !strconcat(OpcodeStr, 4080 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"), 4081 []>, EVEX, EVEX_K; 4082 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), 4083 (ins KRC:$mask, x86memop:$src), 4084 !strconcat(OpcodeStr, 4085 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"), 4086 []>, EVEX, EVEX_KZ; 4087 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), 4088 (ins x86scalar_mop:$src), 4089 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr, 4090 ", $dst|$dst, ${src}", BrdcstStr, "}"), 4091 []>, EVEX, EVEX_B; 4092 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), 4093 (ins KRC:$mask, x86scalar_mop:$src), 4094 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr, 4095 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"), 4096 []>, EVEX, EVEX_B, EVEX_K; 4097 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), 4098 (ins KRC:$mask, x86scalar_mop:$src), 4099 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr, 4100 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}", 4101 BrdcstStr, "}"), 4102 []>, EVEX, EVEX_B, EVEX_KZ; 4103 } 4104} 4105 4106defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512, 4107 i512mem, i32mem, "{1to16}">, EVEX_V512, 4108 EVEX_CD8<32, CD8VF>; 4109defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512, 4110 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W, 4111 EVEX_CD8<64, CD8VF>; 4112 4113def : Pat<(xor 4114 (bc_v16i32 (v16i1sextv16i32)), 4115 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))), 4116 (VPABSDZrr VR512:$src)>; 4117def : Pat<(xor 4118 (bc_v8i64 (v8i1sextv8i64)), 4119 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))), 4120 (VPABSQZrr VR512:$src)>; 4121 4122def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src), 4123 (v16i32 immAllZerosV), (i16 -1))), 4124 (VPABSDZrr VR512:$src)>; 4125def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src), 4126 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))), 4127 (VPABSQZrr VR512:$src)>; 4128 4129multiclass avx512_conflict<bits<8> opc, string OpcodeStr, 4130 RegisterClass RC, RegisterClass KRC, 4131 X86MemOperand x86memop, 4132 X86MemOperand x86scalar_mop, string BrdcstStr> { 4133 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), 4134 (ins RC:$src), 4135 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"), 4136 []>, EVEX; 4137 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), 4138 (ins x86memop:$src), 4139 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"), 4140 []>, EVEX; 4141 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), 4142 (ins x86scalar_mop:$src), 4143 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr, 4144 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"), 4145 []>, EVEX, EVEX_B; 4146 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), 4147 (ins KRC:$mask, RC:$src), 4148 !strconcat(OpcodeStr, 4149 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"), 4150 []>, EVEX, EVEX_KZ; 4151 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), 4152 (ins KRC:$mask, x86memop:$src), 4153 !strconcat(OpcodeStr, 4154 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"), 4155 []>, EVEX, EVEX_KZ; 4156 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), 4157 (ins KRC:$mask, x86scalar_mop:$src), 4158 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr, 4159 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}", 4160 BrdcstStr, "}"), 4161 []>, EVEX, EVEX_KZ, EVEX_B; 4162 4163 let Constraints = "$src1 = $dst" in { 4164 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), 4165 (ins RC:$src1, KRC:$mask, RC:$src2), 4166 !strconcat(OpcodeStr, 4167 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), 4168 []>, EVEX, EVEX_K; 4169 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), 4170 (ins RC:$src1, KRC:$mask, x86memop:$src2), 4171 !strconcat(OpcodeStr, 4172 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), 4173 []>, EVEX, EVEX_K; 4174 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), 4175 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2), 4176 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr, 4177 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"), 4178 []>, EVEX, EVEX_K, EVEX_B; 4179 } 4180} 4181 4182let Predicates = [HasCDI] in { 4183defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM, 4184 i512mem, i32mem, "{1to16}">, 4185 EVEX_V512, EVEX_CD8<32, CD8VF>; 4186 4187 4188defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM, 4189 i512mem, i64mem, "{1to8}">, 4190 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; 4191 4192} 4193 4194def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1, 4195 GR16:$mask), 4196 (VPCONFLICTDrrk VR512:$src1, 4197 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>; 4198 4199def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1, 4200 GR8:$mask), 4201 (VPCONFLICTQrrk VR512:$src1, 4202 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>; 4203