X86InstrFPStack.td revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338
1//===- X86InstrFPStack.td - FPU Instruction Set ------------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the X86 x87 FPU instruction set, defining the 11// instructions, and properties of the instructions which are needed for code 12// generation, machine code emission, and analysis. 13// 14//===----------------------------------------------------------------------===// 15 16//===----------------------------------------------------------------------===// 17// FPStack specific DAG Nodes. 18//===----------------------------------------------------------------------===// 19 20def SDTX86FpGet2 : SDTypeProfile<2, 0, [SDTCisVT<0, f80>, 21 SDTCisVT<1, f80>]>; 22def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisFP<0>, 23 SDTCisPtrTy<1>, 24 SDTCisVT<2, OtherVT>]>; 25def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>, 26 SDTCisPtrTy<1>, 27 SDTCisVT<2, OtherVT>]>; 28def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisPtrTy<1>, 29 SDTCisVT<2, OtherVT>]>; 30def SDTX86Fnstsw : SDTypeProfile<1, 1, [SDTCisVT<0, i16>, SDTCisVT<1, i16>]>; 31def SDTX86FpToIMem : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>; 32 33def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 34 35def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, 36 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 37def X86fst : SDNode<"X86ISD::FST", SDTX86Fst, 38 [SDNPHasChain, SDNPInGlue, SDNPMayStore, 39 SDNPMemOperand]>; 40def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild, 41 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 42def X86fildflag : SDNode<"X86ISD::FILD_FLAG", SDTX86Fild, 43 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad, 44 SDNPMemOperand]>; 45def X86fp_stsw : SDNode<"X86ISD::FNSTSW16r", SDTX86Fnstsw>; 46def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem, 47 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 48def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem, 49 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 50def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem, 51 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 52def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore, 53 [SDNPHasChain, SDNPMayStore, SDNPSideEffect, 54 SDNPMemOperand]>; 55 56//===----------------------------------------------------------------------===// 57// FPStack pattern fragments 58//===----------------------------------------------------------------------===// 59 60def fpimm0 : PatLeaf<(fpimm), [{ 61 return N->isExactlyValue(+0.0); 62}]>; 63 64def fpimmneg0 : PatLeaf<(fpimm), [{ 65 return N->isExactlyValue(-0.0); 66}]>; 67 68def fpimm1 : PatLeaf<(fpimm), [{ 69 return N->isExactlyValue(+1.0); 70}]>; 71 72def fpimmneg1 : PatLeaf<(fpimm), [{ 73 return N->isExactlyValue(-1.0); 74}]>; 75 76// Some 'special' instructions 77let usesCustomInserter = 1 in { // Expanded after instruction selection. 78 def FP32_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP32:$src), 79 [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>; 80 def FP32_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP32:$src), 81 [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>; 82 def FP32_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP32:$src), 83 [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>; 84 def FP64_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP64:$src), 85 [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>; 86 def FP64_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP64:$src), 87 [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>; 88 def FP64_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP64:$src), 89 [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>; 90 def FP80_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP80:$src), 91 [(X86fp_to_i16mem RFP80:$src, addr:$dst)]>; 92 def FP80_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP80:$src), 93 [(X86fp_to_i32mem RFP80:$src, addr:$dst)]>; 94 def FP80_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP80:$src), 95 [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>; 96} 97 98// All FP Stack operations are represented with four instructions here. The 99// first three instructions, generated by the instruction selector, use "RFP32" 100// "RFP64" or "RFP80" registers: traditional register files to reference 32-bit, 101// 64-bit or 80-bit floating point values. These sizes apply to the values, 102// not the registers, which are always 80 bits; RFP32, RFP64 and RFP80 can be 103// copied to each other without losing information. These instructions are all 104// pseudo instructions and use the "_Fp" suffix. 105// In some cases there are additional variants with a mixture of different 106// register sizes. 107// The second instruction is defined with FPI, which is the actual instruction 108// emitted by the assembler. These use "RST" registers, although frequently 109// the actual register(s) used are implicit. These are always 80 bits. 110// The FP stackifier pass converts one to the other after register allocation 111// occurs. 112// 113// Note that the FpI instruction should have instruction selection info (e.g. 114// a pattern) and the FPI instruction should have emission info (e.g. opcode 115// encoding and asm printing info). 116 117// Pseudo Instruction for FP stack return values. 118def FpPOP_RETVAL : FpI_<(outs RFP80:$dst), (ins), SpecialFP, []>; 119 120// FpIf32, FpIf64 - Floating Point Pseudo Instruction template. 121// f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1. 122// f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2. 123// f80 instructions cannot use SSE and use neither of these. 124class FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 125 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32]>; 126class FpIf64<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 127 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64]>; 128 129// Factoring for arithmetic. 130multiclass FPBinary_rr<SDNode OpNode> { 131// Register op register -> register 132// These are separated out because they have no reversed form. 133def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP, 134 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>; 135def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP, 136 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>; 137def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP, 138 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>; 139} 140// The FopST0 series are not included here because of the irregularities 141// in where the 'r' goes in assembly output. 142// These instructions cannot address 80-bit memory. 143multiclass FPBinary<SDNode OpNode, Format fp, string asmstring> { 144// ST(0) = ST(0) + [mem] 145def _Fp32m : FpIf32<(outs RFP32:$dst), 146 (ins RFP32:$src1, f32mem:$src2), OneArgFPRW, 147 [(set RFP32:$dst, 148 (OpNode RFP32:$src1, (loadf32 addr:$src2)))]>; 149def _Fp64m : FpIf64<(outs RFP64:$dst), 150 (ins RFP64:$src1, f64mem:$src2), OneArgFPRW, 151 [(set RFP64:$dst, 152 (OpNode RFP64:$src1, (loadf64 addr:$src2)))]>; 153def _Fp64m32: FpIf64<(outs RFP64:$dst), 154 (ins RFP64:$src1, f32mem:$src2), OneArgFPRW, 155 [(set RFP64:$dst, 156 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2))))]>; 157def _Fp80m32: FpI_<(outs RFP80:$dst), 158 (ins RFP80:$src1, f32mem:$src2), OneArgFPRW, 159 [(set RFP80:$dst, 160 (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2))))]>; 161def _Fp80m64: FpI_<(outs RFP80:$dst), 162 (ins RFP80:$src1, f64mem:$src2), OneArgFPRW, 163 [(set RFP80:$dst, 164 (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2))))]>; 165def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src), 166 !strconcat("f", asmstring, "{s}\t$src")> { 167 let mayLoad = 1; 168} 169def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src), 170 !strconcat("f", asmstring, "{l}\t$src")> { 171 let mayLoad = 1; 172} 173// ST(0) = ST(0) + [memint] 174def _FpI16m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), 175 OneArgFPRW, 176 [(set RFP32:$dst, (OpNode RFP32:$src1, 177 (X86fild addr:$src2, i16)))]>; 178def _FpI32m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2), 179 OneArgFPRW, 180 [(set RFP32:$dst, (OpNode RFP32:$src1, 181 (X86fild addr:$src2, i32)))]>; 182def _FpI16m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2), 183 OneArgFPRW, 184 [(set RFP64:$dst, (OpNode RFP64:$src1, 185 (X86fild addr:$src2, i16)))]>; 186def _FpI32m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), 187 OneArgFPRW, 188 [(set RFP64:$dst, (OpNode RFP64:$src1, 189 (X86fild addr:$src2, i32)))]>; 190def _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2), 191 OneArgFPRW, 192 [(set RFP80:$dst, (OpNode RFP80:$src1, 193 (X86fild addr:$src2, i16)))]>; 194def _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2), 195 OneArgFPRW, 196 [(set RFP80:$dst, (OpNode RFP80:$src1, 197 (X86fild addr:$src2, i32)))]>; 198def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src), 199 !strconcat("fi", asmstring, "{s}\t$src")> { 200 let mayLoad = 1; 201} 202def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src), 203 !strconcat("fi", asmstring, "{l}\t$src")> { 204 let mayLoad = 1; 205} 206} 207 208let Defs = [FPSW] in { 209// FPBinary_rr just defines pseudo-instructions, no need to set a scheduling 210// resources. 211defm ADD : FPBinary_rr<fadd>; 212defm SUB : FPBinary_rr<fsub>; 213defm MUL : FPBinary_rr<fmul>; 214defm DIV : FPBinary_rr<fdiv>; 215// Sets the scheduling resources for the actual NAME#_F<size>m defintions. 216let SchedRW = [WriteFAddLd] in { 217defm ADD : FPBinary<fadd, MRM0m, "add">; 218defm SUB : FPBinary<fsub, MRM4m, "sub">; 219defm SUBR: FPBinary<fsub ,MRM5m, "subr">; 220} 221let SchedRW = [WriteFMulLd] in { 222defm MUL : FPBinary<fmul, MRM1m, "mul">; 223} 224let SchedRW = [WriteFDivLd] in { 225defm DIV : FPBinary<fdiv, MRM6m, "div">; 226defm DIVR: FPBinary<fdiv, MRM7m, "divr">; 227} 228} 229 230class FPST0rInst<Format fp, string asm> 231 : FPI<0xD8, fp, (outs), (ins RST:$op), asm>; 232class FPrST0Inst<Format fp, string asm> 233 : FPI<0xDC, fp, (outs), (ins RST:$op), asm>; 234class FPrST0PInst<Format fp, string asm> 235 : FPI<0xDE, fp, (outs), (ins RST:$op), asm>; 236 237// NOTE: GAS and apparently all other AT&T style assemblers have a broken notion 238// of some of the 'reverse' forms of the fsub and fdiv instructions. As such, 239// we have to put some 'r's in and take them out of weird places. 240let SchedRW = [WriteFAdd] in { 241def ADD_FST0r : FPST0rInst <MRM0r, "fadd\t$op">; 242def ADD_FrST0 : FPrST0Inst <MRM0r, "fadd\t{%st(0), $op|$op, st(0)}">; 243def ADD_FPrST0 : FPrST0PInst<MRM0r, "faddp\t$op">; 244def SUBR_FST0r : FPST0rInst <MRM5r, "fsubr\t$op">; 245def SUB_FrST0 : FPrST0Inst <MRM5r, "fsub{r}\t{%st(0), $op|$op, st(0)}">; 246def SUB_FPrST0 : FPrST0PInst<MRM5r, "fsub{r}p\t$op">; 247def SUB_FST0r : FPST0rInst <MRM4r, "fsub\t$op">; 248def SUBR_FrST0 : FPrST0Inst <MRM4r, "fsub{|r}\t{%st(0), $op|$op, st(0)}">; 249def SUBR_FPrST0 : FPrST0PInst<MRM4r, "fsub{|r}p\t$op">; 250} // SchedRW 251let SchedRW = [WriteFMul] in { 252def MUL_FST0r : FPST0rInst <MRM1r, "fmul\t$op">; 253def MUL_FrST0 : FPrST0Inst <MRM1r, "fmul\t{%st(0), $op|$op, st(0)}">; 254def MUL_FPrST0 : FPrST0PInst<MRM1r, "fmulp\t$op">; 255} // SchedRW 256let SchedRW = [WriteFDiv] in { 257def DIVR_FST0r : FPST0rInst <MRM7r, "fdivr\t$op">; 258def DIV_FrST0 : FPrST0Inst <MRM7r, "fdiv{r}\t{%st(0), $op|$op, st(0)}">; 259def DIV_FPrST0 : FPrST0PInst<MRM7r, "fdiv{r}p\t$op">; 260def DIV_FST0r : FPST0rInst <MRM6r, "fdiv\t$op">; 261def DIVR_FrST0 : FPrST0Inst <MRM6r, "fdiv{|r}\t{%st(0), $op|$op, st(0)}">; 262def DIVR_FPrST0 : FPrST0PInst<MRM6r, "fdiv{|r}p\t$op">; 263} // SchedRW 264 265def COM_FST0r : FPST0rInst <MRM2r, "fcom\t$op">; 266def COMP_FST0r : FPST0rInst <MRM3r, "fcomp\t$op">; 267 268// Unary operations. 269multiclass FPUnary<SDNode OpNode, Format fp, string asmstring> { 270def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW, 271 [(set RFP32:$dst, (OpNode RFP32:$src))]>; 272def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW, 273 [(set RFP64:$dst, (OpNode RFP64:$src))]>; 274def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW, 275 [(set RFP80:$dst, (OpNode RFP80:$src))]>; 276def _F : FPI<0xD9, fp, (outs), (ins), asmstring>; 277} 278 279let Defs = [FPSW] in { 280defm CHS : FPUnary<fneg, MRM_E0, "fchs">; 281defm ABS : FPUnary<fabs, MRM_E1, "fabs">; 282let SchedRW = [WriteFSqrt] in { 283defm SQRT: FPUnary<fsqrt,MRM_FA, "fsqrt">; 284} 285defm SIN : FPUnary<fsin, MRM_FE, "fsin">; 286defm COS : FPUnary<fcos, MRM_FF, "fcos">; 287 288let neverHasSideEffects = 1 in { 289def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>; 290def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>; 291def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>; 292} 293def TST_F : FPI<0xD9, MRM_E4, (outs), (ins), "ftst">; 294} // Defs = [FPSW] 295 296// Versions of FP instructions that take a single memory operand. Added for the 297// disassembler; remove as they are included with patterns elsewhere. 298def FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom{s}\t$src">; 299def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp{s}\t$src">; 300 301def FLDENVm : FPI<0xD9, MRM4m, (outs), (ins f32mem:$src), "fldenv\t$src">; 302def FSTENVm : FPI<0xD9, MRM6m, (outs f32mem:$dst), (ins), "fnstenv\t$dst">; 303 304def FICOM32m : FPI<0xDA, MRM2m, (outs), (ins i32mem:$src), "ficom{l}\t$src">; 305def FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">; 306 307def FCOM64m : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom{l}\t$src">; 308def FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp{l}\t$src">; 309 310def FRSTORm : FPI<0xDD, MRM4m, (outs f32mem:$dst), (ins), "frstor\t$dst">; 311def FSAVEm : FPI<0xDD, MRM6m, (outs f32mem:$dst), (ins), "fnsave\t$dst">; 312def FNSTSWm : FPI<0xDD, MRM7m, (outs f32mem:$dst), (ins), "fnstsw\t$dst">; 313 314def FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{s}\t$src">; 315def FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{s}\t$src">; 316 317def FBLDm : FPI<0xDF, MRM4m, (outs), (ins f32mem:$src), "fbld\t$src">; 318def FBSTPm : FPI<0xDF, MRM6m, (outs f32mem:$dst), (ins), "fbstp\t$dst">; 319 320// Floating point cmovs. 321class FpIf32CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 322 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32, HasCMov]>; 323class FpIf64CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 324 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64, HasCMov]>; 325 326multiclass FPCMov<PatLeaf cc> { 327 def _Fp32 : FpIf32CMov<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), 328 CondMovFP, 329 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, 330 cc, EFLAGS))]>; 331 def _Fp64 : FpIf64CMov<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), 332 CondMovFP, 333 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, 334 cc, EFLAGS))]>; 335 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), 336 CondMovFP, 337 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2, 338 cc, EFLAGS))]>, 339 Requires<[HasCMov]>; 340} 341 342let Defs = [FPSW] in { 343let Uses = [EFLAGS], Constraints = "$src1 = $dst" in { 344defm CMOVB : FPCMov<X86_COND_B>; 345defm CMOVBE : FPCMov<X86_COND_BE>; 346defm CMOVE : FPCMov<X86_COND_E>; 347defm CMOVP : FPCMov<X86_COND_P>; 348defm CMOVNB : FPCMov<X86_COND_AE>; 349defm CMOVNBE: FPCMov<X86_COND_A>; 350defm CMOVNE : FPCMov<X86_COND_NE>; 351defm CMOVNP : FPCMov<X86_COND_NP>; 352} // Uses = [EFLAGS], Constraints = "$src1 = $dst" 353 354let Predicates = [HasCMov] in { 355// These are not factored because there's no clean way to pass DA/DB. 356def CMOVB_F : FPI<0xDA, MRM0r, (outs RST:$op), (ins), 357 "fcmovb\t{$op, %st(0)|st(0), $op}">; 358def CMOVBE_F : FPI<0xDA, MRM2r, (outs RST:$op), (ins), 359 "fcmovbe\t{$op, %st(0)|st(0), $op}">; 360def CMOVE_F : FPI<0xDA, MRM1r, (outs RST:$op), (ins), 361 "fcmove\t{$op, %st(0)|st(0), $op}">; 362def CMOVP_F : FPI<0xDA, MRM3r, (outs RST:$op), (ins), 363 "fcmovu\t{$op, %st(0)|st(0), $op}">; 364def CMOVNB_F : FPI<0xDB, MRM0r, (outs RST:$op), (ins), 365 "fcmovnb\t{$op, %st(0)|st(0), $op}">; 366def CMOVNBE_F: FPI<0xDB, MRM2r, (outs RST:$op), (ins), 367 "fcmovnbe\t{$op, %st(0)|st(0), $op}">; 368def CMOVNE_F : FPI<0xDB, MRM1r, (outs RST:$op), (ins), 369 "fcmovne\t{$op, %st(0)|st(0), $op}">; 370def CMOVNP_F : FPI<0xDB, MRM3r, (outs RST:$op), (ins), 371 "fcmovnu\t{$op, %st(0)|st(0), $op}">; 372} // Predicates = [HasCMov] 373 374// Floating point loads & stores. 375let canFoldAsLoad = 1 in { 376def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP, 377 [(set RFP32:$dst, (loadf32 addr:$src))]>; 378let isReMaterializable = 1 in 379 def LD_Fp64m : FpIf64<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP, 380 [(set RFP64:$dst, (loadf64 addr:$src))]>; 381def LD_Fp80m : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP, 382 [(set RFP80:$dst, (loadf80 addr:$src))]>; 383} 384def LD_Fp32m64 : FpIf64<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP, 385 [(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>; 386def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP, 387 [(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>; 388def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP, 389 [(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>; 390def ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP, 391 [(set RFP32:$dst, (X86fild addr:$src, i16))]>; 392def ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP, 393 [(set RFP32:$dst, (X86fild addr:$src, i32))]>; 394def ILD_Fp64m32: FpIf32<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP, 395 [(set RFP32:$dst, (X86fild addr:$src, i64))]>; 396def ILD_Fp16m64: FpIf64<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP, 397 [(set RFP64:$dst, (X86fild addr:$src, i16))]>; 398def ILD_Fp32m64: FpIf64<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP, 399 [(set RFP64:$dst, (X86fild addr:$src, i32))]>; 400def ILD_Fp64m64: FpIf64<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP, 401 [(set RFP64:$dst, (X86fild addr:$src, i64))]>; 402def ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP, 403 [(set RFP80:$dst, (X86fild addr:$src, i16))]>; 404def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP, 405 [(set RFP80:$dst, (X86fild addr:$src, i32))]>; 406def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP, 407 [(set RFP80:$dst, (X86fild addr:$src, i64))]>; 408 409def ST_Fp32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, 410 [(store RFP32:$src, addr:$op)]>; 411def ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, 412 [(truncstoref32 RFP64:$src, addr:$op)]>; 413def ST_Fp64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, 414 [(store RFP64:$src, addr:$op)]>; 415def ST_Fp80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, 416 [(truncstoref32 RFP80:$src, addr:$op)]>; 417def ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, 418 [(truncstoref64 RFP80:$src, addr:$op)]>; 419// FST does not support 80-bit memory target; FSTP must be used. 420 421let mayStore = 1, neverHasSideEffects = 1 in { 422def ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>; 423def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>; 424def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>; 425def ST_FpP80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>; 426def ST_FpP80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>; 427} 428def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP, 429 [(store RFP80:$src, addr:$op)]>; 430let mayStore = 1, neverHasSideEffects = 1 in { 431def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>; 432def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>; 433def IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>; 434def IST_Fp16m64 : FpIf64<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>; 435def IST_Fp32m64 : FpIf64<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>; 436def IST_Fp64m64 : FpIf64<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>; 437def IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>; 438def IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, []>; 439def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>; 440} 441 442let mayLoad = 1, SchedRW = [WriteLoad] in { 443def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src", 444 IIC_FLD>; 445def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src", 446 IIC_FLD>; 447def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src", 448 IIC_FLD80>; 449def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src", 450 IIC_FILD>; 451def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src", 452 IIC_FILD>; 453def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src", 454 IIC_FILD>; 455} 456let mayStore = 1, SchedRW = [WriteStore] in { 457def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst", 458 IIC_FST>; 459def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst", 460 IIC_FST>; 461def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst", 462 IIC_FST>; 463def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst", 464 IIC_FST>; 465def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst", 466 IIC_FST80>; 467def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst", 468 IIC_FIST>; 469def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst", 470 IIC_FIST>; 471def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst", 472 IIC_FIST>; 473def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst", 474 IIC_FIST>; 475def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst", 476 IIC_FIST>; 477} 478 479// FISTTP requires SSE3 even though it's a FPStack op. 480let Predicates = [HasSSE3] in { 481def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, 482 [(X86fp_to_i16mem RFP32:$src, addr:$op)]>; 483def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, 484 [(X86fp_to_i32mem RFP32:$src, addr:$op)]>; 485def ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, 486 [(X86fp_to_i64mem RFP32:$src, addr:$op)]>; 487def ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, 488 [(X86fp_to_i16mem RFP64:$src, addr:$op)]>; 489def ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, 490 [(X86fp_to_i32mem RFP64:$src, addr:$op)]>; 491def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, 492 [(X86fp_to_i64mem RFP64:$src, addr:$op)]>; 493def ISTT_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, 494 [(X86fp_to_i16mem RFP80:$src, addr:$op)]>; 495def ISTT_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, 496 [(X86fp_to_i32mem RFP80:$src, addr:$op)]>; 497def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, 498 [(X86fp_to_i64mem RFP80:$src, addr:$op)]>; 499} // Predicates = [HasSSE3] 500 501let mayStore = 1, SchedRW = [WriteStore] in { 502def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst", 503 IIC_FST>; 504def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst", 505 IIC_FST>; 506def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), 507 "fisttp{ll}\t$dst", IIC_FST>; 508} 509 510// FP Stack manipulation instructions. 511let SchedRW = [WriteMove] in { 512def LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RST:$op), "fld\t$op", IIC_FLD>; 513def ST_Frr : FPI<0xDD, MRM2r, (outs), (ins RST:$op), "fst\t$op", IIC_FST>; 514def ST_FPrr : FPI<0xDD, MRM3r, (outs), (ins RST:$op), "fstp\t$op", IIC_FST>; 515def XCH_F : FPI<0xD9, MRM1r, (outs), (ins RST:$op), "fxch\t$op", IIC_FXCH>; 516} 517 518// Floating point constant loads. 519let isReMaterializable = 1 in { 520def LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, 521 [(set RFP32:$dst, fpimm0)]>; 522def LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, 523 [(set RFP32:$dst, fpimm1)]>; 524def LD_Fp064 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, 525 [(set RFP64:$dst, fpimm0)]>; 526def LD_Fp164 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, 527 [(set RFP64:$dst, fpimm1)]>; 528def LD_Fp080 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, 529 [(set RFP80:$dst, fpimm0)]>; 530def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, 531 [(set RFP80:$dst, fpimm1)]>; 532} 533 534let SchedRW = [WriteZero] in { 535def LD_F0 : FPI<0xD9, MRM_EE, (outs), (ins), "fldz", IIC_FLDZ>; 536def LD_F1 : FPI<0xD9, MRM_E8, (outs), (ins), "fld1", IIC_FIST>; 537} 538 539// Floating point compares. 540let SchedRW = [WriteFAdd] in { 541def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 542 [(set FPSW, (trunc (X86cmp RFP32:$lhs, RFP32:$rhs)))]>; 543def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 544 [(set FPSW, (trunc (X86cmp RFP64:$lhs, RFP64:$rhs)))]>; 545def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 546 [(set FPSW, (trunc (X86cmp RFP80:$lhs, RFP80:$rhs)))]>; 547} // SchedRW 548} // Defs = [FPSW] 549 550let SchedRW = [WriteFAdd] in { 551// CC = ST(0) cmp ST(i) 552let Defs = [EFLAGS, FPSW] in { 553def UCOM_FpIr32: FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 554 [(set EFLAGS, (X86cmp RFP32:$lhs, RFP32:$rhs))]>; 555def UCOM_FpIr64: FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 556 [(set EFLAGS, (X86cmp RFP64:$lhs, RFP64:$rhs))]>; 557def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 558 [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; 559} 560 561let Defs = [FPSW], Uses = [ST0] in { 562def UCOM_Fr : FPI<0xDD, MRM4r, // FPSW = cmp ST(0) with ST(i) 563 (outs), (ins RST:$reg), "fucom\t$reg", IIC_FUCOM>; 564def UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop 565 (outs), (ins RST:$reg), "fucomp\t$reg", IIC_FUCOM>; 566def UCOM_FPPr : FPI<0xDA, MRM_E9, // cmp ST(0) with ST(1), pop, pop 567 (outs), (ins), "fucompp", IIC_FUCOM>; 568} 569 570let Defs = [EFLAGS, FPSW], Uses = [ST0] in { 571def UCOM_FIr : FPI<0xDB, MRM5r, // CC = cmp ST(0) with ST(i) 572 (outs), (ins RST:$reg), "fucomi\t$reg", IIC_FUCOMI>; 573def UCOM_FIPr : FPI<0xDF, MRM5r, // CC = cmp ST(0) with ST(i), pop 574 (outs), (ins RST:$reg), "fucompi\t$reg", IIC_FUCOMI>; 575} 576 577let Defs = [EFLAGS, FPSW] in { 578def COM_FIr : FPI<0xDB, MRM6r, (outs), (ins RST:$reg), 579 "fcomi\t$reg", IIC_FCOMI>; 580def COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RST:$reg), 581 "fcompi\t$reg", IIC_FCOMI>; 582} 583} // SchedRW 584 585// Floating point flag ops. 586let SchedRW = [WriteALU] in { 587let Defs = [AX], Uses = [FPSW] in 588def FNSTSW16r : I<0xDF, MRM_E0, // AX = fp flags 589 (outs), (ins), "fnstsw\t{%ax|ax}", 590 [(set AX, (X86fp_stsw FPSW))], IIC_FNSTSW>; 591 592def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world 593 (outs), (ins i16mem:$dst), "fnstcw\t$dst", 594 [(X86fp_cwd_get16 addr:$dst)], IIC_FNSTCW>; 595} // SchedRW 596let mayLoad = 1 in 597def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16] 598 (outs), (ins i16mem:$dst), "fldcw\t$dst", [], IIC_FLDCW>, 599 Sched<[WriteLoad]>; 600 601// FPU control instructions 602let SchedRW = [WriteMicrocoded] in { 603let Defs = [FPSW] in 604def FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", [], IIC_FNINIT>; 605def FFREE : FPI<0xDD, MRM0r, (outs), (ins RST:$reg), 606 "ffree\t$reg", IIC_FFREE>; 607// Clear exceptions 608 609let Defs = [FPSW] in 610def FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", [], IIC_FNCLEX>; 611} // SchedRW 612 613// Operandless floating-point instructions for the disassembler. 614let SchedRW = [WriteMicrocoded] in { 615def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", [], IIC_WAIT>; 616 617def FNOP : I<0xD9, MRM_D0, (outs), (ins), "fnop", [], IIC_FNOP>; 618def FXAM : I<0xD9, MRM_E5, (outs), (ins), "fxam", [], IIC_FXAM>; 619def FLDL2T : I<0xD9, MRM_E9, (outs), (ins), "fldl2t", [], IIC_FLDL>; 620def FLDL2E : I<0xD9, MRM_EA, (outs), (ins), "fldl2e", [], IIC_FLDL>; 621def FLDPI : I<0xD9, MRM_EB, (outs), (ins), "fldpi", [], IIC_FLDL>; 622def FLDLG2 : I<0xD9, MRM_EC, (outs), (ins), "fldlg2", [], IIC_FLDL>; 623def FLDLN2 : I<0xD9, MRM_ED, (outs), (ins), "fldln2", [], IIC_FLDL>; 624def F2XM1 : I<0xD9, MRM_F0, (outs), (ins), "f2xm1", [], IIC_F2XM1>; 625def FYL2X : I<0xD9, MRM_F1, (outs), (ins), "fyl2x", [], IIC_FYL2X>; 626def FPTAN : I<0xD9, MRM_F2, (outs), (ins), "fptan", [], IIC_FPTAN>; 627def FPATAN : I<0xD9, MRM_F3, (outs), (ins), "fpatan", [], IIC_FPATAN>; 628def FXTRACT : I<0xD9, MRM_F4, (outs), (ins), "fxtract", [], IIC_FXTRACT>; 629def FPREM1 : I<0xD9, MRM_F5, (outs), (ins), "fprem1", [], IIC_FPREM1>; 630def FDECSTP : I<0xD9, MRM_F6, (outs), (ins), "fdecstp", [], IIC_FPSTP>; 631def FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", [], IIC_FPSTP>; 632def FPREM : I<0xD9, MRM_F8, (outs), (ins), "fprem", [], IIC_FPREM>; 633def FYL2XP1 : I<0xD9, MRM_F9, (outs), (ins), "fyl2xp1", [], IIC_FYL2XP1>; 634def FSINCOS : I<0xD9, MRM_FB, (outs), (ins), "fsincos", [], IIC_FSINCOS>; 635def FRNDINT : I<0xD9, MRM_FC, (outs), (ins), "frndint", [], IIC_FRNDINT>; 636def FSCALE : I<0xD9, MRM_FD, (outs), (ins), "fscale", [], IIC_FSCALE>; 637def FCOMPP : I<0xDE, MRM_D9, (outs), (ins), "fcompp", [], IIC_FCOMPP>; 638 639def FXSAVE : I<0xAE, MRM0m, (outs opaque512mem:$dst), (ins), 640 "fxsave\t$dst", [], IIC_FXSAVE>, TB; 641def FXSAVE64 : RI<0xAE, MRM0m, (outs opaque512mem:$dst), (ins), 642 "fxsave{q|64}\t$dst", [], IIC_FXSAVE>, TB, 643 Requires<[In64BitMode]>; 644def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaque512mem:$src), 645 "fxrstor\t$src", [], IIC_FXRSTOR>, TB; 646def FXRSTOR64 : RI<0xAE, MRM1m, (outs), (ins opaque512mem:$src), 647 "fxrstor{q|64}\t$src", [], IIC_FXRSTOR>, TB, 648 Requires<[In64BitMode]>; 649} // SchedRW 650 651//===----------------------------------------------------------------------===// 652// Non-Instruction Patterns 653//===----------------------------------------------------------------------===// 654 655// Required for RET of f32 / f64 / f80 values. 656def : Pat<(X86fld addr:$src, f32), (LD_Fp32m addr:$src)>; 657def : Pat<(X86fld addr:$src, f64), (LD_Fp64m addr:$src)>; 658def : Pat<(X86fld addr:$src, f80), (LD_Fp80m addr:$src)>; 659 660// Required for CALL which return f32 / f64 / f80 values. 661def : Pat<(X86fst RFP32:$src, addr:$op, f32), (ST_Fp32m addr:$op, RFP32:$src)>; 662def : Pat<(X86fst RFP64:$src, addr:$op, f32), (ST_Fp64m32 addr:$op, 663 RFP64:$src)>; 664def : Pat<(X86fst RFP64:$src, addr:$op, f64), (ST_Fp64m addr:$op, RFP64:$src)>; 665def : Pat<(X86fst RFP80:$src, addr:$op, f32), (ST_Fp80m32 addr:$op, 666 RFP80:$src)>; 667def : Pat<(X86fst RFP80:$src, addr:$op, f64), (ST_Fp80m64 addr:$op, 668 RFP80:$src)>; 669def : Pat<(X86fst RFP80:$src, addr:$op, f80), (ST_FpP80m addr:$op, 670 RFP80:$src)>; 671 672// Floating point constant -0.0 and -1.0 673def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStackf32]>; 674def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStackf32]>; 675def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStackf64]>; 676def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStackf64]>; 677def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>; 678def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>; 679 680// Used to conv. i64 to f64 since there isn't a SSE version. 681def : Pat<(X86fildflag addr:$src, i64), (ILD_Fp64m64 addr:$src)>; 682 683// FP extensions map onto simple pseudo-value conversions if they are to/from 684// the FP stack. 685def : Pat<(f64 (fextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP64)>, 686 Requires<[FPStackf32]>; 687def : Pat<(f80 (fextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP80)>, 688 Requires<[FPStackf32]>; 689def : Pat<(f80 (fextend RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP80)>, 690 Requires<[FPStackf64]>; 691 692// FP truncations map onto simple pseudo-value conversions if they are to/from 693// the FP stack. We have validated that only value-preserving truncations make 694// it through isel. 695def : Pat<(f32 (fround RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP32)>, 696 Requires<[FPStackf32]>; 697def : Pat<(f32 (fround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP32)>, 698 Requires<[FPStackf32]>; 699def : Pat<(f64 (fround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP64)>, 700 Requires<[FPStackf64]>; 701