X86InstrFragmentsSIMD.td revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338
1//===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file provides pattern fragments useful for SIMD instructions. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// MMX Pattern Fragments 16//===----------------------------------------------------------------------===// 17 18def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>; 19def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>; 20 21//===----------------------------------------------------------------------===// 22// SSE specific DAG Nodes. 23//===----------------------------------------------------------------------===// 24 25def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>, 26 SDTCisFP<0>, SDTCisInt<2> ]>; 27def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, 28 SDTCisFP<1>, SDTCisVT<3, i8>, 29 SDTCisVec<1>]>; 30 31def X86umin : SDNode<"X86ISD::UMIN", SDTIntBinOp>; 32def X86umax : SDNode<"X86ISD::UMAX", SDTIntBinOp>; 33def X86smin : SDNode<"X86ISD::SMIN", SDTIntBinOp>; 34def X86smax : SDNode<"X86ISD::SMAX", SDTIntBinOp>; 35 36def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>; 37def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>; 38 39// Commutative and Associative FMIN and FMAX. 40def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp, 41 [SDNPCommutative, SDNPAssociative]>; 42def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp, 43 [SDNPCommutative, SDNPAssociative]>; 44 45def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp, 46 [SDNPCommutative, SDNPAssociative]>; 47def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp, 48 [SDNPCommutative, SDNPAssociative]>; 49def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp, 50 [SDNPCommutative, SDNPAssociative]>; 51def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp, 52 [SDNPCommutative, SDNPAssociative]>; 53def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>; 54def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>; 55def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>; 56def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>; 57def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>; 58def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>; 59def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>; 60def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>; 61def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>; 62def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>; 63def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>; 64//def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>; 65def X86pshufb : SDNode<"X86ISD::PSHUFB", 66 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 67 SDTCisSameAs<0,2>]>>; 68def X86andnp : SDNode<"X86ISD::ANDNP", 69 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 70 SDTCisSameAs<0,2>]>>; 71def X86psign : SDNode<"X86ISD::PSIGN", 72 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 73 SDTCisSameAs<0,2>]>>; 74def X86pextrb : SDNode<"X86ISD::PEXTRB", 75 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>; 76def X86pextrw : SDNode<"X86ISD::PEXTRW", 77 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>; 78def X86pinsrb : SDNode<"X86ISD::PINSRB", 79 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, 80 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>; 81def X86pinsrw : SDNode<"X86ISD::PINSRW", 82 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>, 83 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>; 84def X86insrtps : SDNode<"X86ISD::INSERTPS", 85 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>, 86 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>; 87def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL", 88 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>; 89 90def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad, 91 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 92 93def X86vzext : SDNode<"X86ISD::VZEXT", 94 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 95 SDTCisInt<0>, SDTCisInt<1>, 96 SDTCisOpSmallerThanOp<1, 0>]>>; 97 98def X86vsext : SDNode<"X86ISD::VSEXT", 99 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 100 SDTCisInt<0>, SDTCisInt<1>, 101 SDTCisOpSmallerThanOp<1, 0>]>>; 102 103def X86vtrunc : SDNode<"X86ISD::VTRUNC", 104 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 105 SDTCisInt<0>, SDTCisInt<1>, 106 SDTCisOpSmallerThanOp<0, 1>]>>; 107def X86trunc : SDNode<"X86ISD::TRUNC", 108 SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>, 109 SDTCisOpSmallerThanOp<0, 1>]>>; 110 111def X86vtruncm : SDNode<"X86ISD::VTRUNCM", 112 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, 113 SDTCisInt<0>, SDTCisInt<1>, 114 SDTCisVec<2>, SDTCisInt<2>, 115 SDTCisOpSmallerThanOp<0, 2>]>>; 116def X86vfpext : SDNode<"X86ISD::VFPEXT", 117 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 118 SDTCisFP<0>, SDTCisFP<1>, 119 SDTCisOpSmallerThanOp<1, 0>]>>; 120def X86vfpround: SDNode<"X86ISD::VFPROUND", 121 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 122 SDTCisFP<0>, SDTCisFP<1>, 123 SDTCisOpSmallerThanOp<0, 1>]>>; 124 125def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>; 126def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>; 127def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>; 128def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>; 129def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>; 130 131def X86IntCmpMask : SDTypeProfile<1, 2, 132 [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>; 133def X86pcmpeqm : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>; 134def X86pcmpgtm : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>; 135 136def X86CmpMaskCC : 137 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisInt<0>, SDTCisVec<1>, 138 SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; 139def X86CmpMaskCCScalar : 140 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; 141 142def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>; 143def X86cmpmu : SDNode<"X86ISD::CMPMU", X86CmpMaskCC>; 144def X86cmpms : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalar>; 145 146def X86vshl : SDNode<"X86ISD::VSHL", 147 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 148 SDTCisVec<2>]>>; 149def X86vsrl : SDNode<"X86ISD::VSRL", 150 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 151 SDTCisVec<2>]>>; 152def X86vsra : SDNode<"X86ISD::VSRA", 153 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 154 SDTCisVec<2>]>>; 155 156def X86vshli : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>; 157def X86vsrli : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>; 158def X86vsrai : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>; 159 160def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 161 SDTCisVec<1>, 162 SDTCisSameAs<2, 1>]>; 163def X86subus : SDNode<"X86ISD::SUBUS", SDTIntBinOp>; 164def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>; 165def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>; 166def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>; 167def X86testm : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>, 168 SDTCisVec<1>, 169 SDTCisSameAs<2, 1>]>>; 170def X86testnm : SDNode<"X86ISD::TESTNM", SDTypeProfile<1, 2, [SDTCisVec<0>, 171 SDTCisVec<1>, 172 SDTCisSameAs<2, 1>]>>; 173def X86select : SDNode<"X86ISD::SELECT" , SDTSelect>; 174 175def X86pmuludq : SDNode<"X86ISD::PMULUDQ", 176 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, 177 SDTCisSameAs<1,2>]>>; 178 179// Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get 180// translated into one of the target nodes below during lowering. 181// Note: this is a work in progress... 182def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>; 183def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 184 SDTCisSameAs<0,2>]>; 185def SDTShuff3Op : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 186 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>; 187 188def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>, 189 SDTCisSameAs<0,1>, SDTCisInt<2>]>; 190def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 191 SDTCisSameAs<0,2>, SDTCisInt<3>]>; 192 193def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>; 194def SDTVBroadcastm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>]>; 195 196def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 197 SDTCisSameAs<1,2>, SDTCisVT<3, i32>]>; 198 199def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>, 200 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>; 201 202def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>; 203 204def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>; 205def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>; 206def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>; 207 208def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>; 209 210def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>; 211def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>; 212def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>; 213 214def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>; 215def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>; 216 217def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>; 218def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>; 219def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>; 220 221def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>; 222def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>; 223 224def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>; 225def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>; 226 227def X86VPermilp : SDNode<"X86ISD::VPERMILP", SDTShuff2OpI>; 228def X86VPermv : SDNode<"X86ISD::VPERMV", SDTShuff2Op>; 229def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>; 230def X86VPermv3 : SDNode<"X86ISD::VPERMV3", SDTShuff3Op>; 231def X86VPermiv3 : SDNode<"X86ISD::VPERMIV3", SDTShuff3Op>; 232 233def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>; 234 235def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>; 236def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>; 237def X86Vinsert : SDNode<"X86ISD::VINSERT", SDTypeProfile<1, 3, 238 [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>; 239def X86Vextract : SDNode<"X86ISD::VEXTRACT", SDTypeProfile<1, 2, 240 [SDTCisVec<1>, SDTCisPtrTy<2>]>, []>; 241 242def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>; 243def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>; 244def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFma>; 245def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>; 246def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFma>; 247def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFma>; 248def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFma>; 249 250def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 251 SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>, 252 SDTCisVT<4, i8>]>; 253def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 254 SDTCisVT<2, v16i8>, SDTCisVT<3, i32>, 255 SDTCisVT<4, v16i8>, SDTCisVT<5, i32>, 256 SDTCisVT<6, i8>]>; 257 258def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>; 259def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>; 260 261//===----------------------------------------------------------------------===// 262// SSE Complex Patterns 263//===----------------------------------------------------------------------===// 264 265// These are 'extloads' from a scalar to the low element of a vector, zeroing 266// the top elements. These are used for the SSE 'ss' and 'sd' instruction 267// forms. 268def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [], 269 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, 270 SDNPWantRoot]>; 271def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [], 272 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, 273 SDNPWantRoot]>; 274 275def ssmem : Operand<v4f32> { 276 let PrintMethod = "printf32mem"; 277 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm); 278 let ParserMatchClass = X86Mem32AsmOperand; 279 let OperandType = "OPERAND_MEMORY"; 280} 281def sdmem : Operand<v2f64> { 282 let PrintMethod = "printf64mem"; 283 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm); 284 let ParserMatchClass = X86Mem64AsmOperand; 285 let OperandType = "OPERAND_MEMORY"; 286} 287 288//===----------------------------------------------------------------------===// 289// SSE pattern fragments 290//===----------------------------------------------------------------------===// 291 292// 128-bit load pattern fragments 293// NOTE: all 128-bit integer vector loads are promoted to v2i64 294def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>; 295def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>; 296def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>; 297 298// 256-bit load pattern fragments 299// NOTE: all 256-bit integer vector loads are promoted to v4i64 300def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>; 301def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>; 302def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>; 303 304// 512-bit load pattern fragments 305def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>; 306def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>; 307def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>; 308def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>; 309 310// 128-/256-/512-bit extload pattern fragments 311def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>; 312def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>; 313def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>; 314 315// Like 'store', but always requires 128-bit vector alignment. 316def alignedstore : PatFrag<(ops node:$val, node:$ptr), 317 (store node:$val, node:$ptr), [{ 318 return cast<StoreSDNode>(N)->getAlignment() >= 16; 319}]>; 320 321// Like 'store', but always requires 256-bit vector alignment. 322def alignedstore256 : PatFrag<(ops node:$val, node:$ptr), 323 (store node:$val, node:$ptr), [{ 324 return cast<StoreSDNode>(N)->getAlignment() >= 32; 325}]>; 326 327// Like 'store', but always requires 512-bit vector alignment. 328def alignedstore512 : PatFrag<(ops node:$val, node:$ptr), 329 (store node:$val, node:$ptr), [{ 330 return cast<StoreSDNode>(N)->getAlignment() >= 64; 331}]>; 332 333// Like 'load', but always requires 128-bit vector alignment. 334def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 335 return cast<LoadSDNode>(N)->getAlignment() >= 16; 336}]>; 337 338// Like 'X86vzload', but always requires 128-bit vector alignment. 339def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{ 340 return cast<MemSDNode>(N)->getAlignment() >= 16; 341}]>; 342 343// Like 'load', but always requires 256-bit vector alignment. 344def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 345 return cast<LoadSDNode>(N)->getAlignment() >= 32; 346}]>; 347 348// Like 'load', but always requires 512-bit vector alignment. 349def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 350 return cast<LoadSDNode>(N)->getAlignment() >= 64; 351}]>; 352 353def alignedloadfsf32 : PatFrag<(ops node:$ptr), 354 (f32 (alignedload node:$ptr))>; 355def alignedloadfsf64 : PatFrag<(ops node:$ptr), 356 (f64 (alignedload node:$ptr))>; 357 358// 128-bit aligned load pattern fragments 359// NOTE: all 128-bit integer vector loads are promoted to v2i64 360def alignedloadv4f32 : PatFrag<(ops node:$ptr), 361 (v4f32 (alignedload node:$ptr))>; 362def alignedloadv2f64 : PatFrag<(ops node:$ptr), 363 (v2f64 (alignedload node:$ptr))>; 364def alignedloadv2i64 : PatFrag<(ops node:$ptr), 365 (v2i64 (alignedload node:$ptr))>; 366 367// 256-bit aligned load pattern fragments 368// NOTE: all 256-bit integer vector loads are promoted to v4i64 369def alignedloadv8f32 : PatFrag<(ops node:$ptr), 370 (v8f32 (alignedload256 node:$ptr))>; 371def alignedloadv4f64 : PatFrag<(ops node:$ptr), 372 (v4f64 (alignedload256 node:$ptr))>; 373def alignedloadv4i64 : PatFrag<(ops node:$ptr), 374 (v4i64 (alignedload256 node:$ptr))>; 375 376// 512-bit aligned load pattern fragments 377def alignedloadv16f32 : PatFrag<(ops node:$ptr), 378 (v16f32 (alignedload512 node:$ptr))>; 379def alignedloadv16i32 : PatFrag<(ops node:$ptr), 380 (v16i32 (alignedload512 node:$ptr))>; 381def alignedloadv8f64 : PatFrag<(ops node:$ptr), 382 (v8f64 (alignedload512 node:$ptr))>; 383def alignedloadv8i64 : PatFrag<(ops node:$ptr), 384 (v8i64 (alignedload512 node:$ptr))>; 385 386// Like 'load', but uses special alignment checks suitable for use in 387// memory operands in most SSE instructions, which are required to 388// be naturally aligned on some targets but not on others. If the subtarget 389// allows unaligned accesses, match any load, though this may require 390// setting a feature bit in the processor (on startup, for example). 391// Opteron 10h and later implement such a feature. 392def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 393 return Subtarget->hasVectorUAMem() 394 || cast<LoadSDNode>(N)->getAlignment() >= 16; 395}]>; 396 397def memop4 : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 398 return Subtarget->hasVectorUAMem() 399 || cast<LoadSDNode>(N)->getAlignment() >= 4; 400}]>; 401 402def memop8 : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 403 return Subtarget->hasVectorUAMem() 404 || cast<LoadSDNode>(N)->getAlignment() >= 8; 405}]>; 406 407def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>; 408def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>; 409 410// 128-bit memop pattern fragments 411// NOTE: all 128-bit integer vector loads are promoted to v2i64 412def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>; 413def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>; 414def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>; 415 416// 256-bit memop pattern fragments 417// NOTE: all 256-bit integer vector loads are promoted to v4i64 418def memopv8f32 : PatFrag<(ops node:$ptr), (v8f32 (memop node:$ptr))>; 419def memopv4f64 : PatFrag<(ops node:$ptr), (v4f64 (memop node:$ptr))>; 420def memopv4i64 : PatFrag<(ops node:$ptr), (v4i64 (memop node:$ptr))>; 421 422// 512-bit memop pattern fragments 423def memopv16f32 : PatFrag<(ops node:$ptr), (v16f32 (memop4 node:$ptr))>; 424def memopv8f64 : PatFrag<(ops node:$ptr), (v8f64 (memop8 node:$ptr))>; 425def memopv16i32 : PatFrag<(ops node:$ptr), (v16i32 (memop4 node:$ptr))>; 426def memopv8i64 : PatFrag<(ops node:$ptr), (v8i64 (memop8 node:$ptr))>; 427 428// SSSE3 uses MMX registers for some instructions. They aren't aligned on a 429// 16-byte boundary. 430// FIXME: 8 byte alignment for mmx reads is not required 431def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 432 return cast<LoadSDNode>(N)->getAlignment() >= 8; 433}]>; 434 435def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>; 436 437// MOVNT Support 438// Like 'store', but requires the non-temporal bit to be set 439def nontemporalstore : PatFrag<(ops node:$val, node:$ptr), 440 (st node:$val, node:$ptr), [{ 441 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) 442 return ST->isNonTemporal(); 443 return false; 444}]>; 445 446def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr), 447 (st node:$val, node:$ptr), [{ 448 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) 449 return ST->isNonTemporal() && !ST->isTruncatingStore() && 450 ST->getAddressingMode() == ISD::UNINDEXED && 451 ST->getAlignment() >= 16; 452 return false; 453}]>; 454 455def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr), 456 (st node:$val, node:$ptr), [{ 457 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) 458 return ST->isNonTemporal() && 459 ST->getAlignment() < 16; 460 return false; 461}]>; 462 463// 128-bit bitconvert pattern fragments 464def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>; 465def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>; 466def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>; 467def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>; 468def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>; 469def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>; 470 471// 256-bit bitconvert pattern fragments 472def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>; 473def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>; 474def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>; 475def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>; 476def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>; 477 478// 512-bit bitconvert pattern fragments 479def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>; 480def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>; 481def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>; 482def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>; 483 484def vzmovl_v2i64 : PatFrag<(ops node:$src), 485 (bitconvert (v2i64 (X86vzmovl 486 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>; 487def vzmovl_v4i32 : PatFrag<(ops node:$src), 488 (bitconvert (v4i32 (X86vzmovl 489 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>; 490 491def vzload_v2i64 : PatFrag<(ops node:$src), 492 (bitconvert (v2i64 (X86vzload node:$src)))>; 493 494 495def fp32imm0 : PatLeaf<(f32 fpimm), [{ 496 return N->isExactlyValue(+0.0); 497}]>; 498 499def I8Imm : SDNodeXForm<imm, [{ 500 // Transformation function: get the low 8 bits. 501 return getI8Imm((uint8_t)N->getZExtValue()); 502}]>; 503 504def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>; 505def FROUND_CURRENT : ImmLeaf<i32, [{ return Imm == 4; }]>; 506 507// BYTE_imm - Transform bit immediates into byte immediates. 508def BYTE_imm : SDNodeXForm<imm, [{ 509 // Transformation function: imm >> 3 510 return getI32Imm(N->getZExtValue() >> 3); 511}]>; 512 513// EXTRACT_get_vextract128_imm xform function: convert extract_subvector index 514// to VEXTRACTF128/VEXTRACTI128 imm. 515def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{ 516 return getI8Imm(X86::getExtractVEXTRACT128Immediate(N)); 517}]>; 518 519// INSERT_get_vinsert128_imm xform function: convert insert_subvector index to 520// VINSERTF128/VINSERTI128 imm. 521def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{ 522 return getI8Imm(X86::getInsertVINSERT128Immediate(N)); 523}]>; 524 525// EXTRACT_get_vextract256_imm xform function: convert extract_subvector index 526// to VEXTRACTF64x4 imm. 527def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{ 528 return getI8Imm(X86::getExtractVEXTRACT256Immediate(N)); 529}]>; 530 531// INSERT_get_vinsert256_imm xform function: convert insert_subvector index to 532// VINSERTF64x4 imm. 533def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{ 534 return getI8Imm(X86::getInsertVINSERT256Immediate(N)); 535}]>; 536 537def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index), 538 (extract_subvector node:$bigvec, 539 node:$index), [{ 540 return X86::isVEXTRACT128Index(N); 541}], EXTRACT_get_vextract128_imm>; 542 543def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec, 544 node:$index), 545 (insert_subvector node:$bigvec, node:$smallvec, 546 node:$index), [{ 547 return X86::isVINSERT128Index(N); 548}], INSERT_get_vinsert128_imm>; 549 550 551def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index), 552 (extract_subvector node:$bigvec, 553 node:$index), [{ 554 return X86::isVEXTRACT256Index(N); 555}], EXTRACT_get_vextract256_imm>; 556 557def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec, 558 node:$index), 559 (insert_subvector node:$bigvec, node:$smallvec, 560 node:$index), [{ 561 return X86::isVINSERT256Index(N); 562}], INSERT_get_vinsert256_imm>; 563 564